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KVM: VMX: Support for injecting software exceptions
[linux-2.6/mini2440.git] / arch / x86 / kvm / vmx.c
blob1d974c1eaa7d92e8fd6ee5d846caabace4018171
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
40
41 static int bypass_guest_pf = 1;
42 module_param(bypass_guest_pf, bool, 0);
43
44 static int enable_vpid = 1;
45 module_param(enable_vpid, bool, 0);
46
47 static int flexpriority_enabled = 1;
48 module_param(flexpriority_enabled, bool, 0);
49
50 static int enable_ept = 1;
51 module_param(enable_ept, bool, 0);
52
53 static int emulate_invalid_guest_state = 0;
54 module_param(emulate_invalid_guest_state, bool, 0);
55
56 struct vmcs {
57 u32 revision_id;
58 u32 abort;
59 char data[0];
60 };
61
62 struct vcpu_vmx {
63 struct kvm_vcpu vcpu;
64 struct list_head local_vcpus_link;
65 unsigned long host_rsp;
66 int launched;
67 u8 fail;
68 u32 idt_vectoring_info;
69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
71 int nmsrs;
72 int save_nmsrs;
73 int msr_offset_efer;
74 #ifdef CONFIG_X86_64
75 int msr_offset_kernel_gs_base;
76 #endif
77 struct vmcs *vmcs;
78 struct {
79 int loaded;
80 u16 fs_sel, gs_sel, ldt_sel;
81 int gs_ldt_reload_needed;
82 int fs_reload_needed;
83 int guest_efer_loaded;
84 } host_state;
85 struct {
86 struct {
87 bool pending;
88 u8 vector;
89 unsigned rip;
90 } irq;
91 } rmode;
92 int vpid;
93 bool emulation_required;
94
95 /* Support for vnmi-less CPUs */
96 int soft_vnmi_blocked;
97 ktime_t entry_time;
98 s64 vnmi_blocked_time;
99 };
100
101 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
102 {
103 return container_of(vcpu, struct vcpu_vmx, vcpu);
104 }
105
106 static int init_rmode(struct kvm *kvm);
107 static u64 construct_eptp(unsigned long root_hpa);
108
109 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
110 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
111 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
112
113 static struct page *vmx_io_bitmap_a;
114 static struct page *vmx_io_bitmap_b;
115 static struct page *vmx_msr_bitmap;
116
117 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
118 static DEFINE_SPINLOCK(vmx_vpid_lock);
119
120 static struct vmcs_config {
121 int size;
122 int order;
123 u32 revision_id;
124 u32 pin_based_exec_ctrl;
125 u32 cpu_based_exec_ctrl;
126 u32 cpu_based_2nd_exec_ctrl;
127 u32 vmexit_ctrl;
128 u32 vmentry_ctrl;
129 } vmcs_config;
130
131 static struct vmx_capability {
132 u32 ept;
133 u32 vpid;
134 } vmx_capability;
135
136 #define VMX_SEGMENT_FIELD(seg) \
137 [VCPU_SREG_##seg] = { \
138 .selector = GUEST_##seg##_SELECTOR, \
139 .base = GUEST_##seg##_BASE, \
140 .limit = GUEST_##seg##_LIMIT, \
141 .ar_bytes = GUEST_##seg##_AR_BYTES, \
142 }
143
144 static struct kvm_vmx_segment_field {
145 unsigned selector;
146 unsigned base;
147 unsigned limit;
148 unsigned ar_bytes;
149 } kvm_vmx_segment_fields[] = {
150 VMX_SEGMENT_FIELD(CS),
151 VMX_SEGMENT_FIELD(DS),
152 VMX_SEGMENT_FIELD(ES),
153 VMX_SEGMENT_FIELD(FS),
154 VMX_SEGMENT_FIELD(GS),
155 VMX_SEGMENT_FIELD(SS),
156 VMX_SEGMENT_FIELD(TR),
157 VMX_SEGMENT_FIELD(LDTR),
158 };
159
160 /*
161 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
162 * away by decrementing the array size.
163 */
164 static const u32 vmx_msr_index[] = {
165 #ifdef CONFIG_X86_64
166 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
167 #endif
168 MSR_EFER, MSR_K6_STAR,
169 };
170 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
171
172 static void load_msrs(struct kvm_msr_entry *e, int n)
173 {
174 int i;
175
176 for (i = 0; i < n; ++i)
177 wrmsrl(e[i].index, e[i].data);
178 }
179
180 static void save_msrs(struct kvm_msr_entry *e, int n)
181 {
182 int i;
183
184 for (i = 0; i < n; ++i)
185 rdmsrl(e[i].index, e[i].data);
186 }
187
188 static inline int is_page_fault(u32 intr_info)
189 {
190 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
191 INTR_INFO_VALID_MASK)) ==
192 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
193 }
194
195 static inline int is_no_device(u32 intr_info)
196 {
197 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
198 INTR_INFO_VALID_MASK)) ==
199 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
200 }
201
202 static inline int is_invalid_opcode(u32 intr_info)
203 {
204 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
205 INTR_INFO_VALID_MASK)) ==
206 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
207 }
208
209 static inline int is_external_interrupt(u32 intr_info)
210 {
211 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
212 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
213 }
214
215 static inline int cpu_has_vmx_msr_bitmap(void)
216 {
217 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
218 }
219
220 static inline int cpu_has_vmx_tpr_shadow(void)
221 {
222 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
223 }
224
225 static inline int vm_need_tpr_shadow(struct kvm *kvm)
226 {
227 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
228 }
229
230 static inline int cpu_has_secondary_exec_ctrls(void)
231 {
232 return (vmcs_config.cpu_based_exec_ctrl &
233 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
234 }
235
236 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
237 {
238 return flexpriority_enabled
239 && (vmcs_config.cpu_based_2nd_exec_ctrl &
240 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
241 }
242
243 static inline int cpu_has_vmx_invept_individual_addr(void)
244 {
245 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
246 }
247
248 static inline int cpu_has_vmx_invept_context(void)
249 {
250 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
251 }
252
253 static inline int cpu_has_vmx_invept_global(void)
254 {
255 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
256 }
257
258 static inline int cpu_has_vmx_ept(void)
259 {
260 return (vmcs_config.cpu_based_2nd_exec_ctrl &
261 SECONDARY_EXEC_ENABLE_EPT);
262 }
263
264 static inline int vm_need_ept(void)
265 {
266 return (cpu_has_vmx_ept() && enable_ept);
267 }
268
269 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
270 {
271 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
272 (irqchip_in_kernel(kvm)));
273 }
274
275 static inline int cpu_has_vmx_vpid(void)
276 {
277 return (vmcs_config.cpu_based_2nd_exec_ctrl &
278 SECONDARY_EXEC_ENABLE_VPID);
279 }
280
281 static inline int cpu_has_virtual_nmis(void)
282 {
283 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
284 }
285
286 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
287 {
288 int i;
289
290 for (i = 0; i < vmx->nmsrs; ++i)
291 if (vmx->guest_msrs[i].index == msr)
292 return i;
293 return -1;
294 }
295
296 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
297 {
298 struct {
299 u64 vpid : 16;
300 u64 rsvd : 48;
301 u64 gva;
302 } operand = { vpid, 0, gva };
303
304 asm volatile (__ex(ASM_VMX_INVVPID)
305 /* CF==1 or ZF==1 --> rc = -1 */
306 "; ja 1f ; ud2 ; 1:"
307 : : "a"(&operand), "c"(ext) : "cc", "memory");
308 }
309
310 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
311 {
312 struct {
313 u64 eptp, gpa;
314 } operand = {eptp, gpa};
315
316 asm volatile (__ex(ASM_VMX_INVEPT)
317 /* CF==1 or ZF==1 --> rc = -1 */
318 "; ja 1f ; ud2 ; 1:\n"
319 : : "a" (&operand), "c" (ext) : "cc", "memory");
320 }
321
322 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
323 {
324 int i;
325
326 i = __find_msr_index(vmx, msr);
327 if (i >= 0)
328 return &vmx->guest_msrs[i];
329 return NULL;
330 }
331
332 static void vmcs_clear(struct vmcs *vmcs)
333 {
334 u64 phys_addr = __pa(vmcs);
335 u8 error;
336
337 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
338 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
339 : "cc", "memory");
340 if (error)
341 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
342 vmcs, phys_addr);
343 }
344
345 static void __vcpu_clear(void *arg)
346 {
347 struct vcpu_vmx *vmx = arg;
348 int cpu = raw_smp_processor_id();
349
350 if (vmx->vcpu.cpu == cpu)
351 vmcs_clear(vmx->vmcs);
352 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
353 per_cpu(current_vmcs, cpu) = NULL;
354 rdtscll(vmx->vcpu.arch.host_tsc);
355 list_del(&vmx->local_vcpus_link);
356 vmx->vcpu.cpu = -1;
357 vmx->launched = 0;
358 }
359
360 static void vcpu_clear(struct vcpu_vmx *vmx)
361 {
362 if (vmx->vcpu.cpu == -1)
363 return;
364 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
365 }
366
367 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
368 {
369 if (vmx->vpid == 0)
370 return;
371
372 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
373 }
374
375 static inline void ept_sync_global(void)
376 {
377 if (cpu_has_vmx_invept_global())
378 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
379 }
380
381 static inline void ept_sync_context(u64 eptp)
382 {
383 if (vm_need_ept()) {
384 if (cpu_has_vmx_invept_context())
385 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
386 else
387 ept_sync_global();
388 }
389 }
390
391 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
392 {
393 if (vm_need_ept()) {
394 if (cpu_has_vmx_invept_individual_addr())
395 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
396 eptp, gpa);
397 else
398 ept_sync_context(eptp);
399 }
400 }
401
402 static unsigned long vmcs_readl(unsigned long field)
403 {
404 unsigned long value;
405
406 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
407 : "=a"(value) : "d"(field) : "cc");
408 return value;
409 }
410
411 static u16 vmcs_read16(unsigned long field)
412 {
413 return vmcs_readl(field);
414 }
415
416 static u32 vmcs_read32(unsigned long field)
417 {
418 return vmcs_readl(field);
419 }
420
421 static u64 vmcs_read64(unsigned long field)
422 {
423 #ifdef CONFIG_X86_64
424 return vmcs_readl(field);
425 #else
426 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
427 #endif
428 }
429
430 static noinline void vmwrite_error(unsigned long field, unsigned long value)
431 {
432 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
433 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
434 dump_stack();
435 }
436
437 static void vmcs_writel(unsigned long field, unsigned long value)
438 {
439 u8 error;
440
441 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
442 : "=q"(error) : "a"(value), "d"(field) : "cc");
443 if (unlikely(error))
444 vmwrite_error(field, value);
445 }
446
447 static void vmcs_write16(unsigned long field, u16 value)
448 {
449 vmcs_writel(field, value);
450 }
451
452 static void vmcs_write32(unsigned long field, u32 value)
453 {
454 vmcs_writel(field, value);
455 }
456
457 static void vmcs_write64(unsigned long field, u64 value)
458 {
459 vmcs_writel(field, value);
460 #ifndef CONFIG_X86_64
461 asm volatile ("");
462 vmcs_writel(field+1, value >> 32);
463 #endif
464 }
465
466 static void vmcs_clear_bits(unsigned long field, u32 mask)
467 {
468 vmcs_writel(field, vmcs_readl(field) & ~mask);
469 }
470
471 static void vmcs_set_bits(unsigned long field, u32 mask)
472 {
473 vmcs_writel(field, vmcs_readl(field) | mask);
474 }
475
476 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
477 {
478 u32 eb;
479
480 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
481 if (!vcpu->fpu_active)
482 eb |= 1u << NM_VECTOR;
483 if (vcpu->guest_debug.enabled)
484 eb |= 1u << DB_VECTOR;
485 if (vcpu->arch.rmode.active)
486 eb = ~0;
487 if (vm_need_ept())
488 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
489 vmcs_write32(EXCEPTION_BITMAP, eb);
490 }
491
492 static void reload_tss(void)
493 {
494 /*
495 * VT restores TR but not its size. Useless.
496 */
497 struct descriptor_table gdt;
498 struct desc_struct *descs;
499
500 kvm_get_gdt(&gdt);
501 descs = (void *)gdt.base;
502 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
503 load_TR_desc();
504 }
505
506 static void load_transition_efer(struct vcpu_vmx *vmx)
507 {
508 int efer_offset = vmx->msr_offset_efer;
509 u64 host_efer = vmx->host_msrs[efer_offset].data;
510 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
511 u64 ignore_bits;
512
513 if (efer_offset < 0)
514 return;
515 /*
516 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
517 * outside long mode
518 */
519 ignore_bits = EFER_NX | EFER_SCE;
520 #ifdef CONFIG_X86_64
521 ignore_bits |= EFER_LMA | EFER_LME;
522 /* SCE is meaningful only in long mode on Intel */
523 if (guest_efer & EFER_LMA)
524 ignore_bits &= ~(u64)EFER_SCE;
525 #endif
526 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
527 return;
528
529 vmx->host_state.guest_efer_loaded = 1;
530 guest_efer &= ~ignore_bits;
531 guest_efer |= host_efer & ignore_bits;
532 wrmsrl(MSR_EFER, guest_efer);
533 vmx->vcpu.stat.efer_reload++;
534 }
535
536 static void reload_host_efer(struct vcpu_vmx *vmx)
537 {
538 if (vmx->host_state.guest_efer_loaded) {
539 vmx->host_state.guest_efer_loaded = 0;
540 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
541 }
542 }
543
544 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
545 {
546 struct vcpu_vmx *vmx = to_vmx(vcpu);
547
548 if (vmx->host_state.loaded)
549 return;
550
551 vmx->host_state.loaded = 1;
552 /*
553 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
554 * allow segment selectors with cpl > 0 or ti == 1.
555 */
556 vmx->host_state.ldt_sel = kvm_read_ldt();
557 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
558 vmx->host_state.fs_sel = kvm_read_fs();
559 if (!(vmx->host_state.fs_sel & 7)) {
560 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
561 vmx->host_state.fs_reload_needed = 0;
562 } else {
563 vmcs_write16(HOST_FS_SELECTOR, 0);
564 vmx->host_state.fs_reload_needed = 1;
565 }
566 vmx->host_state.gs_sel = kvm_read_gs();
567 if (!(vmx->host_state.gs_sel & 7))
568 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
569 else {
570 vmcs_write16(HOST_GS_SELECTOR, 0);
571 vmx->host_state.gs_ldt_reload_needed = 1;
572 }
573
574 #ifdef CONFIG_X86_64
575 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
576 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
577 #else
578 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
579 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
580 #endif
581
582 #ifdef CONFIG_X86_64
583 if (is_long_mode(&vmx->vcpu))
584 save_msrs(vmx->host_msrs +
585 vmx->msr_offset_kernel_gs_base, 1);
586
587 #endif
588 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
589 load_transition_efer(vmx);
590 }
591
592 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
593 {
594 unsigned long flags;
595
596 if (!vmx->host_state.loaded)
597 return;
598
599 ++vmx->vcpu.stat.host_state_reload;
600 vmx->host_state.loaded = 0;
601 if (vmx->host_state.fs_reload_needed)
602 kvm_load_fs(vmx->host_state.fs_sel);
603 if (vmx->host_state.gs_ldt_reload_needed) {
604 kvm_load_ldt(vmx->host_state.ldt_sel);
605 /*
606 * If we have to reload gs, we must take care to
607 * preserve our gs base.
608 */
609 local_irq_save(flags);
610 kvm_load_gs(vmx->host_state.gs_sel);
611 #ifdef CONFIG_X86_64
612 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
613 #endif
614 local_irq_restore(flags);
615 }
616 reload_tss();
617 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
618 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
619 reload_host_efer(vmx);
620 }
621
622 static void vmx_load_host_state(struct vcpu_vmx *vmx)
623 {
624 preempt_disable();
625 __vmx_load_host_state(vmx);
626 preempt_enable();
627 }
628
629 /*
630 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
631 * vcpu mutex is already taken.
632 */
633 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
634 {
635 struct vcpu_vmx *vmx = to_vmx(vcpu);
636 u64 phys_addr = __pa(vmx->vmcs);
637 u64 tsc_this, delta, new_offset;
638
639 if (vcpu->cpu != cpu) {
640 vcpu_clear(vmx);
641 kvm_migrate_timers(vcpu);
642 vpid_sync_vcpu_all(vmx);
643 local_irq_disable();
644 list_add(&vmx->local_vcpus_link,
645 &per_cpu(vcpus_on_cpu, cpu));
646 local_irq_enable();
647 }
648
649 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
650 u8 error;
651
652 per_cpu(current_vmcs, cpu) = vmx->vmcs;
653 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
654 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
655 : "cc");
656 if (error)
657 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
658 vmx->vmcs, phys_addr);
659 }
660
661 if (vcpu->cpu != cpu) {
662 struct descriptor_table dt;
663 unsigned long sysenter_esp;
664
665 vcpu->cpu = cpu;
666 /*
667 * Linux uses per-cpu TSS and GDT, so set these when switching
668 * processors.
669 */
670 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
671 kvm_get_gdt(&dt);
672 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
673
674 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
675 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
676
677 /*
678 * Make sure the time stamp counter is monotonous.
679 */
680 rdtscll(tsc_this);
681 if (tsc_this < vcpu->arch.host_tsc) {
682 delta = vcpu->arch.host_tsc - tsc_this;
683 new_offset = vmcs_read64(TSC_OFFSET) + delta;
684 vmcs_write64(TSC_OFFSET, new_offset);
685 }
686 }
687 }
688
689 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
690 {
691 __vmx_load_host_state(to_vmx(vcpu));
692 }
693
694 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
695 {
696 if (vcpu->fpu_active)
697 return;
698 vcpu->fpu_active = 1;
699 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
700 if (vcpu->arch.cr0 & X86_CR0_TS)
701 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
702 update_exception_bitmap(vcpu);
703 }
704
705 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
706 {
707 if (!vcpu->fpu_active)
708 return;
709 vcpu->fpu_active = 0;
710 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
711 update_exception_bitmap(vcpu);
712 }
713
714 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
715 {
716 return vmcs_readl(GUEST_RFLAGS);
717 }
718
719 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
720 {
721 if (vcpu->arch.rmode.active)
722 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
723 vmcs_writel(GUEST_RFLAGS, rflags);
724 }
725
726 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
727 {
728 unsigned long rip;
729 u32 interruptibility;
730
731 rip = kvm_rip_read(vcpu);
732 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
733 kvm_rip_write(vcpu, rip);
734
735 /*
736 * We emulated an instruction, so temporary interrupt blocking
737 * should be removed, if set.
738 */
739 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
740 if (interruptibility & 3)
741 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
742 interruptibility & ~3);
743 vcpu->arch.interrupt_window_open = 1;
744 }
745
746 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
747 bool has_error_code, u32 error_code)
748 {
749 struct vcpu_vmx *vmx = to_vmx(vcpu);
750 u32 intr_info = nr | INTR_INFO_VALID_MASK;
751
752 if (has_error_code) {
753 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
754 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
755 }
756
757 if (vcpu->arch.rmode.active) {
758 vmx->rmode.irq.pending = true;
759 vmx->rmode.irq.vector = nr;
760 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
761 if (nr == BP_VECTOR || nr == OF_VECTOR)
762 vmx->rmode.irq.rip++;
763 intr_info |= INTR_TYPE_SOFT_INTR;
764 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
765 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
766 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
767 return;
768 }
769
770 if (nr == BP_VECTOR || nr == OF_VECTOR) {
771 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
772 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
773 } else
774 intr_info |= INTR_TYPE_HARD_EXCEPTION;
775
776 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
777 }
778
779 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
780 {
781 return false;
782 }
783
784 /*
785 * Swap MSR entry in host/guest MSR entry array.
786 */
787 #ifdef CONFIG_X86_64
788 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
789 {
790 struct kvm_msr_entry tmp;
791
792 tmp = vmx->guest_msrs[to];
793 vmx->guest_msrs[to] = vmx->guest_msrs[from];
794 vmx->guest_msrs[from] = tmp;
795 tmp = vmx->host_msrs[to];
796 vmx->host_msrs[to] = vmx->host_msrs[from];
797 vmx->host_msrs[from] = tmp;
798 }
799 #endif
800
801 /*
802 * Set up the vmcs to automatically save and restore system
803 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
804 * mode, as fiddling with msrs is very expensive.
805 */
806 static void setup_msrs(struct vcpu_vmx *vmx)
807 {
808 int save_nmsrs;
809
810 vmx_load_host_state(vmx);
811 save_nmsrs = 0;
812 #ifdef CONFIG_X86_64
813 if (is_long_mode(&vmx->vcpu)) {
814 int index;
815
816 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
817 if (index >= 0)
818 move_msr_up(vmx, index, save_nmsrs++);
819 index = __find_msr_index(vmx, MSR_LSTAR);
820 if (index >= 0)
821 move_msr_up(vmx, index, save_nmsrs++);
822 index = __find_msr_index(vmx, MSR_CSTAR);
823 if (index >= 0)
824 move_msr_up(vmx, index, save_nmsrs++);
825 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
826 if (index >= 0)
827 move_msr_up(vmx, index, save_nmsrs++);
828 /*
829 * MSR_K6_STAR is only needed on long mode guests, and only
830 * if efer.sce is enabled.
831 */
832 index = __find_msr_index(vmx, MSR_K6_STAR);
833 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
834 move_msr_up(vmx, index, save_nmsrs++);
835 }
836 #endif
837 vmx->save_nmsrs = save_nmsrs;
838
839 #ifdef CONFIG_X86_64
840 vmx->msr_offset_kernel_gs_base =
841 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
842 #endif
843 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
844 }
845
846 /*
847 * reads and returns guest's timestamp counter "register"
848 * guest_tsc = host_tsc + tsc_offset -- 21.3
849 */
850 static u64 guest_read_tsc(void)
851 {
852 u64 host_tsc, tsc_offset;
853
854 rdtscll(host_tsc);
855 tsc_offset = vmcs_read64(TSC_OFFSET);
856 return host_tsc + tsc_offset;
857 }
858
859 /*
860 * writes 'guest_tsc' into guest's timestamp counter "register"
861 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
862 */
863 static void guest_write_tsc(u64 guest_tsc)
864 {
865 u64 host_tsc;
866
867 rdtscll(host_tsc);
868 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
869 }
870
871 /*
872 * Reads an msr value (of 'msr_index') into 'pdata'.
873 * Returns 0 on success, non-0 otherwise.
874 * Assumes vcpu_load() was already called.
875 */
876 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
877 {
878 u64 data;
879 struct kvm_msr_entry *msr;
880
881 if (!pdata) {
882 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
883 return -EINVAL;
884 }
885
886 switch (msr_index) {
887 #ifdef CONFIG_X86_64
888 case MSR_FS_BASE:
889 data = vmcs_readl(GUEST_FS_BASE);
890 break;
891 case MSR_GS_BASE:
892 data = vmcs_readl(GUEST_GS_BASE);
893 break;
894 case MSR_EFER:
895 return kvm_get_msr_common(vcpu, msr_index, pdata);
896 #endif
897 case MSR_IA32_TIME_STAMP_COUNTER:
898 data = guest_read_tsc();
899 break;
900 case MSR_IA32_SYSENTER_CS:
901 data = vmcs_read32(GUEST_SYSENTER_CS);
902 break;
903 case MSR_IA32_SYSENTER_EIP:
904 data = vmcs_readl(GUEST_SYSENTER_EIP);
905 break;
906 case MSR_IA32_SYSENTER_ESP:
907 data = vmcs_readl(GUEST_SYSENTER_ESP);
908 break;
909 default:
910 vmx_load_host_state(to_vmx(vcpu));
911 msr = find_msr_entry(to_vmx(vcpu), msr_index);
912 if (msr) {
913 data = msr->data;
914 break;
915 }
916 return kvm_get_msr_common(vcpu, msr_index, pdata);
917 }
918
919 *pdata = data;
920 return 0;
921 }
922
923 /*
924 * Writes msr value into into the appropriate "register".
925 * Returns 0 on success, non-0 otherwise.
926 * Assumes vcpu_load() was already called.
927 */
928 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
929 {
930 struct vcpu_vmx *vmx = to_vmx(vcpu);
931 struct kvm_msr_entry *msr;
932 int ret = 0;
933
934 switch (msr_index) {
935 #ifdef CONFIG_X86_64
936 case MSR_EFER:
937 vmx_load_host_state(vmx);
938 ret = kvm_set_msr_common(vcpu, msr_index, data);
939 break;
940 case MSR_FS_BASE:
941 vmcs_writel(GUEST_FS_BASE, data);
942 break;
943 case MSR_GS_BASE:
944 vmcs_writel(GUEST_GS_BASE, data);
945 break;
946 #endif
947 case MSR_IA32_SYSENTER_CS:
948 vmcs_write32(GUEST_SYSENTER_CS, data);
949 break;
950 case MSR_IA32_SYSENTER_EIP:
951 vmcs_writel(GUEST_SYSENTER_EIP, data);
952 break;
953 case MSR_IA32_SYSENTER_ESP:
954 vmcs_writel(GUEST_SYSENTER_ESP, data);
955 break;
956 case MSR_IA32_TIME_STAMP_COUNTER:
957 guest_write_tsc(data);
958 break;
959 case MSR_P6_PERFCTR0:
960 case MSR_P6_PERFCTR1:
961 case MSR_P6_EVNTSEL0:
962 case MSR_P6_EVNTSEL1:
963 /*
964 * Just discard all writes to the performance counters; this
965 * should keep both older linux and windows 64-bit guests
966 * happy
967 */
968 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
969
970 break;
971 case MSR_IA32_CR_PAT:
972 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
973 vmcs_write64(GUEST_IA32_PAT, data);
974 vcpu->arch.pat = data;
975 break;
976 }
977 /* Otherwise falls through to kvm_set_msr_common */
978 default:
979 vmx_load_host_state(vmx);
980 msr = find_msr_entry(vmx, msr_index);
981 if (msr) {
982 msr->data = data;
983 break;
984 }
985 ret = kvm_set_msr_common(vcpu, msr_index, data);
986 }
987
988 return ret;
989 }
990
991 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
992 {
993 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
994 switch (reg) {
995 case VCPU_REGS_RSP:
996 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
997 break;
998 case VCPU_REGS_RIP:
999 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1000 break;
1001 default:
1002 break;
1003 }
1004 }
1005
1006 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
1007 {
1008 unsigned long dr7 = 0x400;
1009 int old_singlestep;
1010
1011 old_singlestep = vcpu->guest_debug.singlestep;
1012
1013 vcpu->guest_debug.enabled = dbg->enabled;
1014 if (vcpu->guest_debug.enabled) {
1015 int i;
1016
1017 dr7 |= 0x200; /* exact */
1018 for (i = 0; i < 4; ++i) {
1019 if (!dbg->breakpoints[i].enabled)
1020 continue;
1021 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
1022 dr7 |= 2 << (i*2); /* global enable */
1023 dr7 |= 0 << (i*4+16); /* execution breakpoint */
1024 }
1025
1026 vcpu->guest_debug.singlestep = dbg->singlestep;
1027 } else
1028 vcpu->guest_debug.singlestep = 0;
1029
1030 if (old_singlestep && !vcpu->guest_debug.singlestep) {
1031 unsigned long flags;
1032
1033 flags = vmcs_readl(GUEST_RFLAGS);
1034 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1035 vmcs_writel(GUEST_RFLAGS, flags);
1036 }
1037
1038 update_exception_bitmap(vcpu);
1039 vmcs_writel(GUEST_DR7, dr7);
1040
1041 return 0;
1042 }
1043
1044 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1045 {
1046 if (!vcpu->arch.interrupt.pending)
1047 return -1;
1048 return vcpu->arch.interrupt.nr;
1049 }
1050
1051 static __init int cpu_has_kvm_support(void)
1052 {
1053 return cpu_has_vmx();
1054 }
1055
1056 static __init int vmx_disabled_by_bios(void)
1057 {
1058 u64 msr;
1059
1060 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1061 return (msr & (FEATURE_CONTROL_LOCKED |
1062 FEATURE_CONTROL_VMXON_ENABLED))
1063 == FEATURE_CONTROL_LOCKED;
1064 /* locked but not enabled */
1065 }
1066
1067 static void hardware_enable(void *garbage)
1068 {
1069 int cpu = raw_smp_processor_id();
1070 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1071 u64 old;
1072
1073 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1074 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1075 if ((old & (FEATURE_CONTROL_LOCKED |
1076 FEATURE_CONTROL_VMXON_ENABLED))
1077 != (FEATURE_CONTROL_LOCKED |
1078 FEATURE_CONTROL_VMXON_ENABLED))
1079 /* enable and lock */
1080 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1081 FEATURE_CONTROL_LOCKED |
1082 FEATURE_CONTROL_VMXON_ENABLED);
1083 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1084 asm volatile (ASM_VMX_VMXON_RAX
1085 : : "a"(&phys_addr), "m"(phys_addr)
1086 : "memory", "cc");
1087 }
1088
1089 static void vmclear_local_vcpus(void)
1090 {
1091 int cpu = raw_smp_processor_id();
1092 struct vcpu_vmx *vmx, *n;
1093
1094 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1095 local_vcpus_link)
1096 __vcpu_clear(vmx);
1097 }
1098
1099
1100 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1101 * tricks.
1102 */
1103 static void kvm_cpu_vmxoff(void)
1104 {
1105 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1106 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1107 }
1108
1109 static void hardware_disable(void *garbage)
1110 {
1111 vmclear_local_vcpus();
1112 kvm_cpu_vmxoff();
1113 }
1114
1115 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1116 u32 msr, u32 *result)
1117 {
1118 u32 vmx_msr_low, vmx_msr_high;
1119 u32 ctl = ctl_min | ctl_opt;
1120
1121 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1122
1123 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1124 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1125
1126 /* Ensure minimum (required) set of control bits are supported. */
1127 if (ctl_min & ~ctl)
1128 return -EIO;
1129
1130 *result = ctl;
1131 return 0;
1132 }
1133
1134 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1135 {
1136 u32 vmx_msr_low, vmx_msr_high;
1137 u32 min, opt, min2, opt2;
1138 u32 _pin_based_exec_control = 0;
1139 u32 _cpu_based_exec_control = 0;
1140 u32 _cpu_based_2nd_exec_control = 0;
1141 u32 _vmexit_control = 0;
1142 u32 _vmentry_control = 0;
1143
1144 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1145 opt = PIN_BASED_VIRTUAL_NMIS;
1146 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1147 &_pin_based_exec_control) < 0)
1148 return -EIO;
1149
1150 min = CPU_BASED_HLT_EXITING |
1151 #ifdef CONFIG_X86_64
1152 CPU_BASED_CR8_LOAD_EXITING |
1153 CPU_BASED_CR8_STORE_EXITING |
1154 #endif
1155 CPU_BASED_CR3_LOAD_EXITING |
1156 CPU_BASED_CR3_STORE_EXITING |
1157 CPU_BASED_USE_IO_BITMAPS |
1158 CPU_BASED_MOV_DR_EXITING |
1159 CPU_BASED_USE_TSC_OFFSETING |
1160 CPU_BASED_INVLPG_EXITING;
1161 opt = CPU_BASED_TPR_SHADOW |
1162 CPU_BASED_USE_MSR_BITMAPS |
1163 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1164 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1165 &_cpu_based_exec_control) < 0)
1166 return -EIO;
1167 #ifdef CONFIG_X86_64
1168 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1169 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1170 ~CPU_BASED_CR8_STORE_EXITING;
1171 #endif
1172 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1173 min2 = 0;
1174 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1175 SECONDARY_EXEC_WBINVD_EXITING |
1176 SECONDARY_EXEC_ENABLE_VPID |
1177 SECONDARY_EXEC_ENABLE_EPT;
1178 if (adjust_vmx_controls(min2, opt2,
1179 MSR_IA32_VMX_PROCBASED_CTLS2,
1180 &_cpu_based_2nd_exec_control) < 0)
1181 return -EIO;
1182 }
1183 #ifndef CONFIG_X86_64
1184 if (!(_cpu_based_2nd_exec_control &
1185 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1186 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1187 #endif
1188 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1189 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1190 enabled */
1191 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1192 CPU_BASED_CR3_STORE_EXITING |
1193 CPU_BASED_INVLPG_EXITING);
1194 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1195 &_cpu_based_exec_control) < 0)
1196 return -EIO;
1197 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1198 vmx_capability.ept, vmx_capability.vpid);
1199 }
1200
1201 min = 0;
1202 #ifdef CONFIG_X86_64
1203 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1204 #endif
1205 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1206 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1207 &_vmexit_control) < 0)
1208 return -EIO;
1209
1210 min = 0;
1211 opt = VM_ENTRY_LOAD_IA32_PAT;
1212 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1213 &_vmentry_control) < 0)
1214 return -EIO;
1215
1216 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1217
1218 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1219 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1220 return -EIO;
1221
1222 #ifdef CONFIG_X86_64
1223 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1224 if (vmx_msr_high & (1u<<16))
1225 return -EIO;
1226 #endif
1227
1228 /* Require Write-Back (WB) memory type for VMCS accesses. */
1229 if (((vmx_msr_high >> 18) & 15) != 6)
1230 return -EIO;
1231
1232 vmcs_conf->size = vmx_msr_high & 0x1fff;
1233 vmcs_conf->order = get_order(vmcs_config.size);
1234 vmcs_conf->revision_id = vmx_msr_low;
1235
1236 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1237 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1238 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1239 vmcs_conf->vmexit_ctrl = _vmexit_control;
1240 vmcs_conf->vmentry_ctrl = _vmentry_control;
1241
1242 return 0;
1243 }
1244
1245 static struct vmcs *alloc_vmcs_cpu(int cpu)
1246 {
1247 int node = cpu_to_node(cpu);
1248 struct page *pages;
1249 struct vmcs *vmcs;
1250
1251 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1252 if (!pages)
1253 return NULL;
1254 vmcs = page_address(pages);
1255 memset(vmcs, 0, vmcs_config.size);
1256 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1257 return vmcs;
1258 }
1259
1260 static struct vmcs *alloc_vmcs(void)
1261 {
1262 return alloc_vmcs_cpu(raw_smp_processor_id());
1263 }
1264
1265 static void free_vmcs(struct vmcs *vmcs)
1266 {
1267 free_pages((unsigned long)vmcs, vmcs_config.order);
1268 }
1269
1270 static void free_kvm_area(void)
1271 {
1272 int cpu;
1273
1274 for_each_online_cpu(cpu)
1275 free_vmcs(per_cpu(vmxarea, cpu));
1276 }
1277
1278 static __init int alloc_kvm_area(void)
1279 {
1280 int cpu;
1281
1282 for_each_online_cpu(cpu) {
1283 struct vmcs *vmcs;
1284
1285 vmcs = alloc_vmcs_cpu(cpu);
1286 if (!vmcs) {
1287 free_kvm_area();
1288 return -ENOMEM;
1289 }
1290
1291 per_cpu(vmxarea, cpu) = vmcs;
1292 }
1293 return 0;
1294 }
1295
1296 static __init int hardware_setup(void)
1297 {
1298 if (setup_vmcs_config(&vmcs_config) < 0)
1299 return -EIO;
1300
1301 if (boot_cpu_has(X86_FEATURE_NX))
1302 kvm_enable_efer_bits(EFER_NX);
1303
1304 return alloc_kvm_area();
1305 }
1306
1307 static __exit void hardware_unsetup(void)
1308 {
1309 free_kvm_area();
1310 }
1311
1312 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1313 {
1314 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1315
1316 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1317 vmcs_write16(sf->selector, save->selector);
1318 vmcs_writel(sf->base, save->base);
1319 vmcs_write32(sf->limit, save->limit);
1320 vmcs_write32(sf->ar_bytes, save->ar);
1321 } else {
1322 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1323 << AR_DPL_SHIFT;
1324 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1325 }
1326 }
1327
1328 static void enter_pmode(struct kvm_vcpu *vcpu)
1329 {
1330 unsigned long flags;
1331 struct vcpu_vmx *vmx = to_vmx(vcpu);
1332
1333 vmx->emulation_required = 1;
1334 vcpu->arch.rmode.active = 0;
1335
1336 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1337 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1338 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1339
1340 flags = vmcs_readl(GUEST_RFLAGS);
1341 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1342 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1343 vmcs_writel(GUEST_RFLAGS, flags);
1344
1345 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1346 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1347
1348 update_exception_bitmap(vcpu);
1349
1350 if (emulate_invalid_guest_state)
1351 return;
1352
1353 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1354 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1355 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1356 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1357
1358 vmcs_write16(GUEST_SS_SELECTOR, 0);
1359 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1360
1361 vmcs_write16(GUEST_CS_SELECTOR,
1362 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1363 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1364 }
1365
1366 static gva_t rmode_tss_base(struct kvm *kvm)
1367 {
1368 if (!kvm->arch.tss_addr) {
1369 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1370 kvm->memslots[0].npages - 3;
1371 return base_gfn << PAGE_SHIFT;
1372 }
1373 return kvm->arch.tss_addr;
1374 }
1375
1376 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1377 {
1378 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1379
1380 save->selector = vmcs_read16(sf->selector);
1381 save->base = vmcs_readl(sf->base);
1382 save->limit = vmcs_read32(sf->limit);
1383 save->ar = vmcs_read32(sf->ar_bytes);
1384 vmcs_write16(sf->selector, save->base >> 4);
1385 vmcs_write32(sf->base, save->base & 0xfffff);
1386 vmcs_write32(sf->limit, 0xffff);
1387 vmcs_write32(sf->ar_bytes, 0xf3);
1388 }
1389
1390 static void enter_rmode(struct kvm_vcpu *vcpu)
1391 {
1392 unsigned long flags;
1393 struct vcpu_vmx *vmx = to_vmx(vcpu);
1394
1395 vmx->emulation_required = 1;
1396 vcpu->arch.rmode.active = 1;
1397
1398 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1399 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1400
1401 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1402 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1403
1404 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1405 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1406
1407 flags = vmcs_readl(GUEST_RFLAGS);
1408 vcpu->arch.rmode.save_iopl
1409 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1410
1411 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1412
1413 vmcs_writel(GUEST_RFLAGS, flags);
1414 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1415 update_exception_bitmap(vcpu);
1416
1417 if (emulate_invalid_guest_state)
1418 goto continue_rmode;
1419
1420 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1421 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1422 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1423
1424 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1425 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1426 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1427 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1428 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1429
1430 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1431 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1432 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1433 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1434
1435 continue_rmode:
1436 kvm_mmu_reset_context(vcpu);
1437 init_rmode(vcpu->kvm);
1438 }
1439
1440 #ifdef CONFIG_X86_64
1441
1442 static void enter_lmode(struct kvm_vcpu *vcpu)
1443 {
1444 u32 guest_tr_ar;
1445
1446 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1447 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1448 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1449 __func__);
1450 vmcs_write32(GUEST_TR_AR_BYTES,
1451 (guest_tr_ar & ~AR_TYPE_MASK)
1452 | AR_TYPE_BUSY_64_TSS);
1453 }
1454
1455 vcpu->arch.shadow_efer |= EFER_LMA;
1456
1457 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1458 vmcs_write32(VM_ENTRY_CONTROLS,
1459 vmcs_read32(VM_ENTRY_CONTROLS)
1460 | VM_ENTRY_IA32E_MODE);
1461 }
1462
1463 static void exit_lmode(struct kvm_vcpu *vcpu)
1464 {
1465 vcpu->arch.shadow_efer &= ~EFER_LMA;
1466
1467 vmcs_write32(VM_ENTRY_CONTROLS,
1468 vmcs_read32(VM_ENTRY_CONTROLS)
1469 & ~VM_ENTRY_IA32E_MODE);
1470 }
1471
1472 #endif
1473
1474 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1475 {
1476 vpid_sync_vcpu_all(to_vmx(vcpu));
1477 if (vm_need_ept())
1478 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1479 }
1480
1481 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1482 {
1483 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1484 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1485 }
1486
1487 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1488 {
1489 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1490 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1491 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1492 return;
1493 }
1494 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1495 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1496 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1497 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1498 }
1499 }
1500
1501 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1502
1503 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1504 unsigned long cr0,
1505 struct kvm_vcpu *vcpu)
1506 {
1507 if (!(cr0 & X86_CR0_PG)) {
1508 /* From paging/starting to nonpaging */
1509 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1510 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1511 (CPU_BASED_CR3_LOAD_EXITING |
1512 CPU_BASED_CR3_STORE_EXITING));
1513 vcpu->arch.cr0 = cr0;
1514 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1515 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1516 *hw_cr0 &= ~X86_CR0_WP;
1517 } else if (!is_paging(vcpu)) {
1518 /* From nonpaging to paging */
1519 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1520 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1521 ~(CPU_BASED_CR3_LOAD_EXITING |
1522 CPU_BASED_CR3_STORE_EXITING));
1523 vcpu->arch.cr0 = cr0;
1524 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1525 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1526 *hw_cr0 &= ~X86_CR0_WP;
1527 }
1528 }
1529
1530 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1531 struct kvm_vcpu *vcpu)
1532 {
1533 if (!is_paging(vcpu)) {
1534 *hw_cr4 &= ~X86_CR4_PAE;
1535 *hw_cr4 |= X86_CR4_PSE;
1536 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1537 *hw_cr4 &= ~X86_CR4_PAE;
1538 }
1539
1540 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1541 {
1542 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1543 KVM_VM_CR0_ALWAYS_ON;
1544
1545 vmx_fpu_deactivate(vcpu);
1546
1547 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1548 enter_pmode(vcpu);
1549
1550 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1551 enter_rmode(vcpu);
1552
1553 #ifdef CONFIG_X86_64
1554 if (vcpu->arch.shadow_efer & EFER_LME) {
1555 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1556 enter_lmode(vcpu);
1557 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1558 exit_lmode(vcpu);
1559 }
1560 #endif
1561
1562 if (vm_need_ept())
1563 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1564
1565 vmcs_writel(CR0_READ_SHADOW, cr0);
1566 vmcs_writel(GUEST_CR0, hw_cr0);
1567 vcpu->arch.cr0 = cr0;
1568
1569 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1570 vmx_fpu_activate(vcpu);
1571 }
1572
1573 static u64 construct_eptp(unsigned long root_hpa)
1574 {
1575 u64 eptp;
1576
1577 /* TODO write the value reading from MSR */
1578 eptp = VMX_EPT_DEFAULT_MT |
1579 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1580 eptp |= (root_hpa & PAGE_MASK);
1581
1582 return eptp;
1583 }
1584
1585 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1586 {
1587 unsigned long guest_cr3;
1588 u64 eptp;
1589
1590 guest_cr3 = cr3;
1591 if (vm_need_ept()) {
1592 eptp = construct_eptp(cr3);
1593 vmcs_write64(EPT_POINTER, eptp);
1594 ept_sync_context(eptp);
1595 ept_load_pdptrs(vcpu);
1596 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1597 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1598 }
1599
1600 vmx_flush_tlb(vcpu);
1601 vmcs_writel(GUEST_CR3, guest_cr3);
1602 if (vcpu->arch.cr0 & X86_CR0_PE)
1603 vmx_fpu_deactivate(vcpu);
1604 }
1605
1606 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1607 {
1608 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1609 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1610
1611 vcpu->arch.cr4 = cr4;
1612 if (vm_need_ept())
1613 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1614
1615 vmcs_writel(CR4_READ_SHADOW, cr4);
1616 vmcs_writel(GUEST_CR4, hw_cr4);
1617 }
1618
1619 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1620 {
1621 struct vcpu_vmx *vmx = to_vmx(vcpu);
1622 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1623
1624 vcpu->arch.shadow_efer = efer;
1625 if (!msr)
1626 return;
1627 if (efer & EFER_LMA) {
1628 vmcs_write32(VM_ENTRY_CONTROLS,
1629 vmcs_read32(VM_ENTRY_CONTROLS) |
1630 VM_ENTRY_IA32E_MODE);
1631 msr->data = efer;
1632
1633 } else {
1634 vmcs_write32(VM_ENTRY_CONTROLS,
1635 vmcs_read32(VM_ENTRY_CONTROLS) &
1636 ~VM_ENTRY_IA32E_MODE);
1637
1638 msr->data = efer & ~EFER_LME;
1639 }
1640 setup_msrs(vmx);
1641 }
1642
1643 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1644 {
1645 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1646
1647 return vmcs_readl(sf->base);
1648 }
1649
1650 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1651 struct kvm_segment *var, int seg)
1652 {
1653 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1654 u32 ar;
1655
1656 var->base = vmcs_readl(sf->base);
1657 var->limit = vmcs_read32(sf->limit);
1658 var->selector = vmcs_read16(sf->selector);
1659 ar = vmcs_read32(sf->ar_bytes);
1660 if (ar & AR_UNUSABLE_MASK)
1661 ar = 0;
1662 var->type = ar & 15;
1663 var->s = (ar >> 4) & 1;
1664 var->dpl = (ar >> 5) & 3;
1665 var->present = (ar >> 7) & 1;
1666 var->avl = (ar >> 12) & 1;
1667 var->l = (ar >> 13) & 1;
1668 var->db = (ar >> 14) & 1;
1669 var->g = (ar >> 15) & 1;
1670 var->unusable = (ar >> 16) & 1;
1671 }
1672
1673 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1674 {
1675 struct kvm_segment kvm_seg;
1676
1677 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1678 return 0;
1679
1680 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1681 return 3;
1682
1683 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1684 return kvm_seg.selector & 3;
1685 }
1686
1687 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1688 {
1689 u32 ar;
1690
1691 if (var->unusable)
1692 ar = 1 << 16;
1693 else {
1694 ar = var->type & 15;
1695 ar |= (var->s & 1) << 4;
1696 ar |= (var->dpl & 3) << 5;
1697 ar |= (var->present & 1) << 7;
1698 ar |= (var->avl & 1) << 12;
1699 ar |= (var->l & 1) << 13;
1700 ar |= (var->db & 1) << 14;
1701 ar |= (var->g & 1) << 15;
1702 }
1703 if (ar == 0) /* a 0 value means unusable */
1704 ar = AR_UNUSABLE_MASK;
1705
1706 return ar;
1707 }
1708
1709 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1710 struct kvm_segment *var, int seg)
1711 {
1712 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1713 u32 ar;
1714
1715 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1716 vcpu->arch.rmode.tr.selector = var->selector;
1717 vcpu->arch.rmode.tr.base = var->base;
1718 vcpu->arch.rmode.tr.limit = var->limit;
1719 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1720 return;
1721 }
1722 vmcs_writel(sf->base, var->base);
1723 vmcs_write32(sf->limit, var->limit);
1724 vmcs_write16(sf->selector, var->selector);
1725 if (vcpu->arch.rmode.active && var->s) {
1726 /*
1727 * Hack real-mode segments into vm86 compatibility.
1728 */
1729 if (var->base == 0xffff0000 && var->selector == 0xf000)
1730 vmcs_writel(sf->base, 0xf0000);
1731 ar = 0xf3;
1732 } else
1733 ar = vmx_segment_access_rights(var);
1734 vmcs_write32(sf->ar_bytes, ar);
1735 }
1736
1737 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1738 {
1739 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1740
1741 *db = (ar >> 14) & 1;
1742 *l = (ar >> 13) & 1;
1743 }
1744
1745 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1746 {
1747 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1748 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1749 }
1750
1751 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1752 {
1753 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1754 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1755 }
1756
1757 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1758 {
1759 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1760 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1761 }
1762
1763 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1764 {
1765 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1766 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1767 }
1768
1769 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1770 {
1771 struct kvm_segment var;
1772 u32 ar;
1773
1774 vmx_get_segment(vcpu, &var, seg);
1775 ar = vmx_segment_access_rights(&var);
1776
1777 if (var.base != (var.selector << 4))
1778 return false;
1779 if (var.limit != 0xffff)
1780 return false;
1781 if (ar != 0xf3)
1782 return false;
1783
1784 return true;
1785 }
1786
1787 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1788 {
1789 struct kvm_segment cs;
1790 unsigned int cs_rpl;
1791
1792 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1793 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1794
1795 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1796 return false;
1797 if (!cs.s)
1798 return false;
1799 if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1800 if (cs.dpl > cs_rpl)
1801 return false;
1802 } else if (cs.type & AR_TYPE_CODE_MASK) {
1803 if (cs.dpl != cs_rpl)
1804 return false;
1805 }
1806 if (!cs.present)
1807 return false;
1808
1809 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1810 return true;
1811 }
1812
1813 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1814 {
1815 struct kvm_segment ss;
1816 unsigned int ss_rpl;
1817
1818 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1819 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1820
1821 if ((ss.type != 3) || (ss.type != 7))
1822 return false;
1823 if (!ss.s)
1824 return false;
1825 if (ss.dpl != ss_rpl) /* DPL != RPL */
1826 return false;
1827 if (!ss.present)
1828 return false;
1829
1830 return true;
1831 }
1832
1833 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1834 {
1835 struct kvm_segment var;
1836 unsigned int rpl;
1837
1838 vmx_get_segment(vcpu, &var, seg);
1839 rpl = var.selector & SELECTOR_RPL_MASK;
1840
1841 if (!var.s)
1842 return false;
1843 if (!var.present)
1844 return false;
1845 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1846 if (var.dpl < rpl) /* DPL < RPL */
1847 return false;
1848 }
1849
1850 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1851 * rights flags
1852 */
1853 return true;
1854 }
1855
1856 static bool tr_valid(struct kvm_vcpu *vcpu)
1857 {
1858 struct kvm_segment tr;
1859
1860 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1861
1862 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1863 return false;
1864 if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1865 return false;
1866 if (!tr.present)
1867 return false;
1868
1869 return true;
1870 }
1871
1872 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1873 {
1874 struct kvm_segment ldtr;
1875
1876 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1877
1878 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1879 return false;
1880 if (ldtr.type != 2)
1881 return false;
1882 if (!ldtr.present)
1883 return false;
1884
1885 return true;
1886 }
1887
1888 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1889 {
1890 struct kvm_segment cs, ss;
1891
1892 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1893 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1894
1895 return ((cs.selector & SELECTOR_RPL_MASK) ==
1896 (ss.selector & SELECTOR_RPL_MASK));
1897 }
1898
1899 /*
1900 * Check if guest state is valid. Returns true if valid, false if
1901 * not.
1902 * We assume that registers are always usable
1903 */
1904 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1905 {
1906 /* real mode guest state checks */
1907 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1908 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1909 return false;
1910 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1911 return false;
1912 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1913 return false;
1914 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1915 return false;
1916 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1917 return false;
1918 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1919 return false;
1920 } else {
1921 /* protected mode guest state checks */
1922 if (!cs_ss_rpl_check(vcpu))
1923 return false;
1924 if (!code_segment_valid(vcpu))
1925 return false;
1926 if (!stack_segment_valid(vcpu))
1927 return false;
1928 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1929 return false;
1930 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1931 return false;
1932 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1933 return false;
1934 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1935 return false;
1936 if (!tr_valid(vcpu))
1937 return false;
1938 if (!ldtr_valid(vcpu))
1939 return false;
1940 }
1941 /* TODO:
1942 * - Add checks on RIP
1943 * - Add checks on RFLAGS
1944 */
1945
1946 return true;
1947 }
1948
1949 static int init_rmode_tss(struct kvm *kvm)
1950 {
1951 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1952 u16 data = 0;
1953 int ret = 0;
1954 int r;
1955
1956 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1957 if (r < 0)
1958 goto out;
1959 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1960 r = kvm_write_guest_page(kvm, fn++, &data,
1961 TSS_IOPB_BASE_OFFSET, sizeof(u16));
1962 if (r < 0)
1963 goto out;
1964 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1965 if (r < 0)
1966 goto out;
1967 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1968 if (r < 0)
1969 goto out;
1970 data = ~0;
1971 r = kvm_write_guest_page(kvm, fn, &data,
1972 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1973 sizeof(u8));
1974 if (r < 0)
1975 goto out;
1976
1977 ret = 1;
1978 out:
1979 return ret;
1980 }
1981
1982 static int init_rmode_identity_map(struct kvm *kvm)
1983 {
1984 int i, r, ret;
1985 pfn_t identity_map_pfn;
1986 u32 tmp;
1987
1988 if (!vm_need_ept())
1989 return 1;
1990 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1991 printk(KERN_ERR "EPT: identity-mapping pagetable "
1992 "haven't been allocated!\n");
1993 return 0;
1994 }
1995 if (likely(kvm->arch.ept_identity_pagetable_done))
1996 return 1;
1997 ret = 0;
1998 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1999 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2000 if (r < 0)
2001 goto out;
2002 /* Set up identity-mapping pagetable for EPT in real mode */
2003 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2004 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2005 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2006 r = kvm_write_guest_page(kvm, identity_map_pfn,
2007 &tmp, i * sizeof(tmp), sizeof(tmp));
2008 if (r < 0)
2009 goto out;
2010 }
2011 kvm->arch.ept_identity_pagetable_done = true;
2012 ret = 1;
2013 out:
2014 return ret;
2015 }
2016
2017 static void seg_setup(int seg)
2018 {
2019 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2020
2021 vmcs_write16(sf->selector, 0);
2022 vmcs_writel(sf->base, 0);
2023 vmcs_write32(sf->limit, 0xffff);
2024 vmcs_write32(sf->ar_bytes, 0xf3);
2025 }
2026
2027 static int alloc_apic_access_page(struct kvm *kvm)
2028 {
2029 struct kvm_userspace_memory_region kvm_userspace_mem;
2030 int r = 0;
2031
2032 down_write(&kvm->slots_lock);
2033 if (kvm->arch.apic_access_page)
2034 goto out;
2035 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2036 kvm_userspace_mem.flags = 0;
2037 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2038 kvm_userspace_mem.memory_size = PAGE_SIZE;
2039 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2040 if (r)
2041 goto out;
2042
2043 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2044 out:
2045 up_write(&kvm->slots_lock);
2046 return r;
2047 }
2048
2049 static int alloc_identity_pagetable(struct kvm *kvm)
2050 {
2051 struct kvm_userspace_memory_region kvm_userspace_mem;
2052 int r = 0;
2053
2054 down_write(&kvm->slots_lock);
2055 if (kvm->arch.ept_identity_pagetable)
2056 goto out;
2057 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2058 kvm_userspace_mem.flags = 0;
2059 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2060 kvm_userspace_mem.memory_size = PAGE_SIZE;
2061 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2062 if (r)
2063 goto out;
2064
2065 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2066 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2067 out:
2068 up_write(&kvm->slots_lock);
2069 return r;
2070 }
2071
2072 static void allocate_vpid(struct vcpu_vmx *vmx)
2073 {
2074 int vpid;
2075
2076 vmx->vpid = 0;
2077 if (!enable_vpid || !cpu_has_vmx_vpid())
2078 return;
2079 spin_lock(&vmx_vpid_lock);
2080 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2081 if (vpid < VMX_NR_VPIDS) {
2082 vmx->vpid = vpid;
2083 __set_bit(vpid, vmx_vpid_bitmap);
2084 }
2085 spin_unlock(&vmx_vpid_lock);
2086 }
2087
2088 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2089 {
2090 void *va;
2091
2092 if (!cpu_has_vmx_msr_bitmap())
2093 return;
2094
2095 /*
2096 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2097 * have the write-low and read-high bitmap offsets the wrong way round.
2098 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2099 */
2100 va = kmap(msr_bitmap);
2101 if (msr <= 0x1fff) {
2102 __clear_bit(msr, va + 0x000); /* read-low */
2103 __clear_bit(msr, va + 0x800); /* write-low */
2104 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2105 msr &= 0x1fff;
2106 __clear_bit(msr, va + 0x400); /* read-high */
2107 __clear_bit(msr, va + 0xc00); /* write-high */
2108 }
2109 kunmap(msr_bitmap);
2110 }
2111
2112 /*
2113 * Sets up the vmcs for emulated real mode.
2114 */
2115 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2116 {
2117 u32 host_sysenter_cs, msr_low, msr_high;
2118 u32 junk;
2119 u64 host_pat;
2120 unsigned long a;
2121 struct descriptor_table dt;
2122 int i;
2123 unsigned long kvm_vmx_return;
2124 u32 exec_control;
2125
2126 /* I/O */
2127 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2128 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2129
2130 if (cpu_has_vmx_msr_bitmap())
2131 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2132
2133 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2134
2135 /* Control */
2136 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2137 vmcs_config.pin_based_exec_ctrl);
2138
2139 exec_control = vmcs_config.cpu_based_exec_ctrl;
2140 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2141 exec_control &= ~CPU_BASED_TPR_SHADOW;
2142 #ifdef CONFIG_X86_64
2143 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2144 CPU_BASED_CR8_LOAD_EXITING;
2145 #endif
2146 }
2147 if (!vm_need_ept())
2148 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2149 CPU_BASED_CR3_LOAD_EXITING |
2150 CPU_BASED_INVLPG_EXITING;
2151 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2152
2153 if (cpu_has_secondary_exec_ctrls()) {
2154 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2155 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2156 exec_control &=
2157 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2158 if (vmx->vpid == 0)
2159 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2160 if (!vm_need_ept())
2161 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2162 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2163 }
2164
2165 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2166 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2167 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2168
2169 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2170 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2171 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2172
2173 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2174 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2175 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2176 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2177 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2178 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2179 #ifdef CONFIG_X86_64
2180 rdmsrl(MSR_FS_BASE, a);
2181 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2182 rdmsrl(MSR_GS_BASE, a);
2183 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2184 #else
2185 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2186 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2187 #endif
2188
2189 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2190
2191 kvm_get_idt(&dt);
2192 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2193
2194 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2195 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2196 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2197 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2198 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2199
2200 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2201 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2202 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2203 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2204 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2205 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2206
2207 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2208 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2209 host_pat = msr_low | ((u64) msr_high << 32);
2210 vmcs_write64(HOST_IA32_PAT, host_pat);
2211 }
2212 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2213 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2214 host_pat = msr_low | ((u64) msr_high << 32);
2215 /* Write the default value follow host pat */
2216 vmcs_write64(GUEST_IA32_PAT, host_pat);
2217 /* Keep arch.pat sync with GUEST_IA32_PAT */
2218 vmx->vcpu.arch.pat = host_pat;
2219 }
2220
2221 for (i = 0; i < NR_VMX_MSR; ++i) {
2222 u32 index = vmx_msr_index[i];
2223 u32 data_low, data_high;
2224 u64 data;
2225 int j = vmx->nmsrs;
2226
2227 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2228 continue;
2229 if (wrmsr_safe(index, data_low, data_high) < 0)
2230 continue;
2231 data = data_low | ((u64)data_high << 32);
2232 vmx->host_msrs[j].index = index;
2233 vmx->host_msrs[j].reserved = 0;
2234 vmx->host_msrs[j].data = data;
2235 vmx->guest_msrs[j] = vmx->host_msrs[j];
2236 ++vmx->nmsrs;
2237 }
2238
2239 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2240
2241 /* 22.2.1, 20.8.1 */
2242 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2243
2244 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2245 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2246
2247
2248 return 0;
2249 }
2250
2251 static int init_rmode(struct kvm *kvm)
2252 {
2253 if (!init_rmode_tss(kvm))
2254 return 0;
2255 if (!init_rmode_identity_map(kvm))
2256 return 0;
2257 return 1;
2258 }
2259
2260 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2261 {
2262 struct vcpu_vmx *vmx = to_vmx(vcpu);
2263 u64 msr;
2264 int ret;
2265
2266 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2267 down_read(&vcpu->kvm->slots_lock);
2268 if (!init_rmode(vmx->vcpu.kvm)) {
2269 ret = -ENOMEM;
2270 goto out;
2271 }
2272
2273 vmx->vcpu.arch.rmode.active = 0;
2274
2275 vmx->soft_vnmi_blocked = 0;
2276
2277 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2278 kvm_set_cr8(&vmx->vcpu, 0);
2279 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2280 if (vmx->vcpu.vcpu_id == 0)
2281 msr |= MSR_IA32_APICBASE_BSP;
2282 kvm_set_apic_base(&vmx->vcpu, msr);
2283
2284 fx_init(&vmx->vcpu);
2285
2286 seg_setup(VCPU_SREG_CS);
2287 /*
2288 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2289 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2290 */
2291 if (vmx->vcpu.vcpu_id == 0) {
2292 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2293 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2294 } else {
2295 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2296 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2297 }
2298
2299 seg_setup(VCPU_SREG_DS);
2300 seg_setup(VCPU_SREG_ES);
2301 seg_setup(VCPU_SREG_FS);
2302 seg_setup(VCPU_SREG_GS);
2303 seg_setup(VCPU_SREG_SS);
2304
2305 vmcs_write16(GUEST_TR_SELECTOR, 0);
2306 vmcs_writel(GUEST_TR_BASE, 0);
2307 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2308 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2309
2310 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2311 vmcs_writel(GUEST_LDTR_BASE, 0);
2312 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2313 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2314
2315 vmcs_write32(GUEST_SYSENTER_CS, 0);
2316 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2317 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2318
2319 vmcs_writel(GUEST_RFLAGS, 0x02);
2320 if (vmx->vcpu.vcpu_id == 0)
2321 kvm_rip_write(vcpu, 0xfff0);
2322 else
2323 kvm_rip_write(vcpu, 0);
2324 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2325
2326 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2327 vmcs_writel(GUEST_DR7, 0x400);
2328
2329 vmcs_writel(GUEST_GDTR_BASE, 0);
2330 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2331
2332 vmcs_writel(GUEST_IDTR_BASE, 0);
2333 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2334
2335 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2336 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2337 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2338
2339 guest_write_tsc(0);
2340
2341 /* Special registers */
2342 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2343
2344 setup_msrs(vmx);
2345
2346 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2347
2348 if (cpu_has_vmx_tpr_shadow()) {
2349 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2350 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2351 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2352 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2353 vmcs_write32(TPR_THRESHOLD, 0);
2354 }
2355
2356 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2357 vmcs_write64(APIC_ACCESS_ADDR,
2358 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2359
2360 if (vmx->vpid != 0)
2361 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2362
2363 vmx->vcpu.arch.cr0 = 0x60000010;
2364 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2365 vmx_set_cr4(&vmx->vcpu, 0);
2366 vmx_set_efer(&vmx->vcpu, 0);
2367 vmx_fpu_activate(&vmx->vcpu);
2368 update_exception_bitmap(&vmx->vcpu);
2369
2370 vpid_sync_vcpu_all(vmx);
2371
2372 ret = 0;
2373
2374 /* HACK: Don't enable emulation on guest boot/reset */
2375 vmx->emulation_required = 0;
2376
2377 out:
2378 up_read(&vcpu->kvm->slots_lock);
2379 return ret;
2380 }
2381
2382 static void enable_irq_window(struct kvm_vcpu *vcpu)
2383 {
2384 u32 cpu_based_vm_exec_control;
2385
2386 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2387 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2388 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2389 }
2390
2391 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2392 {
2393 u32 cpu_based_vm_exec_control;
2394
2395 if (!cpu_has_virtual_nmis()) {
2396 enable_irq_window(vcpu);
2397 return;
2398 }
2399
2400 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2401 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2402 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2403 }
2404
2405 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2406 {
2407 struct vcpu_vmx *vmx = to_vmx(vcpu);
2408
2409 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2410
2411 ++vcpu->stat.irq_injections;
2412 if (vcpu->arch.rmode.active) {
2413 vmx->rmode.irq.pending = true;
2414 vmx->rmode.irq.vector = irq;
2415 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2416 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2417 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2418 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2419 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2420 return;
2421 }
2422 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2423 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2424 }
2425
2426 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2427 {
2428 struct vcpu_vmx *vmx = to_vmx(vcpu);
2429
2430 if (!cpu_has_virtual_nmis()) {
2431 /*
2432 * Tracking the NMI-blocked state in software is built upon
2433 * finding the next open IRQ window. This, in turn, depends on
2434 * well-behaving guests: They have to keep IRQs disabled at
2435 * least as long as the NMI handler runs. Otherwise we may
2436 * cause NMI nesting, maybe breaking the guest. But as this is
2437 * highly unlikely, we can live with the residual risk.
2438 */
2439 vmx->soft_vnmi_blocked = 1;
2440 vmx->vnmi_blocked_time = 0;
2441 }
2442
2443 ++vcpu->stat.nmi_injections;
2444 if (vcpu->arch.rmode.active) {
2445 vmx->rmode.irq.pending = true;
2446 vmx->rmode.irq.vector = NMI_VECTOR;
2447 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2448 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2449 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2450 INTR_INFO_VALID_MASK);
2451 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2452 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2453 return;
2454 }
2455 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2456 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2457 }
2458
2459 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2460 {
2461 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2462
2463 vcpu->arch.nmi_window_open =
2464 !(guest_intr & (GUEST_INTR_STATE_STI |
2465 GUEST_INTR_STATE_MOV_SS |
2466 GUEST_INTR_STATE_NMI));
2467 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2468 vcpu->arch.nmi_window_open = 0;
2469
2470 vcpu->arch.interrupt_window_open =
2471 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2472 !(guest_intr & (GUEST_INTR_STATE_STI |
2473 GUEST_INTR_STATE_MOV_SS)));
2474 }
2475
2476 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2477 {
2478 int word_index = __ffs(vcpu->arch.irq_summary);
2479 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2480 int irq = word_index * BITS_PER_LONG + bit_index;
2481
2482 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2483 if (!vcpu->arch.irq_pending[word_index])
2484 clear_bit(word_index, &vcpu->arch.irq_summary);
2485 kvm_queue_interrupt(vcpu, irq);
2486 }
2487
2488 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2489 struct kvm_run *kvm_run)
2490 {
2491 vmx_update_window_states(vcpu);
2492
2493 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2494 if (vcpu->arch.interrupt.pending) {
2495 enable_nmi_window(vcpu);
2496 } else if (vcpu->arch.nmi_window_open) {
2497 vcpu->arch.nmi_pending = false;
2498 vcpu->arch.nmi_injected = true;
2499 } else {
2500 enable_nmi_window(vcpu);
2501 return;
2502 }
2503 }
2504 if (vcpu->arch.nmi_injected) {
2505 vmx_inject_nmi(vcpu);
2506 if (vcpu->arch.nmi_pending)
2507 enable_nmi_window(vcpu);
2508 else if (vcpu->arch.irq_summary
2509 || kvm_run->request_interrupt_window)
2510 enable_irq_window(vcpu);
2511 return;
2512 }
2513
2514 if (vcpu->arch.interrupt_window_open) {
2515 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2516 kvm_do_inject_irq(vcpu);
2517
2518 if (vcpu->arch.interrupt.pending)
2519 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2520 }
2521 if (!vcpu->arch.interrupt_window_open &&
2522 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2523 enable_irq_window(vcpu);
2524 }
2525
2526 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2527 {
2528 int ret;
2529 struct kvm_userspace_memory_region tss_mem = {
2530 .slot = TSS_PRIVATE_MEMSLOT,
2531 .guest_phys_addr = addr,
2532 .memory_size = PAGE_SIZE * 3,
2533 .flags = 0,
2534 };
2535
2536 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2537 if (ret)
2538 return ret;
2539 kvm->arch.tss_addr = addr;
2540 return 0;
2541 }
2542
2543 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2544 {
2545 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2546
2547 set_debugreg(dbg->bp[0], 0);
2548 set_debugreg(dbg->bp[1], 1);
2549 set_debugreg(dbg->bp[2], 2);
2550 set_debugreg(dbg->bp[3], 3);
2551
2552 if (dbg->singlestep) {
2553 unsigned long flags;
2554
2555 flags = vmcs_readl(GUEST_RFLAGS);
2556 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2557 vmcs_writel(GUEST_RFLAGS, flags);
2558 }
2559 }
2560
2561 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2562 int vec, u32 err_code)
2563 {
2564 /*
2565 * Instruction with address size override prefix opcode 0x67
2566 * Cause the #SS fault with 0 error code in VM86 mode.
2567 */
2568 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2569 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2570 return 1;
2571 /*
2572 * Forward all other exceptions that are valid in real mode.
2573 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2574 * the required debugging infrastructure rework.
2575 */
2576 switch (vec) {
2577 case DE_VECTOR:
2578 case DB_VECTOR:
2579 case BP_VECTOR:
2580 case OF_VECTOR:
2581 case BR_VECTOR:
2582 case UD_VECTOR:
2583 case DF_VECTOR:
2584 case SS_VECTOR:
2585 case GP_VECTOR:
2586 case MF_VECTOR:
2587 kvm_queue_exception(vcpu, vec);
2588 return 1;
2589 }
2590 return 0;
2591 }
2592
2593 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2594 {
2595 struct vcpu_vmx *vmx = to_vmx(vcpu);
2596 u32 intr_info, error_code;
2597 unsigned long cr2, rip;
2598 u32 vect_info;
2599 enum emulation_result er;
2600
2601 vect_info = vmx->idt_vectoring_info;
2602 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2603
2604 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2605 !is_page_fault(intr_info))
2606 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2607 "intr info 0x%x\n", __func__, vect_info, intr_info);
2608
2609 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2610 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2611 set_bit(irq, vcpu->arch.irq_pending);
2612 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2613 }
2614
2615 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2616 return 1; /* already handled by vmx_vcpu_run() */
2617
2618 if (is_no_device(intr_info)) {
2619 vmx_fpu_activate(vcpu);
2620 return 1;
2621 }
2622
2623 if (is_invalid_opcode(intr_info)) {
2624 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2625 if (er != EMULATE_DONE)
2626 kvm_queue_exception(vcpu, UD_VECTOR);
2627 return 1;
2628 }
2629
2630 error_code = 0;
2631 rip = kvm_rip_read(vcpu);
2632 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2633 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2634 if (is_page_fault(intr_info)) {
2635 /* EPT won't cause page fault directly */
2636 if (vm_need_ept())
2637 BUG();
2638 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2639 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2640 (u32)((u64)cr2 >> 32), handler);
2641 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2642 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2643 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2644 }
2645
2646 if (vcpu->arch.rmode.active &&
2647 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2648 error_code)) {
2649 if (vcpu->arch.halt_request) {
2650 vcpu->arch.halt_request = 0;
2651 return kvm_emulate_halt(vcpu);
2652 }
2653 return 1;
2654 }
2655
2656 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2657 (INTR_TYPE_HARD_EXCEPTION | 1)) {
2658 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2659 return 0;
2660 }
2661 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2662 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2663 kvm_run->ex.error_code = error_code;
2664 return 0;
2665 }
2666
2667 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2668 struct kvm_run *kvm_run)
2669 {
2670 ++vcpu->stat.irq_exits;
2671 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2672 return 1;
2673 }
2674
2675 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2676 {
2677 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2678 return 0;
2679 }
2680
2681 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2682 {
2683 unsigned long exit_qualification;
2684 int size, down, in, string, rep;
2685 unsigned port;
2686
2687 ++vcpu->stat.io_exits;
2688 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2689 string = (exit_qualification & 16) != 0;
2690
2691 if (string) {
2692 if (emulate_instruction(vcpu,
2693 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2694 return 0;
2695 return 1;
2696 }
2697
2698 size = (exit_qualification & 7) + 1;
2699 in = (exit_qualification & 8) != 0;
2700 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2701 rep = (exit_qualification & 32) != 0;
2702 port = exit_qualification >> 16;
2703
2704 skip_emulated_instruction(vcpu);
2705 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2706 }
2707
2708 static void
2709 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2710 {
2711 /*
2712 * Patch in the VMCALL instruction:
2713 */
2714 hypercall[0] = 0x0f;
2715 hypercall[1] = 0x01;
2716 hypercall[2] = 0xc1;
2717 }
2718
2719 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2720 {
2721 unsigned long exit_qualification;
2722 int cr;
2723 int reg;
2724
2725 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2726 cr = exit_qualification & 15;
2727 reg = (exit_qualification >> 8) & 15;
2728 switch ((exit_qualification >> 4) & 3) {
2729 case 0: /* mov to cr */
2730 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2731 (u32)kvm_register_read(vcpu, reg),
2732 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2733 handler);
2734 switch (cr) {
2735 case 0:
2736 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2737 skip_emulated_instruction(vcpu);
2738 return 1;
2739 case 3:
2740 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2741 skip_emulated_instruction(vcpu);
2742 return 1;
2743 case 4:
2744 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2745 skip_emulated_instruction(vcpu);
2746 return 1;
2747 case 8:
2748 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2749 skip_emulated_instruction(vcpu);
2750 if (irqchip_in_kernel(vcpu->kvm))
2751 return 1;
2752 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2753 return 0;
2754 };
2755 break;
2756 case 2: /* clts */
2757 vmx_fpu_deactivate(vcpu);
2758 vcpu->arch.cr0 &= ~X86_CR0_TS;
2759 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2760 vmx_fpu_activate(vcpu);
2761 KVMTRACE_0D(CLTS, vcpu, handler);
2762 skip_emulated_instruction(vcpu);
2763 return 1;
2764 case 1: /*mov from cr*/
2765 switch (cr) {
2766 case 3:
2767 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2768 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2769 (u32)kvm_register_read(vcpu, reg),
2770 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2771 handler);
2772 skip_emulated_instruction(vcpu);
2773 return 1;
2774 case 8:
2775 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2776 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2777 (u32)kvm_register_read(vcpu, reg), handler);
2778 skip_emulated_instruction(vcpu);
2779 return 1;
2780 }
2781 break;
2782 case 3: /* lmsw */
2783 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2784
2785 skip_emulated_instruction(vcpu);
2786 return 1;
2787 default:
2788 break;
2789 }
2790 kvm_run->exit_reason = 0;
2791 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2792 (int)(exit_qualification >> 4) & 3, cr);
2793 return 0;
2794 }
2795
2796 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2797 {
2798 unsigned long exit_qualification;
2799 unsigned long val;
2800 int dr, reg;
2801
2802 /*
2803 * FIXME: this code assumes the host is debugging the guest.
2804 * need to deal with guest debugging itself too.
2805 */
2806 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2807 dr = exit_qualification & 7;
2808 reg = (exit_qualification >> 8) & 15;
2809 if (exit_qualification & 16) {
2810 /* mov from dr */
2811 switch (dr) {
2812 case 6:
2813 val = 0xffff0ff0;
2814 break;
2815 case 7:
2816 val = 0x400;
2817 break;
2818 default:
2819 val = 0;
2820 }
2821 kvm_register_write(vcpu, reg, val);
2822 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2823 } else {
2824 /* mov to dr */
2825 }
2826 skip_emulated_instruction(vcpu);
2827 return 1;
2828 }
2829
2830 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2831 {
2832 kvm_emulate_cpuid(vcpu);
2833 return 1;
2834 }
2835
2836 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2837 {
2838 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2839 u64 data;
2840
2841 if (vmx_get_msr(vcpu, ecx, &data)) {
2842 kvm_inject_gp(vcpu, 0);
2843 return 1;
2844 }
2845
2846 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2847 handler);
2848
2849 /* FIXME: handling of bits 32:63 of rax, rdx */
2850 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2851 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2852 skip_emulated_instruction(vcpu);
2853 return 1;
2854 }
2855
2856 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2857 {
2858 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2859 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2860 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2861
2862 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2863 handler);
2864
2865 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2866 kvm_inject_gp(vcpu, 0);
2867 return 1;
2868 }
2869
2870 skip_emulated_instruction(vcpu);
2871 return 1;
2872 }
2873
2874 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2875 struct kvm_run *kvm_run)
2876 {
2877 return 1;
2878 }
2879
2880 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2881 struct kvm_run *kvm_run)
2882 {
2883 u32 cpu_based_vm_exec_control;
2884
2885 /* clear pending irq */
2886 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2887 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2888 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2889
2890 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2891 ++vcpu->stat.irq_window_exits;
2892
2893 /*
2894 * If the user space waits to inject interrupts, exit as soon as
2895 * possible
2896 */
2897 if (kvm_run->request_interrupt_window &&
2898 !vcpu->arch.irq_summary) {
2899 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2900 return 0;
2901 }
2902 return 1;
2903 }
2904
2905 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2906 {
2907 skip_emulated_instruction(vcpu);
2908 return kvm_emulate_halt(vcpu);
2909 }
2910
2911 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2912 {
2913 skip_emulated_instruction(vcpu);
2914 kvm_emulate_hypercall(vcpu);
2915 return 1;
2916 }
2917
2918 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2919 {
2920 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2921
2922 kvm_mmu_invlpg(vcpu, exit_qualification);
2923 skip_emulated_instruction(vcpu);
2924 return 1;
2925 }
2926
2927 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2928 {
2929 skip_emulated_instruction(vcpu);
2930 /* TODO: Add support for VT-d/pass-through device */
2931 return 1;
2932 }
2933
2934 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2935 {
2936 u64 exit_qualification;
2937 enum emulation_result er;
2938 unsigned long offset;
2939
2940 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2941 offset = exit_qualification & 0xffful;
2942
2943 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2944
2945 if (er != EMULATE_DONE) {
2946 printk(KERN_ERR
2947 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2948 offset);
2949 return -ENOTSUPP;
2950 }
2951 return 1;
2952 }
2953
2954 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2955 {
2956 struct vcpu_vmx *vmx = to_vmx(vcpu);
2957 unsigned long exit_qualification;
2958 u16 tss_selector;
2959 int reason;
2960
2961 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2962
2963 reason = (u32)exit_qualification >> 30;
2964 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
2965 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
2966 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
2967 == INTR_TYPE_NMI_INTR) {
2968 vcpu->arch.nmi_injected = false;
2969 if (cpu_has_virtual_nmis())
2970 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2971 GUEST_INTR_STATE_NMI);
2972 }
2973 tss_selector = exit_qualification;
2974
2975 return kvm_task_switch(vcpu, tss_selector, reason);
2976 }
2977
2978 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2979 {
2980 u64 exit_qualification;
2981 enum emulation_result er;
2982 gpa_t gpa;
2983 unsigned long hva;
2984 int gla_validity;
2985 int r;
2986
2987 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2988
2989 if (exit_qualification & (1 << 6)) {
2990 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2991 return -ENOTSUPP;
2992 }
2993
2994 gla_validity = (exit_qualification >> 7) & 0x3;
2995 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2996 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2997 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2998 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2999 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3000 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3001 (long unsigned int)exit_qualification);
3002 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3003 kvm_run->hw.hardware_exit_reason = 0;
3004 return -ENOTSUPP;
3005 }
3006
3007 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3008 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
3009 if (!kvm_is_error_hva(hva)) {
3010 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3011 if (r < 0) {
3012 printk(KERN_ERR "EPT: Not enough memory!\n");
3013 return -ENOMEM;
3014 }
3015 return 1;
3016 } else {
3017 /* must be MMIO */
3018 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3019
3020 if (er == EMULATE_FAIL) {
3021 printk(KERN_ERR
3022 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
3023 er);
3024 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3025 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3026 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3027 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3028 (long unsigned int)exit_qualification);
3029 return -ENOTSUPP;
3030 } else if (er == EMULATE_DO_MMIO)
3031 return 0;
3032 }
3033 return 1;
3034 }
3035
3036 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3037 {
3038 u32 cpu_based_vm_exec_control;
3039
3040 /* clear pending NMI */
3041 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3042 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3043 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3044 ++vcpu->stat.nmi_window_exits;
3045
3046 return 1;
3047 }
3048
3049 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3050 struct kvm_run *kvm_run)
3051 {
3052 struct vcpu_vmx *vmx = to_vmx(vcpu);
3053 int err;
3054
3055 preempt_enable();
3056 local_irq_enable();
3057
3058 while (!guest_state_valid(vcpu)) {
3059 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3060
3061 if (err == EMULATE_DO_MMIO)
3062 break;
3063
3064 if (err != EMULATE_DONE) {
3065 kvm_report_emulation_failure(vcpu, "emulation failure");
3066 return;
3067 }
3068
3069 if (signal_pending(current))
3070 break;
3071 if (need_resched())
3072 schedule();
3073 }
3074
3075 local_irq_disable();
3076 preempt_disable();
3077
3078 /* Guest state should be valid now except if we need to
3079 * emulate an MMIO */
3080 if (guest_state_valid(vcpu))
3081 vmx->emulation_required = 0;
3082 }
3083
3084 /*
3085 * The exit handlers return 1 if the exit was handled fully and guest execution
3086 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3087 * to be done to userspace and return 0.
3088 */
3089 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3090 struct kvm_run *kvm_run) = {
3091 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3092 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3093 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3094 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3095 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3096 [EXIT_REASON_CR_ACCESS] = handle_cr,
3097 [EXIT_REASON_DR_ACCESS] = handle_dr,
3098 [EXIT_REASON_CPUID] = handle_cpuid,
3099 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3100 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3101 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3102 [EXIT_REASON_HLT] = handle_halt,
3103 [EXIT_REASON_INVLPG] = handle_invlpg,
3104 [EXIT_REASON_VMCALL] = handle_vmcall,
3105 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3106 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3107 [EXIT_REASON_WBINVD] = handle_wbinvd,
3108 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3109 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3110 };
3111
3112 static const int kvm_vmx_max_exit_handlers =
3113 ARRAY_SIZE(kvm_vmx_exit_handlers);
3114
3115 /*
3116 * The guest has exited. See if we can fix it or if we need userspace
3117 * assistance.
3118 */
3119 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3120 {
3121 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3122 struct vcpu_vmx *vmx = to_vmx(vcpu);
3123 u32 vectoring_info = vmx->idt_vectoring_info;
3124
3125 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3126 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3127
3128 /* If we need to emulate an MMIO from handle_invalid_guest_state
3129 * we just return 0 */
3130 if (vmx->emulation_required && emulate_invalid_guest_state)
3131 return 0;
3132
3133 /* Access CR3 don't cause VMExit in paging mode, so we need
3134 * to sync with guest real CR3. */
3135 if (vm_need_ept() && is_paging(vcpu)) {
3136 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3137 ept_load_pdptrs(vcpu);
3138 }
3139
3140 if (unlikely(vmx->fail)) {
3141 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3142 kvm_run->fail_entry.hardware_entry_failure_reason
3143 = vmcs_read32(VM_INSTRUCTION_ERROR);
3144 return 0;
3145 }
3146
3147 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3148 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3149 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3150 exit_reason != EXIT_REASON_TASK_SWITCH))
3151 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3152 "(0x%x) and exit reason is 0x%x\n",
3153 __func__, vectoring_info, exit_reason);
3154
3155 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3156 if (vcpu->arch.interrupt_window_open) {
3157 vmx->soft_vnmi_blocked = 0;
3158 vcpu->arch.nmi_window_open = 1;
3159 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3160 vcpu->arch.nmi_pending) {
3161 /*
3162 * This CPU don't support us in finding the end of an
3163 * NMI-blocked window if the guest runs with IRQs
3164 * disabled. So we pull the trigger after 1 s of
3165 * futile waiting, but inform the user about this.
3166 */
3167 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3168 "state on VCPU %d after 1 s timeout\n",
3169 __func__, vcpu->vcpu_id);
3170 vmx->soft_vnmi_blocked = 0;
3171 vmx->vcpu.arch.nmi_window_open = 1;
3172 }
3173 }
3174
3175 if (exit_reason < kvm_vmx_max_exit_handlers
3176 && kvm_vmx_exit_handlers[exit_reason])
3177 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3178 else {
3179 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3180 kvm_run->hw.hardware_exit_reason = exit_reason;
3181 }
3182 return 0;
3183 }
3184
3185 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3186 {
3187 int max_irr, tpr;
3188
3189 if (!vm_need_tpr_shadow(vcpu->kvm))
3190 return;
3191
3192 if (!kvm_lapic_enabled(vcpu) ||
3193 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3194 vmcs_write32(TPR_THRESHOLD, 0);
3195 return;
3196 }
3197
3198 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3199 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3200 }
3201
3202 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3203 {
3204 u32 exit_intr_info;
3205 u32 idt_vectoring_info;
3206 bool unblock_nmi;
3207 u8 vector;
3208 int type;
3209 bool idtv_info_valid;
3210 u32 error;
3211
3212 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3213 if (cpu_has_virtual_nmis()) {
3214 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3215 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3216 /*
3217 * SDM 3: 25.7.1.2
3218 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3219 * a guest IRET fault.
3220 */
3221 if (unblock_nmi && vector != DF_VECTOR)
3222 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3223 GUEST_INTR_STATE_NMI);
3224 } else if (unlikely(vmx->soft_vnmi_blocked))
3225 vmx->vnmi_blocked_time +=
3226 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3227
3228 idt_vectoring_info = vmx->idt_vectoring_info;
3229 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3230 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3231 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3232 if (vmx->vcpu.arch.nmi_injected) {
3233 /*
3234 * SDM 3: 25.7.1.2
3235 * Clear bit "block by NMI" before VM entry if a NMI delivery
3236 * faulted.
3237 */
3238 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3239 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3240 GUEST_INTR_STATE_NMI);
3241 else
3242 vmx->vcpu.arch.nmi_injected = false;
3243 }
3244 kvm_clear_exception_queue(&vmx->vcpu);
3245 if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3246 type == INTR_TYPE_SOFT_EXCEPTION)) {
3247 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3248 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3249 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3250 } else
3251 kvm_queue_exception(&vmx->vcpu, vector);
3252 vmx->idt_vectoring_info = 0;
3253 }
3254 kvm_clear_interrupt_queue(&vmx->vcpu);
3255 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3256 kvm_queue_interrupt(&vmx->vcpu, vector);
3257 vmx->idt_vectoring_info = 0;
3258 }
3259 }
3260
3261 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3262 {
3263 update_tpr_threshold(vcpu);
3264
3265 vmx_update_window_states(vcpu);
3266
3267 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3268 if (vcpu->arch.interrupt.pending) {
3269 enable_nmi_window(vcpu);
3270 } else if (vcpu->arch.nmi_window_open) {
3271 vcpu->arch.nmi_pending = false;
3272 vcpu->arch.nmi_injected = true;
3273 } else {
3274 enable_nmi_window(vcpu);
3275 return;
3276 }
3277 }
3278 if (vcpu->arch.nmi_injected) {
3279 vmx_inject_nmi(vcpu);
3280 if (vcpu->arch.nmi_pending)
3281 enable_nmi_window(vcpu);
3282 else if (kvm_cpu_has_interrupt(vcpu))
3283 enable_irq_window(vcpu);
3284 return;
3285 }
3286 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3287 if (vcpu->arch.interrupt_window_open)
3288 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3289 else
3290 enable_irq_window(vcpu);
3291 }
3292 if (vcpu->arch.interrupt.pending) {
3293 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3294 if (kvm_cpu_has_interrupt(vcpu))
3295 enable_irq_window(vcpu);
3296 }
3297 }
3298
3299 /*
3300 * Failure to inject an interrupt should give us the information
3301 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3302 * when fetching the interrupt redirection bitmap in the real-mode
3303 * tss, this doesn't happen. So we do it ourselves.
3304 */
3305 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3306 {
3307 vmx->rmode.irq.pending = 0;
3308 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3309 return;
3310 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3311 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3312 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3313 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3314 return;
3315 }
3316 vmx->idt_vectoring_info =
3317 VECTORING_INFO_VALID_MASK
3318 | INTR_TYPE_EXT_INTR
3319 | vmx->rmode.irq.vector;
3320 }
3321
3322 #ifdef CONFIG_X86_64
3323 #define R "r"
3324 #define Q "q"
3325 #else
3326 #define R "e"
3327 #define Q "l"
3328 #endif
3329
3330 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3331 {
3332 struct vcpu_vmx *vmx = to_vmx(vcpu);
3333 u32 intr_info;
3334
3335 /* Record the guest's net vcpu time for enforced NMI injections. */
3336 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3337 vmx->entry_time = ktime_get();
3338
3339 /* Handle invalid guest state instead of entering VMX */
3340 if (vmx->emulation_required && emulate_invalid_guest_state) {
3341 handle_invalid_guest_state(vcpu, kvm_run);
3342 return;
3343 }
3344
3345 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3346 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3347 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3348 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3349
3350 /*
3351 * Loading guest fpu may have cleared host cr0.ts
3352 */
3353 vmcs_writel(HOST_CR0, read_cr0());
3354
3355 asm(
3356 /* Store host registers */
3357 "push %%"R"dx; push %%"R"bp;"
3358 "push %%"R"cx \n\t"
3359 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3360 "je 1f \n\t"
3361 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3362 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3363 "1: \n\t"
3364 /* Check if vmlaunch of vmresume is needed */
3365 "cmpl $0, %c[launched](%0) \n\t"
3366 /* Load guest registers. Don't clobber flags. */
3367 "mov %c[cr2](%0), %%"R"ax \n\t"
3368 "mov %%"R"ax, %%cr2 \n\t"
3369 "mov %c[rax](%0), %%"R"ax \n\t"
3370 "mov %c[rbx](%0), %%"R"bx \n\t"
3371 "mov %c[rdx](%0), %%"R"dx \n\t"
3372 "mov %c[rsi](%0), %%"R"si \n\t"
3373 "mov %c[rdi](%0), %%"R"di \n\t"
3374 "mov %c[rbp](%0), %%"R"bp \n\t"
3375 #ifdef CONFIG_X86_64
3376 "mov %c[r8](%0), %%r8 \n\t"
3377 "mov %c[r9](%0), %%r9 \n\t"
3378 "mov %c[r10](%0), %%r10 \n\t"
3379 "mov %c[r11](%0), %%r11 \n\t"
3380 "mov %c[r12](%0), %%r12 \n\t"
3381 "mov %c[r13](%0), %%r13 \n\t"
3382 "mov %c[r14](%0), %%r14 \n\t"
3383 "mov %c[r15](%0), %%r15 \n\t"
3384 #endif
3385 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3386
3387 /* Enter guest mode */
3388 "jne .Llaunched \n\t"
3389 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3390 "jmp .Lkvm_vmx_return \n\t"
3391 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3392 ".Lkvm_vmx_return: "
3393 /* Save guest registers, load host registers, keep flags */
3394 "xchg %0, (%%"R"sp) \n\t"
3395 "mov %%"R"ax, %c[rax](%0) \n\t"
3396 "mov %%"R"bx, %c[rbx](%0) \n\t"
3397 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3398 "mov %%"R"dx, %c[rdx](%0) \n\t"
3399 "mov %%"R"si, %c[rsi](%0) \n\t"
3400 "mov %%"R"di, %c[rdi](%0) \n\t"
3401 "mov %%"R"bp, %c[rbp](%0) \n\t"
3402 #ifdef CONFIG_X86_64
3403 "mov %%r8, %c[r8](%0) \n\t"
3404 "mov %%r9, %c[r9](%0) \n\t"
3405 "mov %%r10, %c[r10](%0) \n\t"
3406 "mov %%r11, %c[r11](%0) \n\t"
3407 "mov %%r12, %c[r12](%0) \n\t"
3408 "mov %%r13, %c[r13](%0) \n\t"
3409 "mov %%r14, %c[r14](%0) \n\t"
3410 "mov %%r15, %c[r15](%0) \n\t"
3411 #endif
3412 "mov %%cr2, %%"R"ax \n\t"
3413 "mov %%"R"ax, %c[cr2](%0) \n\t"
3414
3415 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3416 "setbe %c[fail](%0) \n\t"
3417 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3418 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3419 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3420 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3421 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3422 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3423 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3424 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3425 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3426 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3427 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3428 #ifdef CONFIG_X86_64
3429 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3430 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3431 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3432 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3433 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3434 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3435 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3436 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3437 #endif
3438 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3439 : "cc", "memory"
3440 , R"bx", R"di", R"si"
3441 #ifdef CONFIG_X86_64
3442 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3443 #endif
3444 );
3445
3446 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3447 vcpu->arch.regs_dirty = 0;
3448
3449 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3450 if (vmx->rmode.irq.pending)
3451 fixup_rmode_irq(vmx);
3452
3453 vmx_update_window_states(vcpu);
3454
3455 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3456 vmx->launched = 1;
3457
3458 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3459
3460 /* We need to handle NMIs before interrupts are enabled */
3461 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3462 (intr_info & INTR_INFO_VALID_MASK)) {
3463 KVMTRACE_0D(NMI, vcpu, handler);
3464 asm("int $2");
3465 }
3466
3467 vmx_complete_interrupts(vmx);
3468 }
3469
3470 #undef R
3471 #undef Q
3472
3473 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3474 {
3475 struct vcpu_vmx *vmx = to_vmx(vcpu);
3476
3477 if (vmx->vmcs) {
3478 vcpu_clear(vmx);
3479 free_vmcs(vmx->vmcs);
3480 vmx->vmcs = NULL;
3481 }
3482 }
3483
3484 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3485 {
3486 struct vcpu_vmx *vmx = to_vmx(vcpu);
3487
3488 spin_lock(&vmx_vpid_lock);
3489 if (vmx->vpid != 0)
3490 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3491 spin_unlock(&vmx_vpid_lock);
3492 vmx_free_vmcs(vcpu);
3493 kfree(vmx->host_msrs);
3494 kfree(vmx->guest_msrs);
3495 kvm_vcpu_uninit(vcpu);
3496 kmem_cache_free(kvm_vcpu_cache, vmx);
3497 }
3498
3499 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3500 {
3501 int err;
3502 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3503 int cpu;
3504
3505 if (!vmx)
3506 return ERR_PTR(-ENOMEM);
3507
3508 allocate_vpid(vmx);
3509
3510 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3511 if (err)
3512 goto free_vcpu;
3513
3514 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3515 if (!vmx->guest_msrs) {
3516 err = -ENOMEM;
3517 goto uninit_vcpu;
3518 }
3519
3520 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3521 if (!vmx->host_msrs)
3522 goto free_guest_msrs;
3523
3524 vmx->vmcs = alloc_vmcs();
3525 if (!vmx->vmcs)
3526 goto free_msrs;
3527
3528 vmcs_clear(vmx->vmcs);
3529
3530 cpu = get_cpu();
3531 vmx_vcpu_load(&vmx->vcpu, cpu);
3532 err = vmx_vcpu_setup(vmx);
3533 vmx_vcpu_put(&vmx->vcpu);
3534 put_cpu();
3535 if (err)
3536 goto free_vmcs;
3537 if (vm_need_virtualize_apic_accesses(kvm))
3538 if (alloc_apic_access_page(kvm) != 0)
3539 goto free_vmcs;
3540
3541 if (vm_need_ept())
3542 if (alloc_identity_pagetable(kvm) != 0)
3543 goto free_vmcs;
3544
3545 return &vmx->vcpu;
3546
3547 free_vmcs:
3548 free_vmcs(vmx->vmcs);
3549 free_msrs:
3550 kfree(vmx->host_msrs);
3551 free_guest_msrs:
3552 kfree(vmx->guest_msrs);
3553 uninit_vcpu:
3554 kvm_vcpu_uninit(&vmx->vcpu);
3555 free_vcpu:
3556 kmem_cache_free(kvm_vcpu_cache, vmx);
3557 return ERR_PTR(err);
3558 }
3559
3560 static void __init vmx_check_processor_compat(void *rtn)
3561 {
3562 struct vmcs_config vmcs_conf;
3563
3564 *(int *)rtn = 0;
3565 if (setup_vmcs_config(&vmcs_conf) < 0)
3566 *(int *)rtn = -EIO;
3567 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3568 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3569 smp_processor_id());
3570 *(int *)rtn = -EIO;
3571 }
3572 }
3573
3574 static int get_ept_level(void)
3575 {
3576 return VMX_EPT_DEFAULT_GAW + 1;
3577 }
3578
3579 static int vmx_get_mt_mask_shift(void)
3580 {
3581 return VMX_EPT_MT_EPTE_SHIFT;
3582 }
3583
3584 static struct kvm_x86_ops vmx_x86_ops = {
3585 .cpu_has_kvm_support = cpu_has_kvm_support,
3586 .disabled_by_bios = vmx_disabled_by_bios,
3587 .hardware_setup = hardware_setup,
3588 .hardware_unsetup = hardware_unsetup,
3589 .check_processor_compatibility = vmx_check_processor_compat,
3590 .hardware_enable = hardware_enable,
3591 .hardware_disable = hardware_disable,
3592 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3593
3594 .vcpu_create = vmx_create_vcpu,
3595 .vcpu_free = vmx_free_vcpu,
3596 .vcpu_reset = vmx_vcpu_reset,
3597
3598 .prepare_guest_switch = vmx_save_host_state,
3599 .vcpu_load = vmx_vcpu_load,
3600 .vcpu_put = vmx_vcpu_put,
3601
3602 .set_guest_debug = set_guest_debug,
3603 .guest_debug_pre = kvm_guest_debug_pre,
3604 .get_msr = vmx_get_msr,
3605 .set_msr = vmx_set_msr,
3606 .get_segment_base = vmx_get_segment_base,
3607 .get_segment = vmx_get_segment,
3608 .set_segment = vmx_set_segment,
3609 .get_cpl = vmx_get_cpl,
3610 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3611 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3612 .set_cr0 = vmx_set_cr0,
3613 .set_cr3 = vmx_set_cr3,
3614 .set_cr4 = vmx_set_cr4,
3615 .set_efer = vmx_set_efer,
3616 .get_idt = vmx_get_idt,
3617 .set_idt = vmx_set_idt,
3618 .get_gdt = vmx_get_gdt,
3619 .set_gdt = vmx_set_gdt,
3620 .cache_reg = vmx_cache_reg,
3621 .get_rflags = vmx_get_rflags,
3622 .set_rflags = vmx_set_rflags,
3623
3624 .tlb_flush = vmx_flush_tlb,
3625
3626 .run = vmx_vcpu_run,
3627 .handle_exit = kvm_handle_exit,
3628 .skip_emulated_instruction = skip_emulated_instruction,
3629 .patch_hypercall = vmx_patch_hypercall,
3630 .get_irq = vmx_get_irq,
3631 .set_irq = vmx_inject_irq,
3632 .queue_exception = vmx_queue_exception,
3633 .exception_injected = vmx_exception_injected,
3634 .inject_pending_irq = vmx_intr_assist,
3635 .inject_pending_vectors = do_interrupt_requests,
3636
3637 .set_tss_addr = vmx_set_tss_addr,
3638 .get_tdp_level = get_ept_level,
3639 .get_mt_mask_shift = vmx_get_mt_mask_shift,
3640 };
3641
3642 static int __init vmx_init(void)
3643 {
3644 void *va;
3645 int r;
3646
3647 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3648 if (!vmx_io_bitmap_a)
3649 return -ENOMEM;
3650
3651 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3652 if (!vmx_io_bitmap_b) {
3653 r = -ENOMEM;
3654 goto out;
3655 }
3656
3657 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3658 if (!vmx_msr_bitmap) {
3659 r = -ENOMEM;
3660 goto out1;
3661 }
3662
3663 /*
3664 * Allow direct access to the PC debug port (it is often used for I/O
3665 * delays, but the vmexits simply slow things down).
3666 */
3667 va = kmap(vmx_io_bitmap_a);
3668 memset(va, 0xff, PAGE_SIZE);
3669 clear_bit(0x80, va);
3670 kunmap(vmx_io_bitmap_a);
3671
3672 va = kmap(vmx_io_bitmap_b);
3673 memset(va, 0xff, PAGE_SIZE);
3674 kunmap(vmx_io_bitmap_b);
3675
3676 va = kmap(vmx_msr_bitmap);
3677 memset(va, 0xff, PAGE_SIZE);
3678 kunmap(vmx_msr_bitmap);
3679
3680 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3681
3682 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3683 if (r)
3684 goto out2;
3685
3686 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3687 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3688 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3689 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3690 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3691
3692 if (vm_need_ept()) {
3693 bypass_guest_pf = 0;
3694 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3695 VMX_EPT_WRITABLE_MASK);
3696 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3697 VMX_EPT_EXECUTABLE_MASK,
3698 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3699 kvm_enable_tdp();
3700 } else
3701 kvm_disable_tdp();
3702
3703 if (bypass_guest_pf)
3704 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3705
3706 ept_sync_global();
3707
3708 return 0;
3709
3710 out2:
3711 __free_page(vmx_msr_bitmap);
3712 out1:
3713 __free_page(vmx_io_bitmap_b);
3714 out:
3715 __free_page(vmx_io_bitmap_a);
3716 return r;
3717 }
3718
3719 static void __exit vmx_exit(void)
3720 {
3721 __free_page(vmx_msr_bitmap);
3722 __free_page(vmx_io_bitmap_b);
3723 __free_page(vmx_io_bitmap_a);
3724
3725 kvm_exit();
3726 }
3727
3728 module_init(vmx_init)
3729 module_exit(vmx_exit)
Support for the Chinese Samsung S3C2440 based development boards