2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr
;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic
;
63 /* Local APIC timer verification ok */
64 static int local_apic_timer_verify_ok
;
65 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
66 static int local_apic_timer_disabled
;
67 /* Local APIC timer works in C2 */
68 int local_apic_timer_c2_ok
;
69 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
71 int first_system_vector
= 0xfe;
73 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
76 * Debug level, exported for io_apic.c
78 unsigned int apic_verbosity
;
82 /* Have we found an MP table */
85 static struct resource lapic_resource
= {
87 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
90 static unsigned int calibration_result
;
92 static int lapic_next_event(unsigned long delta
,
93 struct clock_event_device
*evt
);
94 static void lapic_timer_setup(enum clock_event_mode mode
,
95 struct clock_event_device
*evt
);
96 static void lapic_timer_broadcast(cpumask_t mask
);
97 static void apic_pm_activate(void);
100 * The local apic timer can be used for any function which is CPU local.
102 static struct clock_event_device lapic_clockevent
= {
104 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
105 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
107 .set_mode
= lapic_timer_setup
,
108 .set_next_event
= lapic_next_event
,
109 .broadcast
= lapic_timer_broadcast
,
113 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
115 /* Local APIC was disabled by the BIOS and enabled by the kernel */
116 static int enabled_via_apicbase
;
118 static unsigned long apic_phys
;
121 * Get the LAPIC version
123 static inline int lapic_get_version(void)
125 return GET_APIC_VERSION(apic_read(APIC_LVR
));
129 * Check, if the APIC is integrated or a separate chip
131 static inline int lapic_is_integrated(void)
133 return APIC_INTEGRATED(lapic_get_version());
137 * Check, whether this is a modern or a first generation APIC
139 static int modern_apic(void)
141 /* AMD systems use old APIC versions, so check the CPU */
142 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
143 boot_cpu_data
.x86
>= 0xf)
145 return lapic_get_version() >= 0x14;
149 * Paravirt kernels also might be using these below ops. So we still
150 * use generic apic_read()/apic_write(), which might be pointing to different
151 * ops in PARAVIRT case.
153 void xapic_wait_icr_idle(void)
155 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
159 u32
safe_xapic_wait_icr_idle(void)
166 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
170 } while (timeout
++ < 1000);
175 void xapic_icr_write(u32 low
, u32 id
)
177 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
178 apic_write(APIC_ICR
, low
);
181 u64
xapic_icr_read(void)
185 icr2
= apic_read(APIC_ICR2
);
186 icr1
= apic_read(APIC_ICR
);
188 return icr1
| ((u64
)icr2
<< 32);
191 static struct apic_ops xapic_ops
= {
192 .read
= native_apic_mem_read
,
193 .write
= native_apic_mem_write
,
194 .icr_read
= xapic_icr_read
,
195 .icr_write
= xapic_icr_write
,
196 .wait_icr_idle
= xapic_wait_icr_idle
,
197 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
200 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
201 EXPORT_SYMBOL_GPL(apic_ops
);
204 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
206 void __cpuinit
enable_NMI_through_LVT0(void)
208 unsigned int v
= APIC_DM_NMI
;
210 /* Level triggered for 82489DX */
211 if (!lapic_is_integrated())
212 v
|= APIC_LVT_LEVEL_TRIGGER
;
213 apic_write(APIC_LVT0
, v
);
217 * get_physical_broadcast - Get number of physical broadcast IDs
219 int get_physical_broadcast(void)
221 return modern_apic() ? 0xff : 0xf;
225 * lapic_get_maxlvt - get the maximum number of local vector table entries
227 int lapic_get_maxlvt(void)
229 unsigned int v
= apic_read(APIC_LVR
);
231 /* 82489DXs do not report # of LVT entries. */
232 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
239 /* Clock divisor is set to 16 */
240 #define APIC_DIVISOR 16
243 * This function sets up the local APIC timer, with a timeout of
244 * 'clocks' APIC bus clock. During calibration we actually call
245 * this function twice on the boot CPU, once with a bogus timeout
246 * value, second time for real. The other (noncalibrating) CPUs
247 * call this function only once, with the real, calibrated value.
249 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
251 unsigned int lvtt_value
, tmp_value
;
253 lvtt_value
= LOCAL_TIMER_VECTOR
;
255 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
256 if (!lapic_is_integrated())
257 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
260 lvtt_value
|= APIC_LVT_MASKED
;
262 apic_write(APIC_LVTT
, lvtt_value
);
267 tmp_value
= apic_read(APIC_TDCR
);
268 apic_write(APIC_TDCR
,
269 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
273 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
277 * Program the next event, relative to now
279 static int lapic_next_event(unsigned long delta
,
280 struct clock_event_device
*evt
)
282 apic_write(APIC_TMICT
, delta
);
287 * Setup the lapic timer in periodic or oneshot mode
289 static void lapic_timer_setup(enum clock_event_mode mode
,
290 struct clock_event_device
*evt
)
295 /* Lapic used for broadcast ? */
296 if (!local_apic_timer_verify_ok
)
299 local_irq_save(flags
);
302 case CLOCK_EVT_MODE_PERIODIC
:
303 case CLOCK_EVT_MODE_ONESHOT
:
304 __setup_APIC_LVTT(calibration_result
,
305 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
307 case CLOCK_EVT_MODE_UNUSED
:
308 case CLOCK_EVT_MODE_SHUTDOWN
:
309 v
= apic_read(APIC_LVTT
);
310 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
311 apic_write(APIC_LVTT
, v
);
313 case CLOCK_EVT_MODE_RESUME
:
314 /* Nothing to do here */
318 local_irq_restore(flags
);
322 * Local APIC timer broadcast function
324 static void lapic_timer_broadcast(cpumask_t mask
)
327 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
332 * Setup the local APIC timer for this CPU. Copy the initilized values
333 * of the boot CPU and register the clock event in the framework.
335 static void __devinit
setup_APIC_timer(void)
337 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
339 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
340 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
342 clockevents_register_device(levt
);
346 * In this functions we calibrate APIC bus clocks to the external timer.
348 * We want to do the calibration only once since we want to have local timer
349 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
352 * This was previously done by reading the PIT/HPET and waiting for a wrap
353 * around to find out, that a tick has elapsed. I have a box, where the PIT
354 * readout is broken, so it never gets out of the wait loop again. This was
355 * also reported by others.
357 * Monitoring the jiffies value is inaccurate and the clockevents
358 * infrastructure allows us to do a simple substitution of the interrupt
361 * The calibration routine also uses the pm_timer when possible, as the PIT
362 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
363 * back to normal later in the boot process).
366 #define LAPIC_CAL_LOOPS (HZ/10)
368 static __initdata
int lapic_cal_loops
= -1;
369 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
370 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
371 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
372 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
375 * Temporary interrupt handler.
377 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
379 unsigned long long tsc
= 0;
380 long tapic
= apic_read(APIC_TMCCT
);
381 unsigned long pm
= acpi_pm_read_early();
386 switch (lapic_cal_loops
++) {
388 lapic_cal_t1
= tapic
;
389 lapic_cal_tsc1
= tsc
;
391 lapic_cal_j1
= jiffies
;
394 case LAPIC_CAL_LOOPS
:
395 lapic_cal_t2
= tapic
;
396 lapic_cal_tsc2
= tsc
;
397 if (pm
< lapic_cal_pm1
)
398 pm
+= ACPI_PM_OVRRUN
;
400 lapic_cal_j2
= jiffies
;
405 static int __init
calibrate_APIC_clock(void)
407 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
408 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
409 const long pm_thresh
= pm_100ms
/100;
410 void (*real_handler
)(struct clock_event_device
*dev
);
411 unsigned long deltaj
;
413 int pm_referenced
= 0;
417 /* Replace the global interrupt handler */
418 real_handler
= global_clock_event
->event_handler
;
419 global_clock_event
->event_handler
= lapic_cal_handler
;
422 * Setup the APIC counter to 1e9. There is no way the lapic
423 * can underflow in the 100ms detection time frame
425 __setup_APIC_LVTT(1000000000, 0, 0);
427 /* Let the interrupts run */
430 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
435 /* Restore the real event handler */
436 global_clock_event
->event_handler
= real_handler
;
438 /* Build delta t1-t2 as apic timer counts down */
439 delta
= lapic_cal_t1
- lapic_cal_t2
;
440 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
442 /* Check, if the PM timer is available */
443 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
444 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
450 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
452 if (deltapm
> (pm_100ms
- pm_thresh
) &&
453 deltapm
< (pm_100ms
+ pm_thresh
)) {
454 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
456 res
= (((u64
) deltapm
) * mult
) >> 22;
457 do_div(res
, 1000000);
458 printk(KERN_WARNING
"APIC calibration not consistent "
459 "with PM Timer: %ldms instead of 100ms\n",
461 /* Correct the lapic counter value */
462 res
= (((u64
) delta
) * pm_100ms
);
463 do_div(res
, deltapm
);
464 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
465 "%lu (%ld)\n", (unsigned long) res
, delta
);
471 /* Calculate the scaled math multiplication factor */
472 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
473 lapic_clockevent
.shift
);
474 lapic_clockevent
.max_delta_ns
=
475 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
476 lapic_clockevent
.min_delta_ns
=
477 clockevent_delta2ns(0xF, &lapic_clockevent
);
479 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
481 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
482 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
483 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
487 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
488 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
490 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
491 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
494 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
496 calibration_result
/ (1000000 / HZ
),
497 calibration_result
% (1000000 / HZ
));
500 * Do a sanity check on the APIC calibration result
502 if (calibration_result
< (1000000 / HZ
)) {
505 "APIC frequency too slow, disabling apic timer\n");
509 local_apic_timer_verify_ok
= 1;
511 /* We trust the pm timer based calibration */
512 if (!pm_referenced
) {
513 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
516 * Setup the apic timer manually
518 levt
->event_handler
= lapic_cal_handler
;
519 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
520 lapic_cal_loops
= -1;
522 /* Let the interrupts run */
525 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
530 /* Stop the lapic timer */
531 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
536 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
537 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
539 /* Check, if the jiffies result is consistent */
540 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
541 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
543 local_apic_timer_verify_ok
= 0;
547 if (!local_apic_timer_verify_ok
) {
549 "APIC timer disabled due to verification failure.\n");
557 * Setup the boot APIC
559 * Calibrate and verify the result.
561 void __init
setup_boot_APIC_clock(void)
564 * The local apic timer can be disabled via the kernel
565 * commandline or from the CPU detection code. Register the lapic
566 * timer as a dummy clock event source on SMP systems, so the
567 * broadcast mechanism is used. On UP systems simply ignore it.
569 if (local_apic_timer_disabled
) {
570 /* No broadcast on UP ! */
571 if (num_possible_cpus() > 1) {
572 lapic_clockevent
.mult
= 1;
578 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
579 "calibrating APIC timer ...\n");
581 if (calibrate_APIC_clock()) {
582 /* No broadcast on UP ! */
583 if (num_possible_cpus() > 1)
589 * If nmi_watchdog is set to IO_APIC, we need the
590 * PIT/HPET going. Otherwise register lapic as a dummy
593 if (nmi_watchdog
!= NMI_IO_APIC
)
594 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
596 printk(KERN_WARNING
"APIC timer registered as dummy,"
597 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
599 /* Setup the lapic or request the broadcast */
603 void __devinit
setup_secondary_APIC_clock(void)
609 * The guts of the apic timer interrupt
611 static void local_apic_timer_interrupt(void)
613 int cpu
= smp_processor_id();
614 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
617 * Normally we should not be here till LAPIC has been initialized but
618 * in some cases like kdump, its possible that there is a pending LAPIC
619 * timer interrupt from previous kernel's context and is delivered in
620 * new kernel the moment interrupts are enabled.
622 * Interrupts are enabled early and LAPIC is setup much later, hence
623 * its possible that when we get here evt->event_handler is NULL.
624 * Check for event_handler being NULL and discard the interrupt as
627 if (!evt
->event_handler
) {
629 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
631 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
636 * the NMI deadlock-detector uses this.
638 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
640 evt
->event_handler(evt
);
644 * Local APIC timer interrupt. This is the most natural way for doing
645 * local interrupts, but local timer interrupts can be emulated by
646 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
648 * [ if a single-CPU system runs an SMP kernel then we call the local
649 * interrupt as well. Thus we cannot inline the local irq ... ]
651 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
653 struct pt_regs
*old_regs
= set_irq_regs(regs
);
656 * NOTE! We'd better ACK the irq immediately,
657 * because timer handling can be slow.
661 * update_process_times() expects us to have done irq_enter().
662 * Besides, if we don't timer interrupts ignore the global
663 * interrupt lock, which is the WrongThing (tm) to do.
666 local_apic_timer_interrupt();
669 set_irq_regs(old_regs
);
672 int setup_profiling_timer(unsigned int multiplier
)
678 * Setup extended LVT, AMD specific (K8, family 10h)
680 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
681 * MCE interrupts are supported. Thus MCE offset must be set to 0.
684 #define APIC_EILVT_LVTOFF_MCE 0
685 #define APIC_EILVT_LVTOFF_IBS 1
687 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
689 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
690 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
694 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
696 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
697 return APIC_EILVT_LVTOFF_MCE
;
700 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
702 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
703 return APIC_EILVT_LVTOFF_IBS
;
707 * Local APIC start and shutdown
711 * clear_local_APIC - shutdown the local APIC
713 * This is called, when a CPU is disabled and before rebooting, so the state of
714 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
715 * leftovers during boot.
717 void clear_local_APIC(void)
722 /* APIC hasn't been mapped yet */
726 maxlvt
= lapic_get_maxlvt();
728 * Masking an LVT entry can trigger a local APIC error
729 * if the vector is zero. Mask LVTERR first to prevent this.
732 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
733 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
736 * Careful: we have to set masks only first to deassert
737 * any level-triggered sources.
739 v
= apic_read(APIC_LVTT
);
740 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
741 v
= apic_read(APIC_LVT0
);
742 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
743 v
= apic_read(APIC_LVT1
);
744 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
746 v
= apic_read(APIC_LVTPC
);
747 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
750 /* lets not touch this if we didn't frob it */
751 #ifdef CONFIG_X86_MCE_P4THERMAL
753 v
= apic_read(APIC_LVTTHMR
);
754 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
758 * Clean APIC state for other OSs:
760 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
761 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
762 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
764 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
766 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
768 #ifdef CONFIG_X86_MCE_P4THERMAL
770 apic_write(APIC_LVTTHMR
, APIC_LVT_MASKED
);
772 /* Integrated APIC (!82489DX) ? */
773 if (lapic_is_integrated()) {
775 /* Clear ESR due to Pentium errata 3AP and 11AP */
776 apic_write(APIC_ESR
, 0);
782 * disable_local_APIC - clear and disable the local APIC
784 void disable_local_APIC(void)
791 * Disable APIC (implies clearing of registers
794 value
= apic_read(APIC_SPIV
);
795 value
&= ~APIC_SPIV_APIC_ENABLED
;
796 apic_write(APIC_SPIV
, value
);
799 * When LAPIC was disabled by the BIOS and enabled by the kernel,
800 * restore the disabled state.
802 if (enabled_via_apicbase
) {
805 rdmsr(MSR_IA32_APICBASE
, l
, h
);
806 l
&= ~MSR_IA32_APICBASE_ENABLE
;
807 wrmsr(MSR_IA32_APICBASE
, l
, h
);
812 * If Linux enabled the LAPIC against the BIOS default disable it down before
813 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
814 * not power-off. Additionally clear all LVT entries before disable_local_APIC
815 * for the case where Linux didn't enable the LAPIC.
817 void lapic_shutdown(void)
824 local_irq_save(flags
);
827 if (enabled_via_apicbase
)
828 disable_local_APIC();
830 local_irq_restore(flags
);
834 * This is to verify that we're looking at a real local APIC.
835 * Check these against your board if the CPUs aren't getting
836 * started for no apparent reason.
838 int __init
verify_local_APIC(void)
840 unsigned int reg0
, reg1
;
843 * The version register is read-only in a real APIC.
845 reg0
= apic_read(APIC_LVR
);
846 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
847 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
848 reg1
= apic_read(APIC_LVR
);
849 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
852 * The two version reads above should print the same
853 * numbers. If the second one is different, then we
854 * poke at a non-APIC.
860 * Check if the version looks reasonably.
862 reg1
= GET_APIC_VERSION(reg0
);
863 if (reg1
== 0x00 || reg1
== 0xff)
865 reg1
= lapic_get_maxlvt();
866 if (reg1
< 0x02 || reg1
== 0xff)
870 * The ID register is read/write in a real APIC.
872 reg0
= apic_read(APIC_ID
);
873 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
876 * The next two are just to see if we have sane values.
877 * They're only really relevant if we're in Virtual Wire
878 * compatibility mode, but most boxes are anymore.
880 reg0
= apic_read(APIC_LVT0
);
881 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
882 reg1
= apic_read(APIC_LVT1
);
883 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
889 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
891 void __init
sync_Arb_IDs(void)
894 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
897 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
902 apic_wait_icr_idle();
904 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
906 APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
910 * An initial setup of the virtual wire mode.
912 void __init
init_bsp_APIC(void)
917 * Don't do the setup now if we have a SMP BIOS as the
918 * through-I/O-APIC virtual wire mode might be active.
920 if (smp_found_config
|| !cpu_has_apic
)
924 * Do not trust the local APIC being empty at bootup.
931 value
= apic_read(APIC_SPIV
);
932 value
&= ~APIC_VECTOR_MASK
;
933 value
|= APIC_SPIV_APIC_ENABLED
;
935 /* This bit is reserved on P4/Xeon and should be cleared */
936 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
937 (boot_cpu_data
.x86
== 15))
938 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
940 value
|= APIC_SPIV_FOCUS_DISABLED
;
941 value
|= SPURIOUS_APIC_VECTOR
;
942 apic_write(APIC_SPIV
, value
);
945 * Set up the virtual wire mode.
947 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
949 if (!lapic_is_integrated()) /* 82489DX */
950 value
|= APIC_LVT_LEVEL_TRIGGER
;
951 apic_write(APIC_LVT1
, value
);
954 static void __cpuinit
lapic_setup_esr(void)
956 unsigned long oldvalue
, value
, maxlvt
;
957 if (lapic_is_integrated() && !esr_disable
) {
959 maxlvt
= lapic_get_maxlvt();
960 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
961 apic_write(APIC_ESR
, 0);
962 oldvalue
= apic_read(APIC_ESR
);
964 /* enables sending errors */
965 value
= ERROR_APIC_VECTOR
;
966 apic_write(APIC_LVTERR
, value
);
968 * spec says clear errors after enabling vector.
971 apic_write(APIC_ESR
, 0);
972 value
= apic_read(APIC_ESR
);
973 if (value
!= oldvalue
)
974 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
975 "vector: 0x%08lx after: 0x%08lx\n",
980 * Something untraceable is creating bad interrupts on
981 * secondary quads ... for the moment, just leave the
982 * ESR disabled - we can't do anything useful with the
983 * errors anyway - mbligh
985 printk(KERN_INFO
"Leaving ESR disabled.\n");
987 printk(KERN_INFO
"No ESR for 82489DX.\n");
993 * setup_local_APIC - setup the local APIC
995 void __cpuinit
setup_local_APIC(void)
997 unsigned long value
, integrated
;
1000 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1002 apic_write(APIC_ESR
, 0);
1003 apic_write(APIC_ESR
, 0);
1004 apic_write(APIC_ESR
, 0);
1005 apic_write(APIC_ESR
, 0);
1008 integrated
= lapic_is_integrated();
1011 * Double-check whether this APIC is really registered.
1013 if (!apic_id_registered())
1017 * Intel recommends to set DFR, LDR and TPR before enabling
1018 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1019 * document number 292116). So here it goes...
1024 * Set Task Priority to 'accept all'. We never change this
1027 value
= apic_read(APIC_TASKPRI
);
1028 value
&= ~APIC_TPRI_MASK
;
1029 apic_write(APIC_TASKPRI
, value
);
1032 * After a crash, we no longer service the interrupts and a pending
1033 * interrupt from previous kernel might still have ISR bit set.
1035 * Most probably by now CPU has serviced that pending interrupt and
1036 * it might not have done the ack_APIC_irq() because it thought,
1037 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1038 * does not clear the ISR bit and cpu thinks it has already serivced
1039 * the interrupt. Hence a vector might get locked. It was noticed
1040 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1042 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1043 value
= apic_read(APIC_ISR
+ i
*0x10);
1044 for (j
= 31; j
>= 0; j
--) {
1051 * Now that we are all set up, enable the APIC
1053 value
= apic_read(APIC_SPIV
);
1054 value
&= ~APIC_VECTOR_MASK
;
1058 value
|= APIC_SPIV_APIC_ENABLED
;
1061 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1062 * certain networking cards. If high frequency interrupts are
1063 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1064 * entry is masked/unmasked at a high rate as well then sooner or
1065 * later IOAPIC line gets 'stuck', no more interrupts are received
1066 * from the device. If focus CPU is disabled then the hang goes
1069 * [ This bug can be reproduced easily with a level-triggered
1070 * PCI Ne2000 networking cards and PII/PIII processors, dual
1074 * Actually disabling the focus CPU check just makes the hang less
1075 * frequent as it makes the interrupt distributon model be more
1076 * like LRU than MRU (the short-term load is more even across CPUs).
1077 * See also the comment in end_level_ioapic_irq(). --macro
1080 /* Enable focus processor (bit==0) */
1081 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1084 * Set spurious IRQ vector
1086 value
|= SPURIOUS_APIC_VECTOR
;
1087 apic_write(APIC_SPIV
, value
);
1090 * Set up LVT0, LVT1:
1092 * set up through-local-APIC on the BP's LINT0. This is not
1093 * strictly necessary in pure symmetric-IO mode, but sometimes
1094 * we delegate interrupts to the 8259A.
1097 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1099 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1100 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1101 value
= APIC_DM_EXTINT
;
1102 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1103 smp_processor_id());
1105 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1106 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1107 smp_processor_id());
1109 apic_write(APIC_LVT0
, value
);
1112 * only the BP should see the LINT1 NMI signal, obviously.
1114 if (!smp_processor_id())
1115 value
= APIC_DM_NMI
;
1117 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1118 if (!integrated
) /* 82489DX */
1119 value
|= APIC_LVT_LEVEL_TRIGGER
;
1120 apic_write(APIC_LVT1
, value
);
1123 void __cpuinit
end_local_APIC_setup(void)
1125 unsigned long value
;
1128 /* Disable the local apic timer */
1129 value
= apic_read(APIC_LVTT
);
1130 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1131 apic_write(APIC_LVTT
, value
);
1133 setup_apic_nmi_watchdog(NULL
);
1138 * Detect and initialize APIC
1140 static int __init
detect_init_APIC(void)
1144 /* Disabled by kernel option? */
1148 switch (boot_cpu_data
.x86_vendor
) {
1149 case X86_VENDOR_AMD
:
1150 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1151 (boot_cpu_data
.x86
== 15))
1154 case X86_VENDOR_INTEL
:
1155 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1156 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1163 if (!cpu_has_apic
) {
1165 * Over-ride BIOS and try to enable the local APIC only if
1166 * "lapic" specified.
1168 if (!force_enable_local_apic
) {
1169 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1170 "you can enable it with \"lapic\"\n");
1174 * Some BIOSes disable the local APIC in the APIC_BASE
1175 * MSR. This can only be done in software for Intel P6 or later
1176 * and AMD K7 (Model > 1) or later.
1178 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1179 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1181 "Local APIC disabled by BIOS -- reenabling.\n");
1182 l
&= ~MSR_IA32_APICBASE_BASE
;
1183 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1184 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1185 enabled_via_apicbase
= 1;
1189 * The APIC feature bit should now be enabled
1192 features
= cpuid_edx(1);
1193 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1194 printk(KERN_WARNING
"Could not enable APIC!\n");
1197 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1198 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1200 /* The BIOS may have set up the APIC at some other address */
1201 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1202 if (l
& MSR_IA32_APICBASE_ENABLE
)
1203 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1205 printk(KERN_INFO
"Found and enabled local APIC!\n");
1212 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1217 * init_apic_mappings - initialize APIC mappings
1219 void __init
init_apic_mappings(void)
1222 * If no local APIC can be found then set up a fake all
1223 * zeroes page to simulate the local APIC and another
1224 * one for the IO-APIC.
1226 if (!smp_found_config
&& detect_init_APIC()) {
1227 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1228 apic_phys
= __pa(apic_phys
);
1230 apic_phys
= mp_lapic_addr
;
1232 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1233 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1237 * Fetch the APIC ID of the BSP in case we have a
1238 * default configuration (or the MP table is broken).
1240 if (boot_cpu_physical_apicid
== -1U)
1241 boot_cpu_physical_apicid
= read_apic_id();
1246 * This initializes the IO-APIC and APIC hardware if this is
1250 int apic_version
[MAX_APICS
];
1252 int __init
APIC_init_uniprocessor(void)
1254 if (!smp_found_config
&& !cpu_has_apic
)
1258 * Complain if the BIOS pretends there is one.
1260 if (!cpu_has_apic
&&
1261 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1262 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1263 boot_cpu_physical_apicid
);
1264 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1268 verify_local_APIC();
1273 * Hack: In case of kdump, after a crash, kernel might be booting
1274 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1275 * might be zero if read from MP tables. Get it from LAPIC.
1277 #ifdef CONFIG_CRASH_DUMP
1278 boot_cpu_physical_apicid
= read_apic_id();
1280 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1284 #ifdef CONFIG_X86_IO_APIC
1285 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1287 localise_nmi_watchdog();
1288 end_local_APIC_setup();
1289 #ifdef CONFIG_X86_IO_APIC
1290 if (smp_found_config
)
1291 if (!skip_ioapic_setup
&& nr_ioapics
)
1300 * Local APIC interrupts
1304 * This interrupt should _never_ happen with our APIC/SMP architecture
1306 void smp_spurious_interrupt(struct pt_regs
*regs
)
1312 * Check if this really is a spurious interrupt and ACK it
1313 * if it is a vectored one. Just in case...
1314 * Spurious interrupts should not be ACKed.
1316 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1317 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1320 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1321 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1322 "should never happen.\n", smp_processor_id());
1323 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1328 * This interrupt should never happen with our APIC/SMP architecture
1330 void smp_error_interrupt(struct pt_regs
*regs
)
1332 unsigned long v
, v1
;
1335 /* First tickle the hardware, only then report what went on. -- REW */
1336 v
= apic_read(APIC_ESR
);
1337 apic_write(APIC_ESR
, 0);
1338 v1
= apic_read(APIC_ESR
);
1340 atomic_inc(&irq_err_count
);
1342 /* Here is what the APIC error bits mean:
1345 2: Send accept error
1346 3: Receive accept error
1348 5: Send illegal vector
1349 6: Received illegal vector
1350 7: Illegal register address
1352 printk(KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1353 smp_processor_id(), v
, v1
);
1358 void __init
smp_intr_init(void)
1361 * IRQ0 must be given a fixed assignment and initialized,
1362 * because it's used before the IO-APIC is set up.
1364 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1367 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1368 * IPI, driven by wakeup.
1370 alloc_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1372 /* IPI for invalidation */
1373 alloc_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1375 /* IPI for generic function call */
1376 alloc_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);
1378 /* IPI for single call function */
1379 set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR
,
1380 call_function_single_interrupt
);
1385 * Initialize APIC interrupts
1387 void __init
apic_intr_init(void)
1392 /* self generated IPI for local APIC timer */
1393 alloc_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
1395 /* IPI vectors for APIC spurious and error interrupts */
1396 alloc_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
1397 alloc_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
1399 /* thermal monitor LVT interrupt */
1400 #ifdef CONFIG_X86_MCE_P4THERMAL
1401 alloc_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
1406 * connect_bsp_APIC - attach the APIC to the interrupt system
1408 void __init
connect_bsp_APIC(void)
1412 * Do not trust the local APIC being empty at bootup.
1416 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1417 * local APIC to INT and NMI lines.
1419 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1420 "enabling APIC mode.\n");
1428 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1429 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1431 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1434 void disconnect_bsp_APIC(int virt_wire_setup
)
1438 * Put the board back into PIC mode (has an effect only on
1439 * certain older boards). Note that APIC interrupts, including
1440 * IPIs, won't work beyond this point! The only exception are
1443 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1444 "entering PIC mode.\n");
1448 /* Go back to Virtual Wire compatibility mode */
1449 unsigned long value
;
1451 /* For the spurious interrupt use vector F, and enable it */
1452 value
= apic_read(APIC_SPIV
);
1453 value
&= ~APIC_VECTOR_MASK
;
1454 value
|= APIC_SPIV_APIC_ENABLED
;
1456 apic_write(APIC_SPIV
, value
);
1458 if (!virt_wire_setup
) {
1460 * For LVT0 make it edge triggered, active high,
1461 * external and enabled
1463 value
= apic_read(APIC_LVT0
);
1464 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1465 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1466 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1467 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1468 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1469 apic_write(APIC_LVT0
, value
);
1472 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1476 * For LVT1 make it edge triggered, active high, nmi and
1479 value
= apic_read(APIC_LVT1
);
1481 APIC_MODE_MASK
| APIC_SEND_PENDING
|
1482 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1483 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1484 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1485 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1486 apic_write(APIC_LVT1
, value
);
1490 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
1492 void __cpuinit
generic_processor_info(int apicid
, int version
)
1496 physid_mask_t phys_cpu
;
1501 if (version
== 0x0) {
1502 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1503 "fixing up to 0x10. (tell your hw vendor)\n",
1507 apic_version
[apicid
] = version
;
1509 phys_cpu
= apicid_to_cpu_present(apicid
);
1510 physids_or(phys_cpu_present_map
, phys_cpu_present_map
, phys_cpu
);
1512 if (num_processors
>= NR_CPUS
) {
1513 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1514 " Processor ignored.\n", NR_CPUS
);
1518 if (num_processors
>= maxcpus
) {
1519 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1520 " Processor ignored.\n", maxcpus
);
1525 cpus_complement(tmp_map
, cpu_present_map
);
1526 cpu
= first_cpu(tmp_map
);
1528 if (apicid
== boot_cpu_physical_apicid
)
1530 * x86_bios_cpu_apicid is required to have processors listed
1531 * in same order as logical cpu numbers. Hence the first
1532 * entry is BSP, and so on.
1536 if (apicid
> max_physical_apicid
)
1537 max_physical_apicid
= apicid
;
1540 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1541 * but we need to work other dependencies like SMP_SUSPEND etc
1542 * before this can be done without some confusion.
1543 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1544 * - Ashok Raj <ashok.raj@intel.com>
1546 if (max_physical_apicid
>= 8) {
1547 switch (boot_cpu_data
.x86_vendor
) {
1548 case X86_VENDOR_INTEL
:
1549 if (!APIC_XAPIC(version
)) {
1553 /* If P4 and above fall through */
1554 case X86_VENDOR_AMD
:
1559 /* are we being called early in kernel startup? */
1560 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1561 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1562 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1564 cpu_to_apicid
[cpu
] = apicid
;
1565 bios_cpu_apicid
[cpu
] = apicid
;
1567 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1568 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1571 cpu_set(cpu
, cpu_possible_map
);
1572 cpu_set(cpu
, cpu_present_map
);
1582 /* r/w apic fields */
1583 unsigned int apic_id
;
1584 unsigned int apic_taskpri
;
1585 unsigned int apic_ldr
;
1586 unsigned int apic_dfr
;
1587 unsigned int apic_spiv
;
1588 unsigned int apic_lvtt
;
1589 unsigned int apic_lvtpc
;
1590 unsigned int apic_lvt0
;
1591 unsigned int apic_lvt1
;
1592 unsigned int apic_lvterr
;
1593 unsigned int apic_tmict
;
1594 unsigned int apic_tdcr
;
1595 unsigned int apic_thmr
;
1598 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1600 unsigned long flags
;
1603 if (!apic_pm_state
.active
)
1606 maxlvt
= lapic_get_maxlvt();
1608 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1609 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1610 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1611 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1612 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1613 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1615 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1616 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1617 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1618 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1619 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1620 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1621 #ifdef CONFIG_X86_MCE_P4THERMAL
1623 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1626 local_irq_save(flags
);
1627 disable_local_APIC();
1628 local_irq_restore(flags
);
1632 static int lapic_resume(struct sys_device
*dev
)
1635 unsigned long flags
;
1638 if (!apic_pm_state
.active
)
1641 maxlvt
= lapic_get_maxlvt();
1643 local_irq_save(flags
);
1646 * Make sure the APICBASE points to the right address
1648 * FIXME! This will be wrong if we ever support suspend on
1649 * SMP! We'll need to do this as part of the CPU restore!
1651 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1652 l
&= ~MSR_IA32_APICBASE_BASE
;
1653 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1654 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1656 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1657 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1658 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1659 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1660 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1661 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1662 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1663 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1664 #ifdef CONFIG_X86_MCE_P4THERMAL
1666 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1669 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1670 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1671 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1672 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1673 apic_write(APIC_ESR
, 0);
1674 apic_read(APIC_ESR
);
1675 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1676 apic_write(APIC_ESR
, 0);
1677 apic_read(APIC_ESR
);
1678 local_irq_restore(flags
);
1683 * This device has no shutdown method - fully functioning local APICs
1684 * are needed on every CPU up until machine_halt/restart/poweroff.
1687 static struct sysdev_class lapic_sysclass
= {
1689 .resume
= lapic_resume
,
1690 .suspend
= lapic_suspend
,
1693 static struct sys_device device_lapic
= {
1695 .cls
= &lapic_sysclass
,
1698 static void __devinit
apic_pm_activate(void)
1700 apic_pm_state
.active
= 1;
1703 static int __init
init_lapic_sysfs(void)
1709 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1711 error
= sysdev_class_register(&lapic_sysclass
);
1713 error
= sysdev_register(&device_lapic
);
1716 device_initcall(init_lapic_sysfs
);
1718 #else /* CONFIG_PM */
1720 static void apic_pm_activate(void) { }
1722 #endif /* CONFIG_PM */
1725 * APIC command line parameters
1727 static int __init
parse_lapic(char *arg
)
1729 force_enable_local_apic
= 1;
1732 early_param("lapic", parse_lapic
);
1734 static int __init
parse_nolapic(char *arg
)
1737 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1740 early_param("nolapic", parse_nolapic
);
1742 static int __init
parse_disable_lapic_timer(char *arg
)
1744 local_apic_timer_disabled
= 1;
1747 early_param("nolapic_timer", parse_disable_lapic_timer
);
1749 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1751 local_apic_timer_c2_ok
= 1;
1754 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1756 static int __init
apic_set_verbosity(char *arg
)
1761 if (strcmp(arg
, "debug") == 0)
1762 apic_verbosity
= APIC_DEBUG
;
1763 else if (strcmp(arg
, "verbose") == 0)
1764 apic_verbosity
= APIC_VERBOSE
;
1768 early_param("apic", apic_set_verbosity
);
1770 static int __init
lapic_insert_resource(void)
1775 /* Put local APIC into the resource map. */
1776 lapic_resource
.start
= apic_phys
;
1777 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1778 insert_resource(&iomem_resource
, &lapic_resource
);
1784 * need call insert after e820_reserve_resources()
1785 * that is using request_resource
1787 late_initcall(lapic_insert_resource
);