2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
11 * Define the pci_ops for TX3927.
13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com>
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #include <linux/types.h>
37 #include <linux/pci.h>
38 #include <linux/kernel.h>
39 #include <linux/init.h>
41 #include <asm/addrspace.h>
42 #include <asm/txx9/tx3927.h>
44 static inline int mkaddr(unsigned char bus
, unsigned char dev_fn
,
47 if (bus
== 0 && dev_fn
>= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU
, 0))
48 return PCIBIOS_DEVICE_NOT_FOUND
;
50 tx3927_pcicptr
->ica
= ((bus
& 0xff) << 0x10) |
51 ((dev_fn
& 0xff) << 0x08) |
54 /* clear M_ABORT and Disable M_ABORT Int. */
55 tx3927_pcicptr
->pcistat
|= PCI_STATUS_REC_MASTER_ABORT
;
56 tx3927_pcicptr
->pcistatim
&= ~PCI_STATUS_REC_MASTER_ABORT
;
58 return PCIBIOS_SUCCESSFUL
;
61 static inline int check_abort(void)
63 if (tx3927_pcicptr
->pcistat
& PCI_STATUS_REC_MASTER_ABORT
)
64 tx3927_pcicptr
->pcistat
|= PCI_STATUS_REC_MASTER_ABORT
;
65 tx3927_pcicptr
->pcistatim
|= PCI_STATUS_REC_MASTER_ABORT
;
66 return PCIBIOS_DEVICE_NOT_FOUND
;
68 return PCIBIOS_SUCCESSFUL
;
71 static int tx3927_pci_read_config(struct pci_bus
*bus
, unsigned int devfn
,
72 int where
, int size
, u32
* val
)
76 ret
= mkaddr(bus
->number
, devfn
, where
);
82 *val
= *(volatile u8
*) ((unsigned long) & tx3927_pcicptr
->icd
| (where
& 3));
86 *val
= le16_to_cpu(*(volatile u16
*) ((unsigned long) & tx3927_pcicptr
->icd
| (where
& 3)));
90 *val
= le32_to_cpu(tx3927_pcicptr
->icd
);
97 static int tx3927_pci_write_config(struct pci_bus
*bus
, unsigned int devfn
,
98 int where
, int size
, u32 val
)
102 ret
= mkaddr(bus
->number
, devfn
, where
);
108 *(volatile u8
*) ((unsigned long) & tx3927_pcicptr
->icd
| (where
& 3)) = val
;
112 *(volatile u16
*) ((unsigned long) & tx3927_pcicptr
->icd
| (where
& 2)) =
117 tx3927_pcicptr
->icd
= cpu_to_le32(val
);
120 if (tx3927_pcicptr
->pcistat
& PCI_STATUS_REC_MASTER_ABORT
)
121 tx3927_pcicptr
->pcistat
|= PCI_STATUS_REC_MASTER_ABORT
;
122 tx3927_pcicptr
->pcistatim
|= PCI_STATUS_REC_MASTER_ABORT
;
123 return PCIBIOS_DEVICE_NOT_FOUND
;
125 return check_abort();
128 static struct pci_ops tx3927_pci_ops
= {
129 .read
= tx3927_pci_read_config
,
130 .write
= tx3927_pci_write_config
,
133 void __init
tx3927_pcic_setup(struct pci_controller
*channel
,
134 unsigned long sdram_size
, int extarb
)
137 unsigned long io_base
=
138 channel
->io_resource
->start
+ mips_io_port_base
- IO_BASE
;
139 unsigned long io_size
=
140 channel
->io_resource
->end
- channel
->io_resource
->start
;
141 unsigned long io_pciaddr
=
142 channel
->io_resource
->start
- channel
->io_offset
;
143 unsigned long mem_base
=
144 channel
->mem_resource
->start
;
145 unsigned long mem_size
=
146 channel
->mem_resource
->end
- channel
->mem_resource
->start
;
147 unsigned long mem_pciaddr
=
148 channel
->mem_resource
->start
- channel
->mem_offset
;
150 printk(KERN_INFO
"TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s",
151 tx3927_pcicptr
->did
, tx3927_pcicptr
->vid
,
153 extarb
? "External" : "Internal");
154 channel
->pci_ops
= &tx3927_pci_ops
;
156 local_irq_save(flags
);
157 /* Disable External PCI Config. Access */
158 tx3927_pcicptr
->lbc
= TX3927_PCIC_LBC_EPCAD
;
160 tx3927_pcicptr
->lbc
|= TX3927_PCIC_LBC_IBSE
|
161 TX3927_PCIC_LBC_TIBSE
|
162 TX3927_PCIC_LBC_TMFBSE
| TX3927_PCIC_LBC_MSDSE
;
164 /* LB->PCI mappings */
165 tx3927_pcicptr
->iomas
= ~(io_size
- 1);
166 tx3927_pcicptr
->ilbioma
= io_base
;
167 tx3927_pcicptr
->ipbioma
= io_pciaddr
;
168 tx3927_pcicptr
->mmas
= ~(mem_size
- 1);
169 tx3927_pcicptr
->ilbmma
= mem_base
;
170 tx3927_pcicptr
->ipbmma
= mem_pciaddr
;
171 /* PCI->LB mappings */
172 tx3927_pcicptr
->iobas
= 0xffffffff;
173 tx3927_pcicptr
->ioba
= 0;
174 tx3927_pcicptr
->tlbioma
= 0;
175 tx3927_pcicptr
->mbas
= ~(sdram_size
- 1);
176 tx3927_pcicptr
->mba
= 0;
177 tx3927_pcicptr
->tlbmma
= 0;
178 /* Enable Direct mapping Address Space Decoder */
179 tx3927_pcicptr
->lbc
|= TX3927_PCIC_LBC_ILMDE
| TX3927_PCIC_LBC_ILIDE
;
181 /* Clear All Local Bus Status */
182 tx3927_pcicptr
->lbstat
= TX3927_PCIC_LBIM_ALL
;
183 /* Enable All Local Bus Interrupts */
184 tx3927_pcicptr
->lbim
= TX3927_PCIC_LBIM_ALL
;
185 /* Clear All PCI Status Error */
186 tx3927_pcicptr
->pcistat
= TX3927_PCIC_PCISTATIM_ALL
;
187 /* Enable All PCI Status Error Interrupts */
188 tx3927_pcicptr
->pcistatim
= TX3927_PCIC_PCISTATIM_ALL
;
190 /* PCIC Int => IRC IRQ10 */
191 tx3927_pcicptr
->il
= TX3927_IR_PCI
;
192 /* Target Control (per errata) */
193 tx3927_pcicptr
->tc
= TX3927_PCIC_TC_OF8E
| TX3927_PCIC_TC_IF8E
;
195 /* Enable Bus Arbiter */
197 tx3927_pcicptr
->pbapmc
= TX3927_PCIC_PBAPMC_PBAEN
;
199 tx3927_pcicptr
->pcicmd
= PCI_COMMAND_MASTER
|
202 PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
203 local_irq_restore(flags
);