arch/sh/boards/mach-se/7724/setup.c

   1 /*
   2  * linux/arch/sh/boards/se/7724/setup.c
   3  *
   4  * Copyright (C) 2009 Renesas Solutions Corp.
   5  *
   6  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/device.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/mtd/physmap.h>
  18 #include <linux/delay.h>
  19 #include <linux/smc91x.h>
  20 #include <linux/gpio.h>
  21 #include <linux/input.h>
  22 #include <video/sh_mobile_lcdc.h>
  23 #include <media/sh_mobile_ceu.h>
  24 #include <asm/io.h>
  25 #include <asm/heartbeat.h>
  26 #include <asm/sh_eth.h>
  27 #include <asm/clock.h>
  28 #include <asm/sh_keysc.h>
  29 #include <cpu/sh7724.h>
  30 #include <mach-se/mach/se7724.h>
  31
  32 /*
  33  * SWx    1234 5678
  34  * ------------------------------------
  35  * SW31 : 1001 1100    : default
  36  * SW32 : 0111 1111    : use on board flash
  37  *
  38  * SW41 : abxx xxxx  -> a = 0 : Analog  monitor
  39  *                          1 : Digital monitor
  40  *                      b = 0 : VGA
  41  *                          1 : SVGA
  42  */
  43
  44 /* Heartbeat */
  45 static struct heartbeat_data heartbeat_data = {
  46         .regsize = 16,
  47 };
  48
  49 static struct resource heartbeat_resources[] = {
  50         [0] = {
  51                 .start  = PA_LED,
  52                 .end    = PA_LED,
  53                 .flags  = IORESOURCE_MEM,
  54         },
  55 };
  56
  57 static struct platform_device heartbeat_device = {
  58         .name           = "heartbeat",
  59         .id             = -1,
  60         .dev = {
  61                 .platform_data = &heartbeat_data,
  62         },
  63         .num_resources  = ARRAY_SIZE(heartbeat_resources),
  64         .resource       = heartbeat_resources,
  65 };
  66
  67 /* LAN91C111 */
  68 static struct smc91x_platdata smc91x_info = {
  69         .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  70 };
  71
  72 static struct resource smc91x_eth_resources[] = {
  73         [0] = {
  74                 .name   = "SMC91C111" ,
  75                 .start  = 0x1a300300,
  76                 .end    = 0x1a30030f,
  77                 .flags  = IORESOURCE_MEM,
  78         },
  79         [1] = {
  80                 .start  = IRQ0_SMC,
  81                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  82         },
  83 };
  84
  85 static struct platform_device smc91x_eth_device = {
  86         .name   = "smc91x",
  87         .num_resources  = ARRAY_SIZE(smc91x_eth_resources),
  88         .resource       = smc91x_eth_resources,
  89         .dev    = {
  90                 .platform_data  = &smc91x_info,
  91         },
  92 };
  93
  94 /* MTD */
  95 static struct mtd_partition nor_flash_partitions[] = {
  96         {
  97                 .name = "uboot",
  98                 .offset = 0,
  99                 .size = (1 * 1024 * 1024),
 100                 .mask_flags = MTD_WRITEABLE,    /* Read-only */
 101         }, {
 102                 .name = "kernel",
 103                 .offset = MTDPART_OFS_APPEND,
 104                 .size = (2 * 1024 * 1024),
 105         }, {
 106                 .name = "free-area",
 107                 .offset = MTDPART_OFS_APPEND,
 108                 .size = MTDPART_SIZ_FULL,
 109         },
 110 };
 111
 112 static struct physmap_flash_data nor_flash_data = {
 113         .width          = 2,
 114         .parts          = nor_flash_partitions,
 115         .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
 116 };
 117
 118 static struct resource nor_flash_resources[] = {
 119         [0] = {
 120                 .name   = "NOR Flash",
 121                 .start  = 0x00000000,
 122                 .end    = 0x01ffffff,
 123                 .flags  = IORESOURCE_MEM,
 124         }
 125 };
 126
 127 static struct platform_device nor_flash_device = {
 128         .name           = "physmap-flash",
 129         .resource       = nor_flash_resources,
 130         .num_resources  = ARRAY_SIZE(nor_flash_resources),
 131         .dev            = {
 132                 .platform_data = &nor_flash_data,
 133         },
 134 };
 135
 136 /* LCDC */
 137 static struct sh_mobile_lcdc_info lcdc_info = {
 138         .clock_source = LCDC_CLK_EXTERNAL,
 139         .ch[0] = {
 140                 .chan = LCDC_CHAN_MAINLCD,
 141                 .bpp = 16,
 142                 .clock_divider = 1,
 143                 .lcd_cfg = {
 144                         .name = "LB070WV1",
 145                         .sync = 0, /* hsync and vsync are active low */
 146                 },
 147                 .lcd_size_cfg = { /* 7.0 inch */
 148                         .width = 152,
 149                         .height = 91,
 150                 },
 151                 .board_cfg = {
 152                 },
 153         }
 154 };
 155
 156 static struct resource lcdc_resources[] = {
 157         [0] = {
 158                 .name   = "LCDC",
 159                 .start  = 0xfe940000,
 160                 .end    = 0xfe941fff,
 161                 .flags  = IORESOURCE_MEM,
 162         },
 163         [1] = {
 164                 .start  = 106,
 165                 .flags  = IORESOURCE_IRQ,
 166         },
 167 };
 168
 169 static struct platform_device lcdc_device = {
 170         .name           = "sh_mobile_lcdc_fb",
 171         .num_resources  = ARRAY_SIZE(lcdc_resources),
 172         .resource       = lcdc_resources,
 173         .dev            = {
 174                 .platform_data  = &lcdc_info,
 175         },
 176 };
 177
 178 /* CEU0 */
 179 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
 180         .flags = SH_CEU_FLAG_USE_8BIT_BUS,
 181 };
 182
 183 static struct resource ceu0_resources[] = {
 184         [0] = {
 185                 .name   = "CEU0",
 186                 .start  = 0xfe910000,
 187                 .end    = 0xfe91009f,
 188                 .flags  = IORESOURCE_MEM,
 189         },
 190         [1] = {
 191                 .start  = 52,
 192                 .flags  = IORESOURCE_IRQ,
 193         },
 194         [2] = {
 195                 /* place holder for contiguous memory */
 196         },
 197 };
 198
 199 static struct platform_device ceu0_device = {
 200         .name           = "sh_mobile_ceu",
 201         .id             = 0, /* "ceu0" clock */
 202         .num_resources  = ARRAY_SIZE(ceu0_resources),
 203         .resource       = ceu0_resources,
 204         .dev    = {
 205                 .platform_data  = &sh_mobile_ceu0_info,
 206         },
 207 };
 208
 209 /* CEU1 */
 210 static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
 211         .flags = SH_CEU_FLAG_USE_8BIT_BUS,
 212 };
 213
 214 static struct resource ceu1_resources[] = {
 215         [0] = {
 216                 .name   = "CEU1",
 217                 .start  = 0xfe914000,
 218                 .end    = 0xfe91409f,
 219                 .flags  = IORESOURCE_MEM,
 220         },
 221         [1] = {
 222                 .start  = 63,
 223                 .flags  = IORESOURCE_IRQ,
 224         },
 225         [2] = {
 226                 /* place holder for contiguous memory */
 227         },
 228 };
 229
 230 static struct platform_device ceu1_device = {
 231         .name           = "sh_mobile_ceu",
 232         .id             = 1, /* "ceu1" clock */
 233         .num_resources  = ARRAY_SIZE(ceu1_resources),
 234         .resource       = ceu1_resources,
 235         .dev    = {
 236                 .platform_data  = &sh_mobile_ceu1_info,
 237         },
 238 };
 239
 240 /* KEYSC */
 241 static struct sh_keysc_info keysc_info = {
 242         .mode = SH_KEYSC_MODE_1,
 243         .scan_timing = 10,
 244         .delay = 50,
 245         .keycodes = {
 246                 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
 247                 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
 248                 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
 249                 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
 250                 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
 251                 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
 252         },
 253 };
 254
 255 static struct resource keysc_resources[] = {
 256         [0] = {
 257                 .start  = 0x1a204000,
 258                 .end    = 0x1a20400f,
 259                 .flags  = IORESOURCE_MEM,
 260         },
 261         [1] = {
 262                 .start  = IRQ0_KEY,
 263                 .flags  = IORESOURCE_IRQ,
 264         },
 265 };
 266
 267 static struct platform_device keysc_device = {
 268         .name           = "sh_keysc",
 269         .id             = 0, /* "keysc0" clock */
 270         .num_resources  = ARRAY_SIZE(keysc_resources),
 271         .resource       = keysc_resources,
 272         .dev    = {
 273                 .platform_data  = &keysc_info,
 274         },
 275 };
 276
 277 /* SH Eth */
 278 static struct resource sh_eth_resources[] = {
 279         [0] = {
 280                 .start = SH_ETH_ADDR,
 281                 .end   = SH_ETH_ADDR + 0x1FC,
 282                 .flags = IORESOURCE_MEM,
 283         },
 284         [1] = {
 285                 .start = 91,
 286                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 287         },
 288 };
 289
 290 struct sh_eth_plat_data sh_eth_plat = {
 291         .phy = 0x1f, /* SMSC LAN8187 */
 292         .edmac_endian = EDMAC_LITTLE_ENDIAN,
 293 };
 294
 295 static struct platform_device sh_eth_device = {
 296         .name = "sh-eth",
 297         .id     = 0,
 298         .dev = {
 299                 .platform_data = &sh_eth_plat,
 300         },
 301         .num_resources = ARRAY_SIZE(sh_eth_resources),
 302         .resource = sh_eth_resources,
 303 };
 304
 305 static struct platform_device *ms7724se_devices[] __initdata = {
 306         &heartbeat_device,
 307         &smc91x_eth_device,
 308         &lcdc_device,
 309         &nor_flash_device,
 310         &ceu0_device,
 311         &ceu1_device,
 312         &keysc_device,
 313         &sh_eth_device,
 314 };
 315
 316 #define EEPROM_OP   0xBA206000
 317 #define EEPROM_ADR  0xBA206004
 318 #define EEPROM_DATA 0xBA20600C
 319 #define EEPROM_STAT 0xBA206010
 320 #define EEPROM_STRT 0xBA206014
 321 static int __init sh_eth_is_eeprom_ready(void)
 322 {
 323         int t = 10000;
 324
 325         while (t--) {
 326                 if (!ctrl_inw(EEPROM_STAT))
 327                         return 1;
 328                 cpu_relax();
 329         }
 330
 331         printk(KERN_ERR "ms7724se can not access to eeprom\n");
 332         return 0;
 333 }
 334
 335 static void __init sh_eth_init(void)
 336 {
 337         int i;
 338         u16 mac[3];
 339
 340         /* check EEPROM status */
 341         if (!sh_eth_is_eeprom_ready())
 342                 return;
 343
 344         /* read MAC addr from EEPROM */
 345         for (i = 0 ; i < 3 ; i++) {
 346                 ctrl_outw(0x0, EEPROM_OP); /* read */
 347                 ctrl_outw(i*2, EEPROM_ADR);
 348                 ctrl_outw(0x1, EEPROM_STRT);
 349                 if (!sh_eth_is_eeprom_ready())
 350                         return;
 351
 352                 mac[i] = ctrl_inw(EEPROM_DATA);
 353                 mac[i] = ((mac[i] & 0xFF) << 8) | (mac[i] >> 8); /* swap */
 354         }
 355
 356         /* reset sh-eth */
 357         ctrl_outl(0x1, SH_ETH_ADDR + 0x0);
 358
 359         /* set MAC addr */
 360         ctrl_outl(((mac[0] << 16) | (mac[1])), SH_ETH_MAHR);
 361         ctrl_outl((mac[2]), SH_ETH_MALR);
 362 }
 363
 364 #define SW4140    0xBA201000
 365 #define FPGA_OUT  0xBA200400
 366 #define PORT_HIZA 0xA4050158
 367
 368 #define SW41_A    0x0100
 369 #define SW41_B    0x0200
 370 #define SW41_C    0x0400
 371 #define SW41_D    0x0800
 372 #define SW41_E    0x1000
 373 #define SW41_F    0x2000
 374 #define SW41_G    0x4000
 375 #define SW41_H    0x8000
 376 static int __init devices_setup(void)
 377 {
 378         u16 sw = ctrl_inw(SW4140); /* select camera, monitor */
 379
 380         /* Reset Release */
 381         ctrl_outw(ctrl_inw(FPGA_OUT) &
 382                   ~((1 << 1)  | /* LAN */
 383                     (1 << 6)  | /* VIDEO DAC */
 384                     (1 << 12) | /* USB0 */
 385                     (1 << 14)), /* RMII */
 386                   FPGA_OUT);
 387
 388         /* enable IRQ 0,1,2 */
 389         gpio_request(GPIO_FN_INTC_IRQ0, NULL);
 390         gpio_request(GPIO_FN_INTC_IRQ1, NULL);
 391         gpio_request(GPIO_FN_INTC_IRQ2, NULL);
 392
 393         /* enable SCIFA3 */
 394         gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
 395         gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
 396         gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
 397         gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
 398         gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
 399
 400         /* enable LCDC */
 401         gpio_request(GPIO_FN_LCDD23,   NULL);
 402         gpio_request(GPIO_FN_LCDD22,   NULL);
 403         gpio_request(GPIO_FN_LCDD21,   NULL);
 404         gpio_request(GPIO_FN_LCDD20,   NULL);
 405         gpio_request(GPIO_FN_LCDD19,   NULL);
 406         gpio_request(GPIO_FN_LCDD18,   NULL);
 407         gpio_request(GPIO_FN_LCDD17,   NULL);
 408         gpio_request(GPIO_FN_LCDD16,   NULL);
 409         gpio_request(GPIO_FN_LCDD15,   NULL);
 410         gpio_request(GPIO_FN_LCDD14,   NULL);
 411         gpio_request(GPIO_FN_LCDD13,   NULL);
 412         gpio_request(GPIO_FN_LCDD12,   NULL);
 413         gpio_request(GPIO_FN_LCDD11,   NULL);
 414         gpio_request(GPIO_FN_LCDD10,   NULL);
 415         gpio_request(GPIO_FN_LCDD9,    NULL);
 416         gpio_request(GPIO_FN_LCDD8,    NULL);
 417         gpio_request(GPIO_FN_LCDD7,    NULL);
 418         gpio_request(GPIO_FN_LCDD6,    NULL);
 419         gpio_request(GPIO_FN_LCDD5,    NULL);
 420         gpio_request(GPIO_FN_LCDD4,    NULL);
 421         gpio_request(GPIO_FN_LCDD3,    NULL);
 422         gpio_request(GPIO_FN_LCDD2,    NULL);
 423         gpio_request(GPIO_FN_LCDD1,    NULL);
 424         gpio_request(GPIO_FN_LCDD0,    NULL);
 425         gpio_request(GPIO_FN_LCDDISP,  NULL);
 426         gpio_request(GPIO_FN_LCDHSYN,  NULL);
 427         gpio_request(GPIO_FN_LCDDCK,   NULL);
 428         gpio_request(GPIO_FN_LCDVSYN,  NULL);
 429         gpio_request(GPIO_FN_LCDDON,   NULL);
 430         gpio_request(GPIO_FN_LCDVEPWC, NULL);
 431         gpio_request(GPIO_FN_LCDVCPWC, NULL);
 432         gpio_request(GPIO_FN_LCDRD,    NULL);
 433         gpio_request(GPIO_FN_LCDLCLK,  NULL);
 434         ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
 435
 436         /* enable CEU0 */
 437         gpio_request(GPIO_FN_VIO0_D15, NULL);
 438         gpio_request(GPIO_FN_VIO0_D14, NULL);
 439         gpio_request(GPIO_FN_VIO0_D13, NULL);
 440         gpio_request(GPIO_FN_VIO0_D12, NULL);
 441         gpio_request(GPIO_FN_VIO0_D11, NULL);
 442         gpio_request(GPIO_FN_VIO0_D10, NULL);
 443         gpio_request(GPIO_FN_VIO0_D9,  NULL);
 444         gpio_request(GPIO_FN_VIO0_D8,  NULL);
 445         gpio_request(GPIO_FN_VIO0_D7,  NULL);
 446         gpio_request(GPIO_FN_VIO0_D6,  NULL);
 447         gpio_request(GPIO_FN_VIO0_D5,  NULL);
 448         gpio_request(GPIO_FN_VIO0_D4,  NULL);
 449         gpio_request(GPIO_FN_VIO0_D3,  NULL);
 450         gpio_request(GPIO_FN_VIO0_D2,  NULL);
 451         gpio_request(GPIO_FN_VIO0_D1,  NULL);
 452         gpio_request(GPIO_FN_VIO0_D0,  NULL);
 453         gpio_request(GPIO_FN_VIO0_VD,  NULL);
 454         gpio_request(GPIO_FN_VIO0_CLK, NULL);
 455         gpio_request(GPIO_FN_VIO0_FLD, NULL);
 456         gpio_request(GPIO_FN_VIO0_HD,  NULL);
 457         platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
 458
 459         /* enable CEU1 */
 460         gpio_request(GPIO_FN_VIO1_D7,  NULL);
 461         gpio_request(GPIO_FN_VIO1_D6,  NULL);
 462         gpio_request(GPIO_FN_VIO1_D5,  NULL);
 463         gpio_request(GPIO_FN_VIO1_D4,  NULL);
 464         gpio_request(GPIO_FN_VIO1_D3,  NULL);
 465         gpio_request(GPIO_FN_VIO1_D2,  NULL);
 466         gpio_request(GPIO_FN_VIO1_D1,  NULL);
 467         gpio_request(GPIO_FN_VIO1_D0,  NULL);
 468         gpio_request(GPIO_FN_VIO1_FLD, NULL);
 469         gpio_request(GPIO_FN_VIO1_HD,  NULL);
 470         gpio_request(GPIO_FN_VIO1_VD,  NULL);
 471         gpio_request(GPIO_FN_VIO1_CLK, NULL);
 472         platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
 473
 474         /* KEYSC */
 475         gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
 476         gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
 477         gpio_request(GPIO_FN_KEYIN4,      NULL);
 478         gpio_request(GPIO_FN_KEYIN3,      NULL);
 479         gpio_request(GPIO_FN_KEYIN2,      NULL);
 480         gpio_request(GPIO_FN_KEYIN1,      NULL);
 481         gpio_request(GPIO_FN_KEYIN0,      NULL);
 482         gpio_request(GPIO_FN_KEYOUT3,     NULL);
 483         gpio_request(GPIO_FN_KEYOUT2,     NULL);
 484         gpio_request(GPIO_FN_KEYOUT1,     NULL);
 485         gpio_request(GPIO_FN_KEYOUT0,     NULL);
 486
 487         /*
 488          * enable SH-Eth
 489          *
 490          * please remove J33 pin from your board !!
 491          *
 492          * ms7724 board should not use GPIO_FN_LNKSTA pin
 493          * So, This time PTX5 is set to input pin
 494          */
 495         gpio_request(GPIO_FN_RMII_RXD0,    NULL);
 496         gpio_request(GPIO_FN_RMII_RXD1,    NULL);
 497         gpio_request(GPIO_FN_RMII_TXD0,    NULL);
 498         gpio_request(GPIO_FN_RMII_TXD1,    NULL);
 499         gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
 500         gpio_request(GPIO_FN_RMII_TX_EN,   NULL);
 501         gpio_request(GPIO_FN_RMII_RX_ER,   NULL);
 502         gpio_request(GPIO_FN_RMII_CRS_DV,  NULL);
 503         gpio_request(GPIO_FN_MDIO,         NULL);
 504         gpio_request(GPIO_FN_MDC,          NULL);
 505         gpio_request(GPIO_PTX5, NULL);
 506         gpio_direction_input(GPIO_PTX5);
 507         sh_eth_init();
 508
 509         if (sw & SW41_B) {
 510                 /* SVGA */
 511                 lcdc_info.ch[0].lcd_cfg.xres         = 800;
 512                 lcdc_info.ch[0].lcd_cfg.yres         = 600;
 513                 lcdc_info.ch[0].lcd_cfg.left_margin  = 142;
 514                 lcdc_info.ch[0].lcd_cfg.right_margin = 52;
 515                 lcdc_info.ch[0].lcd_cfg.hsync_len    = 96;
 516                 lcdc_info.ch[0].lcd_cfg.upper_margin = 24;
 517                 lcdc_info.ch[0].lcd_cfg.lower_margin = 2;
 518                 lcdc_info.ch[0].lcd_cfg.vsync_len    = 2;
 519         } else {
 520                 /* VGA */
 521                 lcdc_info.ch[0].lcd_cfg.xres         = 640;
 522                 lcdc_info.ch[0].lcd_cfg.yres         = 480;
 523                 lcdc_info.ch[0].lcd_cfg.left_margin  = 105;
 524                 lcdc_info.ch[0].lcd_cfg.right_margin = 50;
 525                 lcdc_info.ch[0].lcd_cfg.hsync_len    = 96;
 526                 lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
 527                 lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
 528                 lcdc_info.ch[0].lcd_cfg.vsync_len    = 2;
 529         }
 530
 531         if (sw & SW41_A) {
 532                 /* Digital monitor */
 533                 lcdc_info.ch[0].interface_type = RGB18;
 534                 lcdc_info.ch[0].flags          = 0;
 535         } else {
 536                 /* Analog monitor */
 537                 lcdc_info.ch[0].interface_type = RGB24;
 538                 lcdc_info.ch[0].flags          = LCDC_FLAGS_DWPOL;
 539         }
 540
 541         return platform_add_devices(ms7724se_devices,
 542                                     ARRAY_SIZE(ms7724se_devices));
 543 }
 544 device_initcall(devices_setup);
 545
 546 static struct sh_machine_vector mv_ms7724se __initmv = {
 547         .mv_name        = "ms7724se",
 548         .mv_init_irq    = init_se7724_IRQ,
 549         .mv_nr_irqs     = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,
 550 };