crypto/async_tx/async_tx.c

   1 /*
   2  * core routines for the asynchronous memory transfer/transform api
   3  *
   4  * Copyright © 2006, Intel Corporation.
   5  *
   6  *      Dan Williams <dan.j.williams@intel.com>
   7  *
   8  *      with architecture considerations by:
   9  *      Neil Brown <neilb@suse.de>
  10  *      Jeff Garzik <jeff@garzik.org>
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms and conditions of the GNU General Public License,
  14  * version 2, as published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along with
  22  * this program; if not, write to the Free Software Foundation, Inc.,
  23  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  24  *
  25  */
  26 #include <linux/kernel.h>
  27 #include <linux/async_tx.h>
  28
  29 #ifdef CONFIG_DMA_ENGINE
  30 static enum dma_state_client
  31 dma_channel_add_remove(struct dma_client *client,
  32         struct dma_chan *chan, enum dma_state state);
  33
  34 static struct dma_client async_tx_dma = {
  35         .event_callback = dma_channel_add_remove,
  36         /* .cap_mask == 0 defaults to all channels */
  37 };
  38
  39 /**
  40  * dma_cap_mask_all - enable iteration over all operation types
  41  */
  42 static dma_cap_mask_t dma_cap_mask_all;
  43
  44 /**
  45  * chan_ref_percpu - tracks channel allocations per core/opertion
  46  */
  47 struct chan_ref_percpu {
  48         struct dma_chan_ref *ref;
  49 };
  50
  51 static int channel_table_initialized;
  52 static struct chan_ref_percpu *channel_table[DMA_TX_TYPE_END];
  53
  54 /**
  55  * async_tx_lock - protect modification of async_tx_master_list and serialize
  56  *      rebalance operations
  57  */
  58 static spinlock_t async_tx_lock;
  59
  60 static LIST_HEAD(async_tx_master_list);
  61
  62 /* async_tx_issue_pending_all - start all transactions on all channels */
  63 void async_tx_issue_pending_all(void)
  64 {
  65         struct dma_chan_ref *ref;
  66
  67         rcu_read_lock();
  68         list_for_each_entry_rcu(ref, &async_tx_master_list, node)
  69                 ref->chan->device->device_issue_pending(ref->chan);
  70         rcu_read_unlock();
  71 }
  72 EXPORT_SYMBOL_GPL(async_tx_issue_pending_all);
  73
  74 /* dma_wait_for_async_tx - spin wait for a transcation to complete
  75  * @tx: transaction to wait on
  76  */
  77 enum dma_status
  78 dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  79 {
  80         enum dma_status status;
  81         struct dma_async_tx_descriptor *iter;
  82         struct dma_async_tx_descriptor *parent;
  83
  84         if (!tx)
  85                 return DMA_SUCCESS;
  86
  87         /* poll through the dependency chain, return when tx is complete */
  88         do {
  89                 iter = tx;
  90
  91                 /* find the root of the unsubmitted dependency chain */
  92                 while (iter->cookie == -EBUSY) {
  93                         parent = iter->parent;
  94                         if (parent && parent->cookie == -EBUSY)
  95                                 iter = iter->parent;
  96                         else
  97                                 break;
  98                 }
  99
 100                 status = dma_sync_wait(iter->chan, iter->cookie);
 101         } while (status == DMA_IN_PROGRESS || (iter != tx));
 102
 103         return status;
 104 }
 105 EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
 106
 107 /* async_tx_run_dependencies - helper routine for dma drivers to process
 108  *      (start) dependent operations on their target channel
 109  * @tx: transaction with dependencies
 110  */
 111 void
 112 async_tx_run_dependencies(struct dma_async_tx_descriptor *tx)
 113 {
 114         struct dma_async_tx_descriptor *dep_tx, *_dep_tx;
 115         struct dma_device *dev;
 116         struct dma_chan *chan;
 117
 118         list_for_each_entry_safe(dep_tx, _dep_tx, &tx->depend_list,
 119                 depend_node) {
 120                 chan = dep_tx->chan;
 121                 dev = chan->device;
 122                 /* we can't depend on ourselves */
 123                 BUG_ON(chan == tx->chan);
 124                 list_del(&dep_tx->depend_node);
 125                 tx->tx_submit(dep_tx);
 126
 127                 /* we need to poke the engine as client code does not
 128                  * know about dependency submission events
 129                  */
 130                 dev->device_issue_pending(chan);
 131         }
 132 }
 133 EXPORT_SYMBOL_GPL(async_tx_run_dependencies);
 134
 135 static void
 136 free_dma_chan_ref(struct rcu_head *rcu)
 137 {
 138         struct dma_chan_ref *ref;
 139         ref = container_of(rcu, struct dma_chan_ref, rcu);
 140         kfree(ref);
 141 }
 142
 143 static void
 144 init_dma_chan_ref(struct dma_chan_ref *ref, struct dma_chan *chan)
 145 {
 146         INIT_LIST_HEAD(&ref->node);
 147         INIT_RCU_HEAD(&ref->rcu);
 148         ref->chan = chan;
 149         atomic_set(&ref->count, 0);
 150 }
 151
 152 /**
 153  * get_chan_ref_by_cap - returns the nth channel of the given capability
 154  *      defaults to returning the channel with the desired capability and the
 155  *      lowest reference count if the index can not be satisfied
 156  * @cap: capability to match
 157  * @index: nth channel desired, passing -1 has the effect of forcing the
 158  *  default return value
 159  */
 160 static struct dma_chan_ref *
 161 get_chan_ref_by_cap(enum dma_transaction_type cap, int index)
 162 {
 163         struct dma_chan_ref *ret_ref = NULL, *min_ref = NULL, *ref;
 164
 165         rcu_read_lock();
 166         list_for_each_entry_rcu(ref, &async_tx_master_list, node)
 167                 if (dma_has_cap(cap, ref->chan->device->cap_mask)) {
 168                         if (!min_ref)
 169                                 min_ref = ref;
 170                         else if (atomic_read(&ref->count) <
 171                                 atomic_read(&min_ref->count))
 172                                 min_ref = ref;
 173
 174                         if (index-- == 0) {
 175                                 ret_ref = ref;
 176                                 break;
 177                         }
 178                 }
 179         rcu_read_unlock();
 180
 181         if (!ret_ref)
 182                 ret_ref = min_ref;
 183
 184         if (ret_ref)
 185                 atomic_inc(&ret_ref->count);
 186
 187         return ret_ref;
 188 }
 189
 190 /**
 191  * async_tx_rebalance - redistribute the available channels, optimize
 192  * for cpu isolation in the SMP case, and opertaion isolation in the
 193  * uniprocessor case
 194  */
 195 static void async_tx_rebalance(void)
 196 {
 197         int cpu, cap, cpu_idx = 0;
 198         unsigned long flags;
 199
 200         if (!channel_table_initialized)
 201                 return;
 202
 203         spin_lock_irqsave(&async_tx_lock, flags);
 204
 205         /* undo the last distribution */
 206         for_each_dma_cap_mask(cap, dma_cap_mask_all)
 207                 for_each_possible_cpu(cpu) {
 208                         struct dma_chan_ref *ref =
 209                                 per_cpu_ptr(channel_table[cap], cpu)->ref;
 210                         if (ref) {
 211                                 atomic_set(&ref->count, 0);
 212                                 per_cpu_ptr(channel_table[cap], cpu)->ref =
 213                                                                         NULL;
 214                         }
 215                 }
 216
 217         for_each_dma_cap_mask(cap, dma_cap_mask_all)
 218                 for_each_online_cpu(cpu) {
 219                         struct dma_chan_ref *new;
 220                         if (NR_CPUS > 1)
 221                                 new = get_chan_ref_by_cap(cap, cpu_idx++);
 222                         else
 223                                 new = get_chan_ref_by_cap(cap, -1);
 224
 225                         per_cpu_ptr(channel_table[cap], cpu)->ref = new;
 226                 }
 227
 228         spin_unlock_irqrestore(&async_tx_lock, flags);
 229 }
 230
 231 static enum dma_state_client
 232 dma_channel_add_remove(struct dma_client *client,
 233         struct dma_chan *chan, enum dma_state state)
 234 {
 235         unsigned long found, flags;
 236         struct dma_chan_ref *master_ref, *ref;
 237         enum dma_state_client ack = DMA_DUP; /* default: take no action */
 238
 239         switch (state) {
 240         case DMA_RESOURCE_AVAILABLE:
 241                 found = 0;
 242                 rcu_read_lock();
 243                 list_for_each_entry_rcu(ref, &async_tx_master_list, node)
 244                         if (ref->chan == chan) {
 245                                 found = 1;
 246                                 break;
 247                         }
 248                 rcu_read_unlock();
 249
 250                 pr_debug("async_tx: dma resource available [%s]\n",
 251                         found ? "old" : "new");
 252
 253                 if (!found)
 254                         ack = DMA_ACK;
 255                 else
 256                         break;
 257
 258                 /* add the channel to the generic management list */
 259                 master_ref = kmalloc(sizeof(*master_ref), GFP_KERNEL);
 260                 if (master_ref) {
 261                         /* keep a reference until async_tx is unloaded */
 262                         dma_chan_get(chan);
 263                         init_dma_chan_ref(master_ref, chan);
 264                         spin_lock_irqsave(&async_tx_lock, flags);
 265                         list_add_tail_rcu(&master_ref->node,
 266                                 &async_tx_master_list);
 267                         spin_unlock_irqrestore(&async_tx_lock,
 268                                 flags);
 269                 } else {
 270                         printk(KERN_WARNING "async_tx: unable to create"
 271                                 " new master entry in response to"
 272                                 " a DMA_RESOURCE_ADDED event"
 273                                 " (-ENOMEM)\n");
 274                         return 0;
 275                 }
 276
 277                 async_tx_rebalance();
 278                 break;
 279         case DMA_RESOURCE_REMOVED:
 280                 found = 0;
 281                 spin_lock_irqsave(&async_tx_lock, flags);
 282                 list_for_each_entry_rcu(ref, &async_tx_master_list, node)
 283                         if (ref->chan == chan) {
 284                                 /* permit backing devices to go away */
 285                                 dma_chan_put(ref->chan);
 286                                 list_del_rcu(&ref->node);
 287                                 call_rcu(&ref->rcu, free_dma_chan_ref);
 288                                 found = 1;
 289                                 break;
 290                         }
 291                 spin_unlock_irqrestore(&async_tx_lock, flags);
 292
 293                 pr_debug("async_tx: dma resource removed [%s]\n",
 294                         found ? "ours" : "not ours");
 295
 296                 if (found)
 297                         ack = DMA_ACK;
 298                 else
 299                         break;
 300
 301                 async_tx_rebalance();
 302                 break;
 303         case DMA_RESOURCE_SUSPEND:
 304         case DMA_RESOURCE_RESUME:
 305                 printk(KERN_WARNING "async_tx: does not support dma channel"
 306                         " suspend/resume\n");
 307                 break;
 308         default:
 309                 BUG();
 310         }
 311
 312         return ack;
 313 }
 314
 315 static int __init
 316 async_tx_init(void)
 317 {
 318         enum dma_transaction_type cap;
 319
 320         spin_lock_init(&async_tx_lock);
 321         bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
 322
 323         /* an interrupt will never be an explicit operation type.
 324          * clearing this bit prevents allocation to a slot in 'channel_table'
 325          */
 326         clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
 327
 328         for_each_dma_cap_mask(cap, dma_cap_mask_all) {
 329                 channel_table[cap] = alloc_percpu(struct chan_ref_percpu);
 330                 if (!channel_table[cap])
 331                         goto err;
 332         }
 333
 334         channel_table_initialized = 1;
 335         dma_async_client_register(&async_tx_dma);
 336         dma_async_client_chan_request(&async_tx_dma);
 337
 338         printk(KERN_INFO "async_tx: api initialized (async)\n");
 339
 340         return 0;
 341 err:
 342         printk(KERN_ERR "async_tx: initialization failure\n");
 343
 344         while (--cap >= 0)
 345                 free_percpu(channel_table[cap]);
 346
 347         return 1;
 348 }
 349
 350 static void __exit async_tx_exit(void)
 351 {
 352         enum dma_transaction_type cap;
 353
 354         channel_table_initialized = 0;
 355
 356         for_each_dma_cap_mask(cap, dma_cap_mask_all)
 357                 if (channel_table[cap])
 358                         free_percpu(channel_table[cap]);
 359
 360         dma_async_client_unregister(&async_tx_dma);
 361 }
 362
 363 /**
 364  * __async_tx_find_channel - find a channel to carry out the operation or let
 365  *      the transaction execute synchronously
 366  * @depend_tx: transaction dependency
 367  * @tx_type: transaction type
 368  */
 369 struct dma_chan *
 370 __async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx,
 371         enum dma_transaction_type tx_type)
 372 {
 373         /* see if we can keep the chain on one channel */
 374         if (depend_tx &&
 375                 dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
 376                 return depend_tx->chan;
 377         else if (likely(channel_table_initialized)) {
 378                 struct dma_chan_ref *ref;
 379                 int cpu = get_cpu();
 380                 ref = per_cpu_ptr(channel_table[tx_type], cpu)->ref;
 381                 put_cpu();
 382                 return ref ? ref->chan : NULL;
 383         } else
 384                 return NULL;
 385 }
 386 EXPORT_SYMBOL_GPL(__async_tx_find_channel);
 387 #else
 388 static int __init async_tx_init(void)
 389 {
 390         printk(KERN_INFO "async_tx: api initialized (sync-only)\n");
 391         return 0;
 392 }
 393
 394 static void __exit async_tx_exit(void)
 395 {
 396         do { } while (0);
 397 }
 398 #endif
 399
 400 void
 401 async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
 402         enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx,
 403         dma_async_tx_callback cb_fn, void *cb_param)
 404 {
 405         tx->callback = cb_fn;
 406         tx->callback_param = cb_param;
 407
 408         /* set this new tx to run after depend_tx if:
 409          * 1/ a dependency exists (depend_tx is !NULL)
 410          * 2/ the tx can not be submitted to the current channel
 411          */
 412         if (depend_tx && depend_tx->chan != chan) {
 413                 /* if ack is already set then we cannot be sure
 414                  * we are referring to the correct operation
 415                  */
 416                 BUG_ON(depend_tx->ack);
 417
 418                 tx->parent = depend_tx;
 419                 spin_lock_bh(&depend_tx->lock);
 420                 list_add_tail(&tx->depend_node, &depend_tx->depend_list);
 421                 if (depend_tx->cookie == 0) {
 422                         struct dma_chan *dep_chan = depend_tx->chan;
 423                         struct dma_device *dep_dev = dep_chan->device;
 424                         dep_dev->device_dependency_added(dep_chan);
 425                 }
 426                 spin_unlock_bh(&depend_tx->lock);
 427
 428                 /* schedule an interrupt to trigger the channel switch */
 429                 async_trigger_callback(ASYNC_TX_ACK, depend_tx, NULL, NULL);
 430         } else {
 431                 tx->parent = NULL;
 432                 tx->tx_submit(tx);
 433         }
 434
 435         if (flags & ASYNC_TX_ACK)
 436                 async_tx_ack(tx);
 437
 438         if (depend_tx && (flags & ASYNC_TX_DEP_ACK))
 439                 async_tx_ack(depend_tx);
 440 }
 441 EXPORT_SYMBOL_GPL(async_tx_submit);
 442
 443 /**
 444  * async_trigger_callback - schedules the callback function to be run after
 445  * any dependent operations have been completed.
 446  * @flags: ASYNC_TX_ACK, ASYNC_TX_DEP_ACK
 447  * @depend_tx: 'callback' requires the completion of this transaction
 448  * @cb_fn: function to call after depend_tx completes
 449  * @cb_param: parameter to pass to the callback routine
 450  */
 451 struct dma_async_tx_descriptor *
 452 async_trigger_callback(enum async_tx_flags flags,
 453         struct dma_async_tx_descriptor *depend_tx,
 454         dma_async_tx_callback cb_fn, void *cb_param)
 455 {
 456         struct dma_chan *chan;
 457         struct dma_device *device;
 458         struct dma_async_tx_descriptor *tx;
 459
 460         if (depend_tx) {
 461                 chan = depend_tx->chan;
 462                 device = chan->device;
 463
 464                 /* see if we can schedule an interrupt
 465                  * otherwise poll for completion
 466                  */
 467                 if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
 468                         device = NULL;
 469
 470                 tx = device ? device->device_prep_dma_interrupt(chan) : NULL;
 471         } else
 472                 tx = NULL;
 473
 474         if (tx) {
 475                 pr_debug("%s: (async)\n", __func__);
 476
 477                 async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
 478         } else {
 479                 pr_debug("%s: (sync)\n", __func__);
 480
 481                 /* wait for any prerequisite operations */
 482                 if (depend_tx) {
 483                         /* if ack is already set then we cannot be sure
 484                          * we are referring to the correct operation
 485                          */
 486                         BUG_ON(depend_tx->ack);
 487                         if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR)
 488                                 panic("%s: DMA_ERROR waiting for depend_tx\n",
 489                                         __func__);
 490                 }
 491
 492                 async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
 493         }
 494
 495         return tx;
 496 }
 497 EXPORT_SYMBOL_GPL(async_trigger_callback);
 498
 499 module_init(async_tx_init);
 500 module_exit(async_tx_exit);
 501
 502 MODULE_AUTHOR("Intel Corporation");
 503 MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API");
 504 MODULE_LICENSE("GPL");