2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
34 * definitions for the ACPI scanning code
36 #define IVRS_HEADER_LENGTH 48
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
52 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
53 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
54 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
55 #define IVHD_FLAG_ISOC_EN_MASK 0x08
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70 * ACPI table definitions
72 * These data structures are laid over the table to parse the important values
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
90 } __attribute__((packed
));
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
101 } __attribute__((packed
));
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
116 } __attribute__((packed
));
120 static int __initdata amd_iommu_detected
;
122 u16 amd_iommu_last_bdf
; /* largest PCI device id we have
124 LIST_HEAD(amd_iommu_unity_map
); /* a list of required unity mappings
126 #ifdef CONFIG_IOMMU_STRESS
127 bool amd_iommu_isolate
= false;
129 bool amd_iommu_isolate
= true; /* if true, device isolation is
133 bool amd_iommu_unmap_flush
; /* if true, flush on every unmap */
135 LIST_HEAD(amd_iommu_list
); /* list of all AMD IOMMUs in the
139 * Pointer to the device table which is shared by all AMD IOMMUs
140 * it is indexed by the PCI device id or the HT unit id and contains
141 * information about the domain the device belongs to as well as the
142 * page table root pointer.
144 struct dev_table_entry
*amd_iommu_dev_table
;
147 * The alias table is a driver specific data structure which contains the
148 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
149 * More than one device can share the same requestor id.
151 u16
*amd_iommu_alias_table
;
154 * The rlookup table is used to find the IOMMU which is responsible
155 * for a specific device. It is also indexed by the PCI device id.
157 struct amd_iommu
**amd_iommu_rlookup_table
;
160 * The pd table (protection domain table) is used to find the protection domain
161 * data structure a device belongs to. Indexed with the PCI device id too.
163 struct protection_domain
**amd_iommu_pd_table
;
166 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
167 * to know which ones are already in use.
169 unsigned long *amd_iommu_pd_alloc_bitmap
;
171 static u32 dev_table_size
; /* size of the device table */
172 static u32 alias_table_size
; /* size of the alias table */
173 static u32 rlookup_table_size
; /* size if the rlookup table */
175 static inline void update_last_devid(u16 devid
)
177 if (devid
> amd_iommu_last_bdf
)
178 amd_iommu_last_bdf
= devid
;
181 static inline unsigned long tbl_size(int entry_size
)
183 unsigned shift
= PAGE_SHIFT
+
184 get_order(((int)amd_iommu_last_bdf
+ 1) * entry_size
);
189 /****************************************************************************
191 * AMD IOMMU MMIO register space handling functions
193 * These functions are used to program the IOMMU device registers in
194 * MMIO space required for that driver.
196 ****************************************************************************/
199 * This function set the exclusion range in the IOMMU. DMA accesses to the
200 * exclusion range are passed through untranslated
202 static void iommu_set_exclusion_range(struct amd_iommu
*iommu
)
204 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
205 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
208 if (!iommu
->exclusion_start
)
211 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
212 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
213 &entry
, sizeof(entry
));
216 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
217 &entry
, sizeof(entry
));
220 /* Programs the physical address of the device table into the IOMMU hardware */
221 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
225 BUG_ON(iommu
->mmio_base
== NULL
);
227 entry
= virt_to_phys(amd_iommu_dev_table
);
228 entry
|= (dev_table_size
>> 12) - 1;
229 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
230 &entry
, sizeof(entry
));
233 /* Generic functions to enable/disable certain features of the IOMMU. */
234 static void iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
238 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
240 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
243 static void __init
iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
247 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
249 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
252 /* Function to enable the hardware */
253 static void iommu_enable(struct amd_iommu
*iommu
)
255 printk(KERN_INFO
"AMD IOMMU: Enabling IOMMU at %s cap 0x%hx\n",
256 dev_name(&iommu
->dev
->dev
), iommu
->cap_ptr
);
258 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
261 static void iommu_disable(struct amd_iommu
*iommu
)
263 iommu_feature_disable(iommu
, CONTROL_IOMMU_EN
);
267 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
268 * the system has one.
270 static u8
* __init
iommu_map_mmio_space(u64 address
)
274 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu"))
277 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
281 release_mem_region(address
, MMIO_REGION_LENGTH
);
286 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
288 if (iommu
->mmio_base
)
289 iounmap(iommu
->mmio_base
);
290 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
293 /****************************************************************************
295 * The functions below belong to the first pass of AMD IOMMU ACPI table
296 * parsing. In this pass we try to find out the highest device id this
297 * code has to handle. Upon this information the size of the shared data
298 * structures is determined later.
300 ****************************************************************************/
303 * This function calculates the length of a given IVHD entry
305 static inline int ivhd_entry_length(u8
*ivhd
)
307 return 0x04 << (*ivhd
>> 6);
311 * This function reads the last device id the IOMMU has to handle from the PCI
312 * capability header for this IOMMU
314 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
318 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
319 update_last_devid(calc_devid(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
325 * After reading the highest device id from the IOMMU PCI capability header
326 * this function looks if there is a higher device id defined in the ACPI table
328 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
330 u8
*p
= (void *)h
, *end
= (void *)h
;
331 struct ivhd_entry
*dev
;
336 find_last_devid_on_pci(PCI_BUS(h
->devid
),
342 dev
= (struct ivhd_entry
*)p
;
344 case IVHD_DEV_SELECT
:
345 case IVHD_DEV_RANGE_END
:
347 case IVHD_DEV_EXT_SELECT
:
348 /* all the above subfield types refer to device ids */
349 update_last_devid(dev
->devid
);
354 p
+= ivhd_entry_length(p
);
363 * Iterate over all IVHD entries in the ACPI table and find the highest device
364 * id which we need to handle. This is the first of three functions which parse
365 * the ACPI table. So we check the checksum here.
367 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
370 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
371 struct ivhd_header
*h
;
374 * Validate checksum here so we don't need to do it when
375 * we actually parse the table
377 for (i
= 0; i
< table
->length
; ++i
)
380 /* ACPI table corrupt */
383 p
+= IVRS_HEADER_LENGTH
;
385 end
+= table
->length
;
387 h
= (struct ivhd_header
*)p
;
390 find_last_devid_from_ivhd(h
);
402 /****************************************************************************
404 * The following functions belong the the code path which parses the ACPI table
405 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
406 * data structures, initialize the device/alias/rlookup table and also
407 * basically initialize the hardware.
409 ****************************************************************************/
412 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
413 * write commands to that buffer later and the IOMMU will execute them
416 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
418 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
419 get_order(CMD_BUFFER_SIZE
));
424 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
;
430 * This function writes the command buffer address to the hardware and
433 static void iommu_enable_command_buffer(struct amd_iommu
*iommu
)
437 BUG_ON(iommu
->cmd_buf
== NULL
);
439 entry
= (u64
)virt_to_phys(iommu
->cmd_buf
);
440 entry
|= MMIO_CMD_SIZE_512
;
442 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
443 &entry
, sizeof(entry
));
445 /* set head and tail to zero manually */
446 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
447 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
449 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
452 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
454 free_pages((unsigned long)iommu
->cmd_buf
,
455 get_order(iommu
->cmd_buf_size
));
458 /* allocates the memory where the IOMMU will log its events to */
459 static u8
* __init
alloc_event_buffer(struct amd_iommu
*iommu
)
461 iommu
->evt_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
462 get_order(EVT_BUFFER_SIZE
));
464 if (iommu
->evt_buf
== NULL
)
467 return iommu
->evt_buf
;
470 static void iommu_enable_event_buffer(struct amd_iommu
*iommu
)
474 BUG_ON(iommu
->evt_buf
== NULL
);
476 entry
= (u64
)virt_to_phys(iommu
->evt_buf
) | EVT_LEN_MASK
;
478 memcpy_toio(iommu
->mmio_base
+ MMIO_EVT_BUF_OFFSET
,
479 &entry
, sizeof(entry
));
481 iommu_feature_enable(iommu
, CONTROL_EVT_LOG_EN
);
484 static void __init
free_event_buffer(struct amd_iommu
*iommu
)
486 free_pages((unsigned long)iommu
->evt_buf
, get_order(EVT_BUFFER_SIZE
));
489 /* sets a specific bit in the device table entry. */
490 static void set_dev_entry_bit(u16 devid
, u8 bit
)
492 int i
= (bit
>> 5) & 0x07;
493 int _bit
= bit
& 0x1f;
495 amd_iommu_dev_table
[devid
].data
[i
] |= (1 << _bit
);
498 /* Writes the specific IOMMU for a device into the rlookup table */
499 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
501 amd_iommu_rlookup_table
[devid
] = iommu
;
505 * This function takes the device specific flags read from the ACPI
506 * table and sets up the device table entry with that information
508 static void __init
set_dev_entry_from_acpi(struct amd_iommu
*iommu
,
509 u16 devid
, u32 flags
, u32 ext_flags
)
511 if (flags
& ACPI_DEVFLAG_INITPASS
)
512 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
513 if (flags
& ACPI_DEVFLAG_EXTINT
)
514 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
515 if (flags
& ACPI_DEVFLAG_NMI
)
516 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
517 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
518 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
519 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
520 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
521 if (flags
& ACPI_DEVFLAG_LINT0
)
522 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
523 if (flags
& ACPI_DEVFLAG_LINT1
)
524 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
526 set_iommu_for_device(iommu
, devid
);
530 * Reads the device exclusion range from ACPI and initialize IOMMU with
533 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
535 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
537 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
542 * We only can configure exclusion ranges per IOMMU, not
543 * per device. But we can enable the exclusion range per
544 * device. This is done here
546 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
547 iommu
->exclusion_start
= m
->range_start
;
548 iommu
->exclusion_length
= m
->range_length
;
553 * This function reads some important data from the IOMMU PCI space and
554 * initializes the driver data structure with it. It reads the hardware
555 * capabilities and the first/last device entries
557 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
559 int cap_ptr
= iommu
->cap_ptr
;
562 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_CAP_HDR_OFFSET
,
564 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_RANGE_OFFSET
,
566 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_MISC_OFFSET
,
569 iommu
->first_device
= calc_devid(MMIO_GET_BUS(range
),
571 iommu
->last_device
= calc_devid(MMIO_GET_BUS(range
),
573 iommu
->evt_msi_num
= MMIO_MSI_NUM(misc
);
577 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
578 * initializes the hardware and our data structures with it.
580 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
581 struct ivhd_header
*h
)
584 u8
*end
= p
, flags
= 0;
585 u16 dev_i
, devid
= 0, devid_start
= 0, devid_to
= 0;
588 struct ivhd_entry
*e
;
591 * First set the recommended feature enable bits from ACPI
592 * into the IOMMU control registers
594 h
->flags
& IVHD_FLAG_HT_TUN_EN_MASK
?
595 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
596 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
598 h
->flags
& IVHD_FLAG_PASSPW_EN_MASK
?
599 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
600 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
602 h
->flags
& IVHD_FLAG_RESPASSPW_EN_MASK
?
603 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
604 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
606 h
->flags
& IVHD_FLAG_ISOC_EN_MASK
?
607 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
608 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
611 * make IOMMU memory accesses cache coherent
613 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
616 * Done. Now parse the device entries
618 p
+= sizeof(struct ivhd_header
);
623 e
= (struct ivhd_entry
*)p
;
627 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
628 " last device %02x:%02x.%x flags: %02x\n",
629 PCI_BUS(iommu
->first_device
),
630 PCI_SLOT(iommu
->first_device
),
631 PCI_FUNC(iommu
->first_device
),
632 PCI_BUS(iommu
->last_device
),
633 PCI_SLOT(iommu
->last_device
),
634 PCI_FUNC(iommu
->last_device
),
637 for (dev_i
= iommu
->first_device
;
638 dev_i
<= iommu
->last_device
; ++dev_i
)
639 set_dev_entry_from_acpi(iommu
, dev_i
,
642 case IVHD_DEV_SELECT
:
644 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
652 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
654 case IVHD_DEV_SELECT_RANGE_START
:
656 DUMP_printk(" DEV_SELECT_RANGE_START\t "
657 "devid: %02x:%02x.%x flags: %02x\n",
663 devid_start
= e
->devid
;
670 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
671 "flags: %02x devid_to: %02x:%02x.%x\n",
676 PCI_BUS(e
->ext
>> 8),
677 PCI_SLOT(e
->ext
>> 8),
678 PCI_FUNC(e
->ext
>> 8));
681 devid_to
= e
->ext
>> 8;
682 set_dev_entry_from_acpi(iommu
, devid_to
, e
->flags
, 0);
683 amd_iommu_alias_table
[devid
] = devid_to
;
685 case IVHD_DEV_ALIAS_RANGE
:
687 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
688 "devid: %02x:%02x.%x flags: %02x "
689 "devid_to: %02x:%02x.%x\n",
694 PCI_BUS(e
->ext
>> 8),
695 PCI_SLOT(e
->ext
>> 8),
696 PCI_FUNC(e
->ext
>> 8));
698 devid_start
= e
->devid
;
700 devid_to
= e
->ext
>> 8;
704 case IVHD_DEV_EXT_SELECT
:
706 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
707 "flags: %02x ext: %08x\n",
714 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
,
717 case IVHD_DEV_EXT_SELECT_RANGE
:
719 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
720 "%02x:%02x.%x flags: %02x ext: %08x\n",
726 devid_start
= e
->devid
;
731 case IVHD_DEV_RANGE_END
:
733 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
739 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
741 amd_iommu_alias_table
[dev_i
] = devid_to
;
742 set_dev_entry_from_acpi(iommu
,
743 amd_iommu_alias_table
[dev_i
],
751 p
+= ivhd_entry_length(p
);
755 /* Initializes the device->iommu mapping for the driver */
756 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
760 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
761 set_iommu_for_device(iommu
, i
);
766 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
768 free_command_buffer(iommu
);
769 free_event_buffer(iommu
);
770 iommu_unmap_mmio_space(iommu
);
773 static void __init
free_iommu_all(void)
775 struct amd_iommu
*iommu
, *next
;
777 for_each_iommu_safe(iommu
, next
) {
778 list_del(&iommu
->list
);
779 free_iommu_one(iommu
);
785 * This function clues the initialization function for one IOMMU
786 * together and also allocates the command buffer and programs the
787 * hardware. It does NOT enable the IOMMU. This is done afterwards.
789 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
791 spin_lock_init(&iommu
->lock
);
792 list_add_tail(&iommu
->list
, &amd_iommu_list
);
795 * Copy data from ACPI table entry to the iommu struct
797 iommu
->dev
= pci_get_bus_and_slot(PCI_BUS(h
->devid
), h
->devid
& 0xff);
801 iommu
->cap_ptr
= h
->cap_ptr
;
802 iommu
->pci_seg
= h
->pci_seg
;
803 iommu
->mmio_phys
= h
->mmio_phys
;
804 iommu
->mmio_base
= iommu_map_mmio_space(h
->mmio_phys
);
805 if (!iommu
->mmio_base
)
808 iommu
->cmd_buf
= alloc_command_buffer(iommu
);
812 iommu
->evt_buf
= alloc_event_buffer(iommu
);
816 iommu
->int_enabled
= false;
818 init_iommu_from_pci(iommu
);
819 init_iommu_from_acpi(iommu
, h
);
820 init_iommu_devices(iommu
);
822 return pci_enable_device(iommu
->dev
);
826 * Iterates over all IOMMU entries in the ACPI table, allocates the
827 * IOMMU structure and initializes it with init_iommu_one()
829 static int __init
init_iommu_all(struct acpi_table_header
*table
)
831 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
832 struct ivhd_header
*h
;
833 struct amd_iommu
*iommu
;
836 end
+= table
->length
;
837 p
+= IVRS_HEADER_LENGTH
;
840 h
= (struct ivhd_header
*)p
;
844 DUMP_printk("IOMMU: device: %02x:%02x.%01x cap: %04x "
845 "seg: %d flags: %01x info %04x\n",
846 PCI_BUS(h
->devid
), PCI_SLOT(h
->devid
),
847 PCI_FUNC(h
->devid
), h
->cap_ptr
,
848 h
->pci_seg
, h
->flags
, h
->info
);
849 DUMP_printk(" mmio-addr: %016llx\n",
852 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
855 ret
= init_iommu_one(iommu
, h
);
870 /****************************************************************************
872 * The following functions initialize the MSI interrupts for all IOMMUs
873 * in the system. Its a bit challenging because there could be multiple
874 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
877 ****************************************************************************/
879 static int __init
iommu_setup_msi(struct amd_iommu
*iommu
)
883 if (pci_enable_msi(iommu
->dev
))
886 r
= request_irq(iommu
->dev
->irq
, amd_iommu_int_handler
,
892 pci_disable_msi(iommu
->dev
);
896 iommu
->int_enabled
= true;
897 iommu_feature_enable(iommu
, CONTROL_EVT_INT_EN
);
902 static int iommu_init_msi(struct amd_iommu
*iommu
)
904 if (iommu
->int_enabled
)
907 if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSI
))
908 return iommu_setup_msi(iommu
);
913 /****************************************************************************
915 * The next functions belong to the third pass of parsing the ACPI
916 * table. In this last pass the memory mapping requirements are
917 * gathered (like exclusion and unity mapping reanges).
919 ****************************************************************************/
921 static void __init
free_unity_maps(void)
923 struct unity_map_entry
*entry
, *next
;
925 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
926 list_del(&entry
->list
);
931 /* called when we find an exclusion range definition in ACPI */
932 static int __init
init_exclusion_range(struct ivmd_header
*m
)
938 set_device_exclusion_range(m
->devid
, m
);
940 case ACPI_IVMD_TYPE_ALL
:
941 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
942 set_device_exclusion_range(i
, m
);
944 case ACPI_IVMD_TYPE_RANGE
:
945 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
946 set_device_exclusion_range(i
, m
);
955 /* called for unity map ACPI definition */
956 static int __init
init_unity_map_range(struct ivmd_header
*m
)
958 struct unity_map_entry
*e
= 0;
961 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
970 s
= "IVMD_TYPEi\t\t\t";
971 e
->devid_start
= e
->devid_end
= m
->devid
;
973 case ACPI_IVMD_TYPE_ALL
:
974 s
= "IVMD_TYPE_ALL\t\t";
976 e
->devid_end
= amd_iommu_last_bdf
;
978 case ACPI_IVMD_TYPE_RANGE
:
979 s
= "IVMD_TYPE_RANGE\t\t";
980 e
->devid_start
= m
->devid
;
981 e
->devid_end
= m
->aux
;
984 e
->address_start
= PAGE_ALIGN(m
->range_start
);
985 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
986 e
->prot
= m
->flags
>> 1;
988 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
989 " range_start: %016llx range_end: %016llx flags: %x\n", s
,
990 PCI_BUS(e
->devid_start
), PCI_SLOT(e
->devid_start
),
991 PCI_FUNC(e
->devid_start
), PCI_BUS(e
->devid_end
),
992 PCI_SLOT(e
->devid_end
), PCI_FUNC(e
->devid_end
),
993 e
->address_start
, e
->address_end
, m
->flags
);
995 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
1000 /* iterates over all memory definitions we find in the ACPI table */
1001 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
1003 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
1004 struct ivmd_header
*m
;
1006 end
+= table
->length
;
1007 p
+= IVRS_HEADER_LENGTH
;
1010 m
= (struct ivmd_header
*)p
;
1011 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
1012 init_exclusion_range(m
);
1013 else if (m
->flags
& IVMD_FLAG_UNITY_MAP
)
1014 init_unity_map_range(m
);
1023 * Init the device table to not allow DMA access for devices and
1024 * suppress all page faults
1026 static void init_device_table(void)
1030 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
1031 set_dev_entry_bit(devid
, DEV_ENTRY_VALID
);
1032 set_dev_entry_bit(devid
, DEV_ENTRY_TRANSLATION
);
1037 * This function finally enables all IOMMUs found in the system after
1038 * they have been initialized
1040 static void enable_iommus(void)
1042 struct amd_iommu
*iommu
;
1044 for_each_iommu(iommu
) {
1045 iommu_set_device_table(iommu
);
1046 iommu_enable_command_buffer(iommu
);
1047 iommu_enable_event_buffer(iommu
);
1048 iommu_set_exclusion_range(iommu
);
1049 iommu_init_msi(iommu
);
1050 iommu_enable(iommu
);
1054 static void disable_iommus(void)
1056 struct amd_iommu
*iommu
;
1058 for_each_iommu(iommu
)
1059 iommu_disable(iommu
);
1063 * Suspend/Resume support
1064 * disable suspend until real resume implemented
1067 static int amd_iommu_resume(struct sys_device
*dev
)
1070 * Disable IOMMUs before reprogramming the hardware registers.
1071 * IOMMU is still enabled from the resume kernel.
1075 /* re-load the hardware */
1079 * we have to flush after the IOMMUs are enabled because a
1080 * disabled IOMMU will never execute the commands we send
1082 amd_iommu_flush_all_domains();
1083 amd_iommu_flush_all_devices();
1088 static int amd_iommu_suspend(struct sys_device
*dev
, pm_message_t state
)
1090 /* disable IOMMUs to go out of the way for BIOS */
1096 static struct sysdev_class amd_iommu_sysdev_class
= {
1097 .name
= "amd_iommu",
1098 .suspend
= amd_iommu_suspend
,
1099 .resume
= amd_iommu_resume
,
1102 static struct sys_device device_amd_iommu
= {
1104 .cls
= &amd_iommu_sysdev_class
,
1108 * This is the core init function for AMD IOMMU hardware in the system.
1109 * This function is called from the generic x86 DMA layer initialization
1112 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1115 * 1 pass) Find the highest PCI device id the driver has to handle.
1116 * Upon this information the size of the data structures is
1117 * determined that needs to be allocated.
1119 * 2 pass) Initialize the data structures just allocated with the
1120 * information in the ACPI table about available AMD IOMMUs
1121 * in the system. It also maps the PCI devices in the
1122 * system to specific IOMMUs
1124 * 3 pass) After the basic data structures are allocated and
1125 * initialized we update them with information about memory
1126 * remapping requirements parsed out of the ACPI table in
1129 * After that the hardware is initialized and ready to go. In the last
1130 * step we do some Linux specific things like registering the driver in
1131 * the dma_ops interface and initializing the suspend/resume support
1132 * functions. Finally it prints some information about AMD IOMMUs and
1133 * the driver state and enables the hardware.
1135 int __init
amd_iommu_init(void)
1141 printk(KERN_INFO
"AMD IOMMU disabled by kernel command line\n");
1145 if (!amd_iommu_detected
)
1149 * First parse ACPI tables to find the largest Bus/Dev/Func
1150 * we need to handle. Upon this information the shared data
1151 * structures for the IOMMUs in the system will be allocated
1153 if (acpi_table_parse("IVRS", find_last_devid_acpi
) != 0)
1156 dev_table_size
= tbl_size(DEV_TABLE_ENTRY_SIZE
);
1157 alias_table_size
= tbl_size(ALIAS_TABLE_ENTRY_SIZE
);
1158 rlookup_table_size
= tbl_size(RLOOKUP_TABLE_ENTRY_SIZE
);
1162 /* Device table - directly used by all IOMMUs */
1163 amd_iommu_dev_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1164 get_order(dev_table_size
));
1165 if (amd_iommu_dev_table
== NULL
)
1169 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1170 * IOMMU see for that device
1172 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
1173 get_order(alias_table_size
));
1174 if (amd_iommu_alias_table
== NULL
)
1177 /* IOMMU rlookup table - find the IOMMU for a specific device */
1178 amd_iommu_rlookup_table
= (void *)__get_free_pages(
1179 GFP_KERNEL
| __GFP_ZERO
,
1180 get_order(rlookup_table_size
));
1181 if (amd_iommu_rlookup_table
== NULL
)
1185 * Protection Domain table - maps devices to protection domains
1186 * This table has the same size as the rlookup_table
1188 amd_iommu_pd_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1189 get_order(rlookup_table_size
));
1190 if (amd_iommu_pd_table
== NULL
)
1193 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(
1194 GFP_KERNEL
| __GFP_ZERO
,
1195 get_order(MAX_DOMAIN_ID
/8));
1196 if (amd_iommu_pd_alloc_bitmap
== NULL
)
1199 /* init the device table */
1200 init_device_table();
1203 * let all alias entries point to itself
1205 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1206 amd_iommu_alias_table
[i
] = i
;
1209 * never allocate domain 0 because its used as the non-allocated and
1210 * error value placeholder
1212 amd_iommu_pd_alloc_bitmap
[0] = 1;
1215 * now the data structures are allocated and basically initialized
1216 * start the real acpi table scan
1219 if (acpi_table_parse("IVRS", init_iommu_all
) != 0)
1222 if (acpi_table_parse("IVRS", init_memory_definitions
) != 0)
1225 ret
= sysdev_class_register(&amd_iommu_sysdev_class
);
1229 ret
= sysdev_register(&device_amd_iommu
);
1233 ret
= amd_iommu_init_dma_ops();
1239 printk(KERN_INFO
"AMD IOMMU: device isolation ");
1240 if (amd_iommu_isolate
)
1241 printk("enabled\n");
1243 printk("disabled\n");
1245 if (amd_iommu_unmap_flush
)
1246 printk(KERN_INFO
"AMD IOMMU: IO/TLB flush on unmap enabled\n");
1248 printk(KERN_INFO
"AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1254 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
,
1255 get_order(MAX_DOMAIN_ID
/8));
1257 free_pages((unsigned long)amd_iommu_pd_table
,
1258 get_order(rlookup_table_size
));
1260 free_pages((unsigned long)amd_iommu_rlookup_table
,
1261 get_order(rlookup_table_size
));
1263 free_pages((unsigned long)amd_iommu_alias_table
,
1264 get_order(alias_table_size
));
1266 free_pages((unsigned long)amd_iommu_dev_table
,
1267 get_order(dev_table_size
));
1276 /****************************************************************************
1278 * Early detect code. This code runs at IOMMU detection time in the DMA
1279 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1282 ****************************************************************************/
1283 static int __init
early_amd_iommu_detect(struct acpi_table_header
*table
)
1288 void __init
amd_iommu_detect(void)
1290 if (swiotlb
|| no_iommu
|| (iommu_detected
&& !gart_iommu_aperture
))
1293 if (acpi_table_parse("IVRS", early_amd_iommu_detect
) == 0) {
1295 amd_iommu_detected
= 1;
1296 #ifdef CONFIG_GART_IOMMU
1297 gart_iommu_aperture_disabled
= 1;
1298 gart_iommu_aperture
= 0;
1303 /****************************************************************************
1305 * Parsing functions for the AMD IOMMU specific kernel command line
1308 ****************************************************************************/
1310 static int __init
parse_amd_iommu_dump(char *str
)
1312 amd_iommu_dump
= true;
1317 static int __init
parse_amd_iommu_options(char *str
)
1319 for (; *str
; ++str
) {
1320 if (strncmp(str
, "isolate", 7) == 0)
1321 amd_iommu_isolate
= true;
1322 if (strncmp(str
, "share", 5) == 0)
1323 amd_iommu_isolate
= false;
1324 if (strncmp(str
, "fullflush", 9) == 0)
1325 amd_iommu_unmap_flush
= true;
1331 __setup("amd_iommu_dump", parse_amd_iommu_dump
);
1332 __setup("amd_iommu=", parse_amd_iommu_options
);