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x86: move boot_cpu_physical_apicid to apic_32.c
[linux-2.6/mini2440.git] / drivers / ssb / main.c
blob8003a9e55ac461451ab3f412f9c58eab79efbae7
1 /*
2 * Sonics Silicon Backplane
3 * Subsystem core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include "ssb_private.h"
12
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include <linux/ssb/ssb.h>
16 #include <linux/ssb/ssb_regs.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/pci.h>
19
20 #include <pcmcia/cs_types.h>
21 #include <pcmcia/cs.h>
22 #include <pcmcia/cistpl.h>
23 #include <pcmcia/ds.h>
24
25
26 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
27 MODULE_LICENSE("GPL");
28
29
30 /* Temporary list of yet-to-be-attached buses */
31 static LIST_HEAD(attach_queue);
32 /* List if running buses */
33 static LIST_HEAD(buses);
34 /* Software ID counter */
35 static unsigned int next_busnumber;
36 /* buses_mutes locks the two buslists and the next_busnumber.
37 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
38 static DEFINE_MUTEX(buses_mutex);
39
40 /* There are differences in the codeflow, if the bus is
41 * initialized from early boot, as various needed services
42 * are not available early. This is a mechanism to delay
43 * these initializations to after early boot has finished.
44 * It's also used to avoid mutex locking, as that's not
45 * available and needed early. */
46 static bool ssb_is_early_boot = 1;
47
48 static void ssb_buses_lock(void);
49 static void ssb_buses_unlock(void);
50
51
52 #ifdef CONFIG_SSB_PCIHOST
53 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
54 {
55 struct ssb_bus *bus;
56
57 ssb_buses_lock();
58 list_for_each_entry(bus, &buses, list) {
59 if (bus->bustype == SSB_BUSTYPE_PCI &&
60 bus->host_pci == pdev)
61 goto found;
62 }
63 bus = NULL;
64 found:
65 ssb_buses_unlock();
66
67 return bus;
68 }
69 #endif /* CONFIG_SSB_PCIHOST */
70
71 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
72 {
73 if (dev)
74 get_device(dev->dev);
75 return dev;
76 }
77
78 static void ssb_device_put(struct ssb_device *dev)
79 {
80 if (dev)
81 put_device(dev->dev);
82 }
83
84 static int ssb_bus_resume(struct ssb_bus *bus)
85 {
86 int err;
87
88 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
89 err = ssb_pcmcia_init(bus);
90 if (err) {
91 /* No need to disable XTAL, as we don't have one on PCMCIA. */
92 return err;
93 }
94 ssb_chipco_resume(&bus->chipco);
95
96 return 0;
97 }
98
99 static int ssb_device_resume(struct device *dev)
100 {
101 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
102 struct ssb_driver *ssb_drv;
103 struct ssb_bus *bus;
104 int err = 0;
105
106 bus = ssb_dev->bus;
107 if (bus->suspend_cnt == bus->nr_devices) {
108 err = ssb_bus_resume(bus);
109 if (err)
110 return err;
111 }
112 bus->suspend_cnt--;
113 if (dev->driver) {
114 ssb_drv = drv_to_ssb_drv(dev->driver);
115 if (ssb_drv && ssb_drv->resume)
116 err = ssb_drv->resume(ssb_dev);
117 if (err)
118 goto out;
119 }
120 out:
121 return err;
122 }
123
124 static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state)
125 {
126 ssb_chipco_suspend(&bus->chipco, state);
127 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
128
129 /* Reset HW state information in memory, so that HW is
130 * completely reinitialized on resume. */
131 bus->mapped_device = NULL;
132 #ifdef CONFIG_SSB_DRIVER_PCICORE
133 bus->pcicore.setup_done = 0;
134 #endif
135 #ifdef CONFIG_SSB_DEBUG
136 bus->powered_up = 0;
137 #endif
138 }
139
140 static int ssb_device_suspend(struct device *dev, pm_message_t state)
141 {
142 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
143 struct ssb_driver *ssb_drv;
144 struct ssb_bus *bus;
145 int err = 0;
146
147 if (dev->driver) {
148 ssb_drv = drv_to_ssb_drv(dev->driver);
149 if (ssb_drv && ssb_drv->suspend)
150 err = ssb_drv->suspend(ssb_dev, state);
151 if (err)
152 goto out;
153 }
154
155 bus = ssb_dev->bus;
156 bus->suspend_cnt++;
157 if (bus->suspend_cnt == bus->nr_devices) {
158 /* All devices suspended. Shutdown the bus. */
159 ssb_bus_suspend(bus, state);
160 }
161
162 out:
163 return err;
164 }
165
166 #ifdef CONFIG_SSB_PCIHOST
167 int ssb_devices_freeze(struct ssb_bus *bus)
168 {
169 struct ssb_device *dev;
170 struct ssb_driver *drv;
171 int err = 0;
172 int i;
173 pm_message_t state = PMSG_FREEZE;
174
175 /* First check that we are capable to freeze all devices. */
176 for (i = 0; i < bus->nr_devices; i++) {
177 dev = &(bus->devices[i]);
178 if (!dev->dev ||
179 !dev->dev->driver ||
180 !device_is_registered(dev->dev))
181 continue;
182 drv = drv_to_ssb_drv(dev->dev->driver);
183 if (!drv)
184 continue;
185 if (!drv->suspend) {
186 /* Nope, can't suspend this one. */
187 return -EOPNOTSUPP;
188 }
189 }
190 /* Now suspend all devices */
191 for (i = 0; i < bus->nr_devices; i++) {
192 dev = &(bus->devices[i]);
193 if (!dev->dev ||
194 !dev->dev->driver ||
195 !device_is_registered(dev->dev))
196 continue;
197 drv = drv_to_ssb_drv(dev->dev->driver);
198 if (!drv)
199 continue;
200 err = drv->suspend(dev, state);
201 if (err) {
202 ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
203 dev->dev->bus_id);
204 goto err_unwind;
205 }
206 }
207
208 return 0;
209 err_unwind:
210 for (i--; i >= 0; i--) {
211 dev = &(bus->devices[i]);
212 if (!dev->dev ||
213 !dev->dev->driver ||
214 !device_is_registered(dev->dev))
215 continue;
216 drv = drv_to_ssb_drv(dev->dev->driver);
217 if (!drv)
218 continue;
219 if (drv->resume)
220 drv->resume(dev);
221 }
222 return err;
223 }
224
225 int ssb_devices_thaw(struct ssb_bus *bus)
226 {
227 struct ssb_device *dev;
228 struct ssb_driver *drv;
229 int err;
230 int i;
231
232 for (i = 0; i < bus->nr_devices; i++) {
233 dev = &(bus->devices[i]);
234 if (!dev->dev ||
235 !dev->dev->driver ||
236 !device_is_registered(dev->dev))
237 continue;
238 drv = drv_to_ssb_drv(dev->dev->driver);
239 if (!drv)
240 continue;
241 if (SSB_WARN_ON(!drv->resume))
242 continue;
243 err = drv->resume(dev);
244 if (err) {
245 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
246 dev->dev->bus_id);
247 }
248 }
249
250 return 0;
251 }
252 #endif /* CONFIG_SSB_PCIHOST */
253
254 static void ssb_device_shutdown(struct device *dev)
255 {
256 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
257 struct ssb_driver *ssb_drv;
258
259 if (!dev->driver)
260 return;
261 ssb_drv = drv_to_ssb_drv(dev->driver);
262 if (ssb_drv && ssb_drv->shutdown)
263 ssb_drv->shutdown(ssb_dev);
264 }
265
266 static int ssb_device_remove(struct device *dev)
267 {
268 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
269 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
270
271 if (ssb_drv && ssb_drv->remove)
272 ssb_drv->remove(ssb_dev);
273 ssb_device_put(ssb_dev);
274
275 return 0;
276 }
277
278 static int ssb_device_probe(struct device *dev)
279 {
280 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
281 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
282 int err = 0;
283
284 ssb_device_get(ssb_dev);
285 if (ssb_drv && ssb_drv->probe)
286 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
287 if (err)
288 ssb_device_put(ssb_dev);
289
290 return err;
291 }
292
293 static int ssb_match_devid(const struct ssb_device_id *tabid,
294 const struct ssb_device_id *devid)
295 {
296 if ((tabid->vendor != devid->vendor) &&
297 tabid->vendor != SSB_ANY_VENDOR)
298 return 0;
299 if ((tabid->coreid != devid->coreid) &&
300 tabid->coreid != SSB_ANY_ID)
301 return 0;
302 if ((tabid->revision != devid->revision) &&
303 tabid->revision != SSB_ANY_REV)
304 return 0;
305 return 1;
306 }
307
308 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
309 {
310 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
311 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
312 const struct ssb_device_id *id;
313
314 for (id = ssb_drv->id_table;
315 id->vendor || id->coreid || id->revision;
316 id++) {
317 if (ssb_match_devid(id, &ssb_dev->id))
318 return 1; /* found */
319 }
320
321 return 0;
322 }
323
324 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
325 {
326 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
327
328 if (!dev)
329 return -ENODEV;
330
331 return add_uevent_var(env,
332 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
333 ssb_dev->id.vendor, ssb_dev->id.coreid,
334 ssb_dev->id.revision);
335 }
336
337 static struct bus_type ssb_bustype = {
338 .name = "ssb",
339 .match = ssb_bus_match,
340 .probe = ssb_device_probe,
341 .remove = ssb_device_remove,
342 .shutdown = ssb_device_shutdown,
343 .suspend = ssb_device_suspend,
344 .resume = ssb_device_resume,
345 .uevent = ssb_device_uevent,
346 };
347
348 static void ssb_buses_lock(void)
349 {
350 /* See the comment at the ssb_is_early_boot definition */
351 if (!ssb_is_early_boot)
352 mutex_lock(&buses_mutex);
353 }
354
355 static void ssb_buses_unlock(void)
356 {
357 /* See the comment at the ssb_is_early_boot definition */
358 if (!ssb_is_early_boot)
359 mutex_unlock(&buses_mutex);
360 }
361
362 static void ssb_devices_unregister(struct ssb_bus *bus)
363 {
364 struct ssb_device *sdev;
365 int i;
366
367 for (i = bus->nr_devices - 1; i >= 0; i--) {
368 sdev = &(bus->devices[i]);
369 if (sdev->dev)
370 device_unregister(sdev->dev);
371 }
372 }
373
374 void ssb_bus_unregister(struct ssb_bus *bus)
375 {
376 ssb_buses_lock();
377 ssb_devices_unregister(bus);
378 list_del(&bus->list);
379 ssb_buses_unlock();
380
381 /* ssb_pcmcia_exit(bus); */
382 ssb_pci_exit(bus);
383 ssb_iounmap(bus);
384 }
385 EXPORT_SYMBOL(ssb_bus_unregister);
386
387 static void ssb_release_dev(struct device *dev)
388 {
389 struct __ssb_dev_wrapper *devwrap;
390
391 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
392 kfree(devwrap);
393 }
394
395 static int ssb_devices_register(struct ssb_bus *bus)
396 {
397 struct ssb_device *sdev;
398 struct device *dev;
399 struct __ssb_dev_wrapper *devwrap;
400 int i, err = 0;
401 int dev_idx = 0;
402
403 for (i = 0; i < bus->nr_devices; i++) {
404 sdev = &(bus->devices[i]);
405
406 /* We don't register SSB-system devices to the kernel,
407 * as the drivers for them are built into SSB. */
408 switch (sdev->id.coreid) {
409 case SSB_DEV_CHIPCOMMON:
410 case SSB_DEV_PCI:
411 case SSB_DEV_PCIE:
412 case SSB_DEV_PCMCIA:
413 case SSB_DEV_MIPS:
414 case SSB_DEV_MIPS_3302:
415 case SSB_DEV_EXTIF:
416 continue;
417 }
418
419 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
420 if (!devwrap) {
421 ssb_printk(KERN_ERR PFX
422 "Could not allocate device\n");
423 err = -ENOMEM;
424 goto error;
425 }
426 dev = &devwrap->dev;
427 devwrap->sdev = sdev;
428
429 dev->release = ssb_release_dev;
430 dev->bus = &ssb_bustype;
431 snprintf(dev->bus_id, sizeof(dev->bus_id),
432 "ssb%u:%d", bus->busnumber, dev_idx);
433
434 switch (bus->bustype) {
435 case SSB_BUSTYPE_PCI:
436 #ifdef CONFIG_SSB_PCIHOST
437 sdev->irq = bus->host_pci->irq;
438 dev->parent = &bus->host_pci->dev;
439 sdev->dma_dev = &bus->host_pci->dev;
440 #endif
441 break;
442 case SSB_BUSTYPE_PCMCIA:
443 #ifdef CONFIG_SSB_PCMCIAHOST
444 sdev->irq = bus->host_pcmcia->irq.AssignedIRQ;
445 dev->parent = &bus->host_pcmcia->dev;
446 sdev->dma_dev = &bus->host_pcmcia->dev;
447 #endif
448 break;
449 case SSB_BUSTYPE_SSB:
450 sdev->dma_dev = dev;
451 break;
452 }
453
454 sdev->dev = dev;
455 err = device_register(dev);
456 if (err) {
457 ssb_printk(KERN_ERR PFX
458 "Could not register %s\n",
459 dev->bus_id);
460 /* Set dev to NULL to not unregister
461 * dev on error unwinding. */
462 sdev->dev = NULL;
463 kfree(devwrap);
464 goto error;
465 }
466 dev_idx++;
467 }
468
469 return 0;
470 error:
471 /* Unwind the already registered devices. */
472 ssb_devices_unregister(bus);
473 return err;
474 }
475
476 /* Needs ssb_buses_lock() */
477 static int ssb_attach_queued_buses(void)
478 {
479 struct ssb_bus *bus, *n;
480 int err = 0;
481 int drop_them_all = 0;
482
483 list_for_each_entry_safe(bus, n, &attach_queue, list) {
484 if (drop_them_all) {
485 list_del(&bus->list);
486 continue;
487 }
488 /* Can't init the PCIcore in ssb_bus_register(), as that
489 * is too early in boot for embedded systems
490 * (no udelay() available). So do it here in attach stage.
491 */
492 err = ssb_bus_powerup(bus, 0);
493 if (err)
494 goto error;
495 ssb_pcicore_init(&bus->pcicore);
496 ssb_bus_may_powerdown(bus);
497
498 err = ssb_devices_register(bus);
499 error:
500 if (err) {
501 drop_them_all = 1;
502 list_del(&bus->list);
503 continue;
504 }
505 list_move_tail(&bus->list, &buses);
506 }
507
508 return err;
509 }
510
511 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
512 {
513 struct ssb_bus *bus = dev->bus;
514
515 offset += dev->core_index * SSB_CORE_SIZE;
516 return readw(bus->mmio + offset);
517 }
518
519 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
520 {
521 struct ssb_bus *bus = dev->bus;
522
523 offset += dev->core_index * SSB_CORE_SIZE;
524 return readl(bus->mmio + offset);
525 }
526
527 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
528 {
529 struct ssb_bus *bus = dev->bus;
530
531 offset += dev->core_index * SSB_CORE_SIZE;
532 writew(value, bus->mmio + offset);
533 }
534
535 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
536 {
537 struct ssb_bus *bus = dev->bus;
538
539 offset += dev->core_index * SSB_CORE_SIZE;
540 writel(value, bus->mmio + offset);
541 }
542
543 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
544 static const struct ssb_bus_ops ssb_ssb_ops = {
545 .read16 = ssb_ssb_read16,
546 .read32 = ssb_ssb_read32,
547 .write16 = ssb_ssb_write16,
548 .write32 = ssb_ssb_write32,
549 };
550
551 static int ssb_fetch_invariants(struct ssb_bus *bus,
552 ssb_invariants_func_t get_invariants)
553 {
554 struct ssb_init_invariants iv;
555 int err;
556
557 memset(&iv, 0, sizeof(iv));
558 err = get_invariants(bus, &iv);
559 if (err)
560 goto out;
561 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
562 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
563 bus->has_cardbus_slot = iv.has_cardbus_slot;
564 out:
565 return err;
566 }
567
568 static int ssb_bus_register(struct ssb_bus *bus,
569 ssb_invariants_func_t get_invariants,
570 unsigned long baseaddr)
571 {
572 int err;
573
574 spin_lock_init(&bus->bar_lock);
575 INIT_LIST_HEAD(&bus->list);
576 #ifdef CONFIG_SSB_EMBEDDED
577 spin_lock_init(&bus->gpio_lock);
578 #endif
579
580 /* Powerup the bus */
581 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
582 if (err)
583 goto out;
584 ssb_buses_lock();
585 bus->busnumber = next_busnumber;
586 /* Scan for devices (cores) */
587 err = ssb_bus_scan(bus, baseaddr);
588 if (err)
589 goto err_disable_xtal;
590
591 /* Init PCI-host device (if any) */
592 err = ssb_pci_init(bus);
593 if (err)
594 goto err_unmap;
595 /* Init PCMCIA-host device (if any) */
596 err = ssb_pcmcia_init(bus);
597 if (err)
598 goto err_pci_exit;
599
600 /* Initialize basic system devices (if available) */
601 err = ssb_bus_powerup(bus, 0);
602 if (err)
603 goto err_pcmcia_exit;
604 ssb_chipcommon_init(&bus->chipco);
605 ssb_mipscore_init(&bus->mipscore);
606 err = ssb_fetch_invariants(bus, get_invariants);
607 if (err) {
608 ssb_bus_may_powerdown(bus);
609 goto err_pcmcia_exit;
610 }
611 ssb_bus_may_powerdown(bus);
612
613 /* Queue it for attach.
614 * See the comment at the ssb_is_early_boot definition. */
615 list_add_tail(&bus->list, &attach_queue);
616 if (!ssb_is_early_boot) {
617 /* This is not early boot, so we must attach the bus now */
618 err = ssb_attach_queued_buses();
619 if (err)
620 goto err_dequeue;
621 }
622 next_busnumber++;
623 ssb_buses_unlock();
624
625 out:
626 return err;
627
628 err_dequeue:
629 list_del(&bus->list);
630 err_pcmcia_exit:
631 /* ssb_pcmcia_exit(bus); */
632 err_pci_exit:
633 ssb_pci_exit(bus);
634 err_unmap:
635 ssb_iounmap(bus);
636 err_disable_xtal:
637 ssb_buses_unlock();
638 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
639 return err;
640 }
641
642 #ifdef CONFIG_SSB_PCIHOST
643 int ssb_bus_pcibus_register(struct ssb_bus *bus,
644 struct pci_dev *host_pci)
645 {
646 int err;
647
648 bus->bustype = SSB_BUSTYPE_PCI;
649 bus->host_pci = host_pci;
650 bus->ops = &ssb_pci_ops;
651
652 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
653 if (!err) {
654 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
655 "PCI device %s\n", host_pci->dev.bus_id);
656 }
657
658 return err;
659 }
660 EXPORT_SYMBOL(ssb_bus_pcibus_register);
661 #endif /* CONFIG_SSB_PCIHOST */
662
663 #ifdef CONFIG_SSB_PCMCIAHOST
664 int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
665 struct pcmcia_device *pcmcia_dev,
666 unsigned long baseaddr)
667 {
668 int err;
669
670 bus->bustype = SSB_BUSTYPE_PCMCIA;
671 bus->host_pcmcia = pcmcia_dev;
672 bus->ops = &ssb_pcmcia_ops;
673
674 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
675 if (!err) {
676 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
677 "PCMCIA device %s\n", pcmcia_dev->devname);
678 }
679
680 return err;
681 }
682 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
683 #endif /* CONFIG_SSB_PCMCIAHOST */
684
685 int ssb_bus_ssbbus_register(struct ssb_bus *bus,
686 unsigned long baseaddr,
687 ssb_invariants_func_t get_invariants)
688 {
689 int err;
690
691 bus->bustype = SSB_BUSTYPE_SSB;
692 bus->ops = &ssb_ssb_ops;
693
694 err = ssb_bus_register(bus, get_invariants, baseaddr);
695 if (!err) {
696 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
697 "address 0x%08lX\n", baseaddr);
698 }
699
700 return err;
701 }
702
703 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
704 {
705 drv->drv.name = drv->name;
706 drv->drv.bus = &ssb_bustype;
707 drv->drv.owner = owner;
708
709 return driver_register(&drv->drv);
710 }
711 EXPORT_SYMBOL(__ssb_driver_register);
712
713 void ssb_driver_unregister(struct ssb_driver *drv)
714 {
715 driver_unregister(&drv->drv);
716 }
717 EXPORT_SYMBOL(ssb_driver_unregister);
718
719 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
720 {
721 struct ssb_bus *bus = dev->bus;
722 struct ssb_device *ent;
723 int i;
724
725 for (i = 0; i < bus->nr_devices; i++) {
726 ent = &(bus->devices[i]);
727 if (ent->id.vendor != dev->id.vendor)
728 continue;
729 if (ent->id.coreid != dev->id.coreid)
730 continue;
731
732 ent->devtypedata = data;
733 }
734 }
735 EXPORT_SYMBOL(ssb_set_devtypedata);
736
737 static u32 clkfactor_f6_resolve(u32 v)
738 {
739 /* map the magic values */
740 switch (v) {
741 case SSB_CHIPCO_CLK_F6_2:
742 return 2;
743 case SSB_CHIPCO_CLK_F6_3:
744 return 3;
745 case SSB_CHIPCO_CLK_F6_4:
746 return 4;
747 case SSB_CHIPCO_CLK_F6_5:
748 return 5;
749 case SSB_CHIPCO_CLK_F6_6:
750 return 6;
751 case SSB_CHIPCO_CLK_F6_7:
752 return 7;
753 }
754 return 0;
755 }
756
757 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
758 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
759 {
760 u32 n1, n2, clock, m1, m2, m3, mc;
761
762 n1 = (n & SSB_CHIPCO_CLK_N1);
763 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
764
765 switch (plltype) {
766 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
767 if (m & SSB_CHIPCO_CLK_T6_MMASK)
768 return SSB_CHIPCO_CLK_T6_M0;
769 return SSB_CHIPCO_CLK_T6_M1;
770 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
771 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
772 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
773 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
774 n1 = clkfactor_f6_resolve(n1);
775 n2 += SSB_CHIPCO_CLK_F5_BIAS;
776 break;
777 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
778 n1 += SSB_CHIPCO_CLK_T2_BIAS;
779 n2 += SSB_CHIPCO_CLK_T2_BIAS;
780 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
781 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
782 break;
783 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
784 return 100000000;
785 default:
786 SSB_WARN_ON(1);
787 }
788
789 switch (plltype) {
790 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
791 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
792 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
793 break;
794 default:
795 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
796 }
797 if (!clock)
798 return 0;
799
800 m1 = (m & SSB_CHIPCO_CLK_M1);
801 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
802 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
803 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
804
805 switch (plltype) {
806 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
807 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
808 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
809 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
810 m1 = clkfactor_f6_resolve(m1);
811 if ((plltype == SSB_PLLTYPE_1) ||
812 (plltype == SSB_PLLTYPE_3))
813 m2 += SSB_CHIPCO_CLK_F5_BIAS;
814 else
815 m2 = clkfactor_f6_resolve(m2);
816 m3 = clkfactor_f6_resolve(m3);
817
818 switch (mc) {
819 case SSB_CHIPCO_CLK_MC_BYPASS:
820 return clock;
821 case SSB_CHIPCO_CLK_MC_M1:
822 return (clock / m1);
823 case SSB_CHIPCO_CLK_MC_M1M2:
824 return (clock / (m1 * m2));
825 case SSB_CHIPCO_CLK_MC_M1M2M3:
826 return (clock / (m1 * m2 * m3));
827 case SSB_CHIPCO_CLK_MC_M1M3:
828 return (clock / (m1 * m3));
829 }
830 return 0;
831 case SSB_PLLTYPE_2:
832 m1 += SSB_CHIPCO_CLK_T2_BIAS;
833 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
834 m3 += SSB_CHIPCO_CLK_T2_BIAS;
835 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
836 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
837 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
838
839 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
840 clock /= m1;
841 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
842 clock /= m2;
843 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
844 clock /= m3;
845 return clock;
846 default:
847 SSB_WARN_ON(1);
848 }
849 return 0;
850 }
851
852 /* Get the current speed the backplane is running at */
853 u32 ssb_clockspeed(struct ssb_bus *bus)
854 {
855 u32 rate;
856 u32 plltype;
857 u32 clkctl_n, clkctl_m;
858
859 if (ssb_extif_available(&bus->extif))
860 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
861 &clkctl_n, &clkctl_m);
862 else if (bus->chipco.dev)
863 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
864 &clkctl_n, &clkctl_m);
865 else
866 return 0;
867
868 if (bus->chip_id == 0x5365) {
869 rate = 100000000;
870 } else {
871 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
872 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
873 rate /= 2;
874 }
875
876 return rate;
877 }
878 EXPORT_SYMBOL(ssb_clockspeed);
879
880 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
881 {
882 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
883
884 /* The REJECT bit changed position in TMSLOW between
885 * Backplane revisions. */
886 switch (rev) {
887 case SSB_IDLOW_SSBREV_22:
888 return SSB_TMSLOW_REJECT_22;
889 case SSB_IDLOW_SSBREV_23:
890 return SSB_TMSLOW_REJECT_23;
891 case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
892 case SSB_IDLOW_SSBREV_25: /* same here */
893 case SSB_IDLOW_SSBREV_26: /* same here */
894 case SSB_IDLOW_SSBREV_27: /* same here */
895 return SSB_TMSLOW_REJECT_23; /* this is a guess */
896 default:
897 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
898 WARN_ON(1);
899 }
900 return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
901 }
902
903 int ssb_device_is_enabled(struct ssb_device *dev)
904 {
905 u32 val;
906 u32 reject;
907
908 reject = ssb_tmslow_reject_bitmask(dev);
909 val = ssb_read32(dev, SSB_TMSLOW);
910 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
911
912 return (val == SSB_TMSLOW_CLOCK);
913 }
914 EXPORT_SYMBOL(ssb_device_is_enabled);
915
916 static void ssb_flush_tmslow(struct ssb_device *dev)
917 {
918 /* Make _really_ sure the device has finished the TMSLOW
919 * register write transaction, as we risk running into
920 * a machine check exception otherwise.
921 * Do this by reading the register back to commit the
922 * PCI write and delay an additional usec for the device
923 * to react to the change. */
924 ssb_read32(dev, SSB_TMSLOW);
925 udelay(1);
926 }
927
928 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
929 {
930 u32 val;
931
932 ssb_device_disable(dev, core_specific_flags);
933 ssb_write32(dev, SSB_TMSLOW,
934 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
935 SSB_TMSLOW_FGC | core_specific_flags);
936 ssb_flush_tmslow(dev);
937
938 /* Clear SERR if set. This is a hw bug workaround. */
939 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
940 ssb_write32(dev, SSB_TMSHIGH, 0);
941
942 val = ssb_read32(dev, SSB_IMSTATE);
943 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
944 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
945 ssb_write32(dev, SSB_IMSTATE, val);
946 }
947
948 ssb_write32(dev, SSB_TMSLOW,
949 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
950 core_specific_flags);
951 ssb_flush_tmslow(dev);
952
953 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
954 core_specific_flags);
955 ssb_flush_tmslow(dev);
956 }
957 EXPORT_SYMBOL(ssb_device_enable);
958
959 /* Wait for a bit in a register to get set or unset.
960 * timeout is in units of ten-microseconds */
961 static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
962 int timeout, int set)
963 {
964 int i;
965 u32 val;
966
967 for (i = 0; i < timeout; i++) {
968 val = ssb_read32(dev, reg);
969 if (set) {
970 if (val & bitmask)
971 return 0;
972 } else {
973 if (!(val & bitmask))
974 return 0;
975 }
976 udelay(10);
977 }
978 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
979 "register %04X to %s.\n",
980 bitmask, reg, (set ? "set" : "clear"));
981
982 return -ETIMEDOUT;
983 }
984
985 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
986 {
987 u32 reject;
988
989 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
990 return;
991
992 reject = ssb_tmslow_reject_bitmask(dev);
993 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
994 ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
995 ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
996 ssb_write32(dev, SSB_TMSLOW,
997 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
998 reject | SSB_TMSLOW_RESET |
999 core_specific_flags);
1000 ssb_flush_tmslow(dev);
1001
1002 ssb_write32(dev, SSB_TMSLOW,
1003 reject | SSB_TMSLOW_RESET |
1004 core_specific_flags);
1005 ssb_flush_tmslow(dev);
1006 }
1007 EXPORT_SYMBOL(ssb_device_disable);
1008
1009 u32 ssb_dma_translation(struct ssb_device *dev)
1010 {
1011 switch (dev->bus->bustype) {
1012 case SSB_BUSTYPE_SSB:
1013 return 0;
1014 case SSB_BUSTYPE_PCI:
1015 case SSB_BUSTYPE_PCMCIA:
1016 return SSB_PCI_DMA;
1017 }
1018 return 0;
1019 }
1020 EXPORT_SYMBOL(ssb_dma_translation);
1021
1022 int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
1023 {
1024 struct device *dma_dev = ssb_dev->dma_dev;
1025
1026 #ifdef CONFIG_SSB_PCIHOST
1027 if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI)
1028 return dma_set_mask(dma_dev, mask);
1029 #endif
1030 dma_dev->coherent_dma_mask = mask;
1031 dma_dev->dma_mask = &dma_dev->coherent_dma_mask;
1032
1033 return 0;
1034 }
1035 EXPORT_SYMBOL(ssb_dma_set_mask);
1036
1037 int ssb_bus_may_powerdown(struct ssb_bus *bus)
1038 {
1039 struct ssb_chipcommon *cc;
1040 int err = 0;
1041
1042 /* On buses where more than one core may be working
1043 * at a time, we must not powerdown stuff if there are
1044 * still cores that may want to run. */
1045 if (bus->bustype == SSB_BUSTYPE_SSB)
1046 goto out;
1047
1048 cc = &bus->chipco;
1049
1050 if (!cc->dev)
1051 goto out;
1052 if (cc->dev->id.revision < 5)
1053 goto out;
1054
1055 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1056 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1057 if (err)
1058 goto error;
1059 out:
1060 #ifdef CONFIG_SSB_DEBUG
1061 bus->powered_up = 0;
1062 #endif
1063 return err;
1064 error:
1065 ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1066 goto out;
1067 }
1068 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1069
1070 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1071 {
1072 struct ssb_chipcommon *cc;
1073 int err;
1074 enum ssb_clkmode mode;
1075
1076 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1077 if (err)
1078 goto error;
1079 cc = &bus->chipco;
1080 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1081 ssb_chipco_set_clockmode(cc, mode);
1082
1083 #ifdef CONFIG_SSB_DEBUG
1084 bus->powered_up = 1;
1085 #endif
1086 return 0;
1087 error:
1088 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1089 return err;
1090 }
1091 EXPORT_SYMBOL(ssb_bus_powerup);
1092
1093 u32 ssb_admatch_base(u32 adm)
1094 {
1095 u32 base = 0;
1096
1097 switch (adm & SSB_ADM_TYPE) {
1098 case SSB_ADM_TYPE0:
1099 base = (adm & SSB_ADM_BASE0);
1100 break;
1101 case SSB_ADM_TYPE1:
1102 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1103 base = (adm & SSB_ADM_BASE1);
1104 break;
1105 case SSB_ADM_TYPE2:
1106 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1107 base = (adm & SSB_ADM_BASE2);
1108 break;
1109 default:
1110 SSB_WARN_ON(1);
1111 }
1112
1113 return base;
1114 }
1115 EXPORT_SYMBOL(ssb_admatch_base);
1116
1117 u32 ssb_admatch_size(u32 adm)
1118 {
1119 u32 size = 0;
1120
1121 switch (adm & SSB_ADM_TYPE) {
1122 case SSB_ADM_TYPE0:
1123 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1124 break;
1125 case SSB_ADM_TYPE1:
1126 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1127 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1128 break;
1129 case SSB_ADM_TYPE2:
1130 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1131 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1132 break;
1133 default:
1134 SSB_WARN_ON(1);
1135 }
1136 size = (1 << (size + 1));
1137
1138 return size;
1139 }
1140 EXPORT_SYMBOL(ssb_admatch_size);
1141
1142 static int __init ssb_modinit(void)
1143 {
1144 int err;
1145
1146 /* See the comment at the ssb_is_early_boot definition */
1147 ssb_is_early_boot = 0;
1148 err = bus_register(&ssb_bustype);
1149 if (err)
1150 return err;
1151
1152 /* Maybe we already registered some buses at early boot.
1153 * Check for this and attach them
1154 */
1155 ssb_buses_lock();
1156 err = ssb_attach_queued_buses();
1157 ssb_buses_unlock();
1158 if (err)
1159 bus_unregister(&ssb_bustype);
1160
1161 err = b43_pci_ssb_bridge_init();
1162 if (err) {
1163 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1164 "initialization failed");
1165 /* don't fail SSB init because of this */
1166 err = 0;
1167 }
1168
1169 return err;
1170 }
1171 /* ssb must be initialized after PCI but before the ssb drivers.
1172 * That means we must use some initcall between subsys_initcall
1173 * and device_initcall. */
1174 fs_initcall(ssb_modinit);
1175
1176 static void __exit ssb_modexit(void)
1177 {
1178 b43_pci_ssb_bridge_exit();
1179 bus_unregister(&ssb_bustype);
1180 }
1181 module_exit(ssb_modexit)
Support for the Chinese Samsung S3C2440 based development boards