?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
pciehp: cleanup pcie_poll_cmd
[linux-2.6/mini2440.git] / drivers / serial / imx.c
blob5a375bf0ebf4ab7756bf5ed3529f4f04b44acfde
1 /*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
27 */
28
29 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30 #define SUPPORT_SYSRQ
31 #endif
32
33 #include <linux/module.h>
34 #include <linux/ioport.h>
35 #include <linux/init.h>
36 #include <linux/console.h>
37 #include <linux/sysrq.h>
38 #include <linux/platform_device.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
43
44 #include <asm/io.h>
45 #include <asm/irq.h>
46 #include <asm/hardware.h>
47 #include <asm/arch/imx-uart.h>
48
49 /* Register definitions */
50 #define URXD0 0x0 /* Receiver Register */
51 #define URTX0 0x40 /* Transmitter Register */
52 #define UCR1 0x80 /* Control Register 1 */
53 #define UCR2 0x84 /* Control Register 2 */
54 #define UCR3 0x88 /* Control Register 3 */
55 #define UCR4 0x8c /* Control Register 4 */
56 #define UFCR 0x90 /* FIFO Control Register */
57 #define USR1 0x94 /* Status Register 1 */
58 #define USR2 0x98 /* Status Register 2 */
59 #define UESC 0x9c /* Escape Character Register */
60 #define UTIM 0xa0 /* Escape Timer Register */
61 #define UBIR 0xa4 /* BRM Incremental Register */
62 #define UBMR 0xa8 /* BRM Modulator Register */
63 #define UBRC 0xac /* Baud Rate Count Register */
64 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
65 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
66 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
67 #define BIPR4 0xbc /* Incremental Preset Register 4 */
68 #define BMPR1 0xc0 /* BRM Modulator Register 1 */
69 #define BMPR2 0xc4 /* BRM Modulator Register 2 */
70 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
71 #define BMPR4 0xcc /* BRM Modulator Register 4 */
72 #define UTS 0xd0 /* UART Test Register */
73
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
106 #define UCR2_RXEN (1<<1) /* Receiver enabled */
107 #define UCR2_SRST (1<<0) /* SW reset */
108 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109 #define UCR3_PARERREN (1<<12) /* Parity enable */
110 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111 #define UCR3_DSR (1<<10) /* Data set ready */
112 #define UCR3_DCD (1<<9) /* Data carrier detect */
113 #define UCR3_RI (1<<8) /* Ring indicator */
114 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121 #define UCR3_BPEN (1<<0) /* Preset registers enable */
122 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IRSC (1<<5) /* IR special case */
128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136 #define USR1_RTSS (1<<14) /* RTS pin status */
137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138 #define USR1_RTSD (1<<12) /* RTS delta */
139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149 #define USR2_IDLE (1<<12) /* Idle condition */
150 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151 #define USR2_WAKE (1<<7) /* Wake */
152 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153 #define USR2_TXDC (1<<3) /* Transmitter complete */
154 #define USR2_BRCD (1<<2) /* Break condition */
155 #define USR2_ORE (1<<1) /* Overrun error */
156 #define USR2_RDR (1<<0) /* Recv data ready */
157 #define UTS_FRCPERR (1<<13) /* Force parity error */
158 #define UTS_LOOP (1<<12) /* Loop tx and rx */
159 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161 #define UTS_TXFULL (1<<4) /* TxFIFO full */
162 #define UTS_RXFULL (1<<3) /* RxFIFO full */
163 #define UTS_SOFTRST (1<<0) /* Software reset */
164
165 /* We've been assigned a range on the "Low-density serial ports" major */
166 #define SERIAL_IMX_MAJOR 204
167 #define MINOR_START 41
168
169 /*
170 * This determines how often we check the modem status signals
171 * for any change. They generally aren't connected to an IRQ
172 * so we have to poll them. We also check immediately before
173 * filling the TX fifo incase CTS has been dropped.
174 */
175 #define MCTRL_TIMEOUT (250*HZ/1000)
176
177 #define DRIVER_NAME "IMX-uart"
178
179 struct imx_port {
180 struct uart_port port;
181 struct timer_list timer;
182 unsigned int old_status;
183 int txirq,rxirq,rtsirq;
184 int have_rtscts:1;
185 };
186
187 /*
188 * Handle any change of modem status signal since we were last called.
189 */
190 static void imx_mctrl_check(struct imx_port *sport)
191 {
192 unsigned int status, changed;
193
194 status = sport->port.ops->get_mctrl(&sport->port);
195 changed = status ^ sport->old_status;
196
197 if (changed == 0)
198 return;
199
200 sport->old_status = status;
201
202 if (changed & TIOCM_RI)
203 sport->port.icount.rng++;
204 if (changed & TIOCM_DSR)
205 sport->port.icount.dsr++;
206 if (changed & TIOCM_CAR)
207 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
208 if (changed & TIOCM_CTS)
209 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
210
211 wake_up_interruptible(&sport->port.info->delta_msr_wait);
212 }
213
214 /*
215 * This is our per-port timeout handler, for checking the
216 * modem status signals.
217 */
218 static void imx_timeout(unsigned long data)
219 {
220 struct imx_port *sport = (struct imx_port *)data;
221 unsigned long flags;
222
223 if (sport->port.info) {
224 spin_lock_irqsave(&sport->port.lock, flags);
225 imx_mctrl_check(sport);
226 spin_unlock_irqrestore(&sport->port.lock, flags);
227
228 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
229 }
230 }
231
232 /*
233 * interrupts disabled on entry
234 */
235 static void imx_stop_tx(struct uart_port *port)
236 {
237 struct imx_port *sport = (struct imx_port *)port;
238 unsigned long temp;
239
240 temp = readl(sport->port.membase + UCR1);
241 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
242 }
243
244 /*
245 * interrupts disabled on entry
246 */
247 static void imx_stop_rx(struct uart_port *port)
248 {
249 struct imx_port *sport = (struct imx_port *)port;
250 unsigned long temp;
251
252 temp = readl(sport->port.membase + UCR2);
253 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
254 }
255
256 /*
257 * Set the modem control timer to fire immediately.
258 */
259 static void imx_enable_ms(struct uart_port *port)
260 {
261 struct imx_port *sport = (struct imx_port *)port;
262
263 mod_timer(&sport->timer, jiffies);
264 }
265
266 static inline void imx_transmit_buffer(struct imx_port *sport)
267 {
268 struct circ_buf *xmit = &sport->port.info->xmit;
269
270 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
271 /* send xmit->buf[xmit->tail]
272 * out the port here */
273 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
274 xmit->tail = (xmit->tail + 1) &
275 (UART_XMIT_SIZE - 1);
276 sport->port.icount.tx++;
277 if (uart_circ_empty(xmit))
278 break;
279 }
280
281 if (uart_circ_empty(xmit))
282 imx_stop_tx(&sport->port);
283 }
284
285 /*
286 * interrupts disabled on entry
287 */
288 static void imx_start_tx(struct uart_port *port)
289 {
290 struct imx_port *sport = (struct imx_port *)port;
291 unsigned long temp;
292
293 temp = readl(sport->port.membase + UCR1);
294 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
295
296 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
297 imx_transmit_buffer(sport);
298 }
299
300 static irqreturn_t imx_rtsint(int irq, void *dev_id)
301 {
302 struct imx_port *sport = dev_id;
303 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
304 unsigned long flags;
305
306 spin_lock_irqsave(&sport->port.lock, flags);
307
308 writel(USR1_RTSD, sport->port.membase + USR1);
309 uart_handle_cts_change(&sport->port, !!val);
310 wake_up_interruptible(&sport->port.info->delta_msr_wait);
311
312 spin_unlock_irqrestore(&sport->port.lock, flags);
313 return IRQ_HANDLED;
314 }
315
316 static irqreturn_t imx_txint(int irq, void *dev_id)
317 {
318 struct imx_port *sport = dev_id;
319 struct circ_buf *xmit = &sport->port.info->xmit;
320 unsigned long flags;
321
322 spin_lock_irqsave(&sport->port.lock,flags);
323 if (sport->port.x_char)
324 {
325 /* Send next char */
326 writel(sport->port.x_char, sport->port.membase + URTX0);
327 goto out;
328 }
329
330 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
331 imx_stop_tx(&sport->port);
332 goto out;
333 }
334
335 imx_transmit_buffer(sport);
336
337 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
338 uart_write_wakeup(&sport->port);
339
340 out:
341 spin_unlock_irqrestore(&sport->port.lock,flags);
342 return IRQ_HANDLED;
343 }
344
345 static irqreturn_t imx_rxint(int irq, void *dev_id)
346 {
347 struct imx_port *sport = dev_id;
348 unsigned int rx,flg,ignored = 0;
349 struct tty_struct *tty = sport->port.info->tty;
350 unsigned long flags, temp;
351
352 spin_lock_irqsave(&sport->port.lock,flags);
353
354 while (readl(sport->port.membase + USR2) & USR2_RDR) {
355 flg = TTY_NORMAL;
356 sport->port.icount.rx++;
357
358 rx = readl(sport->port.membase + URXD0);
359
360 temp = readl(sport->port.membase + USR2);
361 if (temp & USR2_BRCD) {
362 writel(temp | USR2_BRCD, sport->port.membase + USR2);
363 if (uart_handle_break(&sport->port))
364 continue;
365 }
366
367 if (uart_handle_sysrq_char
368 (&sport->port, (unsigned char)rx))
369 continue;
370
371 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
372 if (rx & URXD_PRERR)
373 sport->port.icount.parity++;
374 else if (rx & URXD_FRMERR)
375 sport->port.icount.frame++;
376 if (rx & URXD_OVRRUN)
377 sport->port.icount.overrun++;
378
379 if (rx & sport->port.ignore_status_mask) {
380 if (++ignored > 100)
381 goto out;
382 continue;
383 }
384
385 rx &= sport->port.read_status_mask;
386
387 if (rx & URXD_PRERR)
388 flg = TTY_PARITY;
389 else if (rx & URXD_FRMERR)
390 flg = TTY_FRAME;
391 if (rx & URXD_OVRRUN)
392 flg = TTY_OVERRUN;
393
394 #ifdef SUPPORT_SYSRQ
395 sport->port.sysrq = 0;
396 #endif
397 }
398
399 tty_insert_flip_char(tty, rx, flg);
400 }
401
402 out:
403 spin_unlock_irqrestore(&sport->port.lock,flags);
404 tty_flip_buffer_push(tty);
405 return IRQ_HANDLED;
406 }
407
408 /*
409 * Return TIOCSER_TEMT when transmitter is not busy.
410 */
411 static unsigned int imx_tx_empty(struct uart_port *port)
412 {
413 struct imx_port *sport = (struct imx_port *)port;
414
415 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
416 }
417
418 /*
419 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
420 */
421 static unsigned int imx_get_mctrl(struct uart_port *port)
422 {
423 struct imx_port *sport = (struct imx_port *)port;
424 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
425
426 if (readl(sport->port.membase + USR1) & USR1_RTSS)
427 tmp |= TIOCM_CTS;
428
429 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
430 tmp |= TIOCM_RTS;
431
432 return tmp;
433 }
434
435 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
436 {
437 struct imx_port *sport = (struct imx_port *)port;
438 unsigned long temp;
439
440 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
441
442 if (mctrl & TIOCM_RTS)
443 temp |= UCR2_CTS;
444
445 writel(temp, sport->port.membase + UCR2);
446 }
447
448 /*
449 * Interrupts always disabled.
450 */
451 static void imx_break_ctl(struct uart_port *port, int break_state)
452 {
453 struct imx_port *sport = (struct imx_port *)port;
454 unsigned long flags, temp;
455
456 spin_lock_irqsave(&sport->port.lock, flags);
457
458 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
459
460 if ( break_state != 0 )
461 temp |= UCR1_SNDBRK;
462
463 writel(temp, sport->port.membase + UCR1);
464
465 spin_unlock_irqrestore(&sport->port.lock, flags);
466 }
467
468 #define TXTL 2 /* reset default */
469 #define RXTL 1 /* reset default */
470
471 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
472 {
473 unsigned int val;
474 unsigned int ufcr_rfdiv;
475
476 /* set receiver / transmitter trigger level.
477 * RFDIV is set such way to satisfy requested uartclk value
478 */
479 val = TXTL << 10 | RXTL;
480 ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
481
482 if(!ufcr_rfdiv)
483 ufcr_rfdiv = 1;
484
485 if(ufcr_rfdiv >= 7)
486 ufcr_rfdiv = 6;
487 else
488 ufcr_rfdiv = 6 - ufcr_rfdiv;
489
490 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
491
492 writel(val, sport->port.membase + UFCR);
493
494 return 0;
495 }
496
497 static int imx_startup(struct uart_port *port)
498 {
499 struct imx_port *sport = (struct imx_port *)port;
500 int retval;
501 unsigned long flags, temp;
502
503 imx_setup_ufcr(sport, 0);
504
505 /* disable the DREN bit (Data Ready interrupt enable) before
506 * requesting IRQs
507 */
508 temp = readl(sport->port.membase + UCR4);
509 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
510
511 /*
512 * Allocate the IRQ
513 */
514 retval = request_irq(sport->rxirq, imx_rxint, 0,
515 DRIVER_NAME, sport);
516 if (retval) goto error_out1;
517
518 retval = request_irq(sport->txirq, imx_txint, 0,
519 DRIVER_NAME, sport);
520 if (retval) goto error_out2;
521
522 retval = request_irq(sport->rtsirq, imx_rtsint,
523 (sport->rtsirq < IMX_IRQS) ? 0 :
524 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
525 DRIVER_NAME, sport);
526 if (retval) goto error_out3;
527
528 /*
529 * Finally, clear and enable interrupts
530 */
531 writel(USR1_RTSD, sport->port.membase + USR1);
532
533 temp = readl(sport->port.membase + UCR1);
534 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
535 writel(temp, sport->port.membase + UCR1);
536
537 temp = readl(sport->port.membase + UCR2);
538 temp |= (UCR2_RXEN | UCR2_TXEN);
539 writel(temp, sport->port.membase + UCR2);
540
541 /*
542 * Enable modem status interrupts
543 */
544 spin_lock_irqsave(&sport->port.lock,flags);
545 imx_enable_ms(&sport->port);
546 spin_unlock_irqrestore(&sport->port.lock,flags);
547
548 return 0;
549
550 error_out3:
551 free_irq(sport->txirq, sport);
552 error_out2:
553 free_irq(sport->rxirq, sport);
554 error_out1:
555 return retval;
556 }
557
558 static void imx_shutdown(struct uart_port *port)
559 {
560 struct imx_port *sport = (struct imx_port *)port;
561 unsigned long temp;
562
563 /*
564 * Stop our timer.
565 */
566 del_timer_sync(&sport->timer);
567
568 /*
569 * Free the interrupts
570 */
571 free_irq(sport->rtsirq, sport);
572 free_irq(sport->txirq, sport);
573 free_irq(sport->rxirq, sport);
574
575 /*
576 * Disable all interrupts, port and break condition.
577 */
578
579 temp = readl(sport->port.membase + UCR1);
580 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
581 writel(temp, sport->port.membase + UCR1);
582 }
583
584 static void
585 imx_set_termios(struct uart_port *port, struct ktermios *termios,
586 struct ktermios *old)
587 {
588 struct imx_port *sport = (struct imx_port *)port;
589 unsigned long flags;
590 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
591 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
592
593 /*
594 * If we don't support modem control lines, don't allow
595 * these to be set.
596 */
597 if (0) {
598 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
599 termios->c_cflag |= CLOCAL;
600 }
601
602 /*
603 * We only support CS7 and CS8.
604 */
605 while ((termios->c_cflag & CSIZE) != CS7 &&
606 (termios->c_cflag & CSIZE) != CS8) {
607 termios->c_cflag &= ~CSIZE;
608 termios->c_cflag |= old_csize;
609 old_csize = CS8;
610 }
611
612 if ((termios->c_cflag & CSIZE) == CS8)
613 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
614 else
615 ucr2 = UCR2_SRST | UCR2_IRTS;
616
617 if (termios->c_cflag & CRTSCTS) {
618 if( sport->have_rtscts ) {
619 ucr2 &= ~UCR2_IRTS;
620 ucr2 |= UCR2_CTSC;
621 } else {
622 termios->c_cflag &= ~CRTSCTS;
623 }
624 }
625
626 if (termios->c_cflag & CSTOPB)
627 ucr2 |= UCR2_STPB;
628 if (termios->c_cflag & PARENB) {
629 ucr2 |= UCR2_PREN;
630 if (termios->c_cflag & PARODD)
631 ucr2 |= UCR2_PROE;
632 }
633
634 /*
635 * Ask the core to calculate the divisor for us.
636 */
637 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
638 quot = uart_get_divisor(port, baud);
639
640 spin_lock_irqsave(&sport->port.lock, flags);
641
642 sport->port.read_status_mask = 0;
643 if (termios->c_iflag & INPCK)
644 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
645 if (termios->c_iflag & (BRKINT | PARMRK))
646 sport->port.read_status_mask |= URXD_BRK;
647
648 /*
649 * Characters to ignore
650 */
651 sport->port.ignore_status_mask = 0;
652 if (termios->c_iflag & IGNPAR)
653 sport->port.ignore_status_mask |= URXD_PRERR;
654 if (termios->c_iflag & IGNBRK) {
655 sport->port.ignore_status_mask |= URXD_BRK;
656 /*
657 * If we're ignoring parity and break indicators,
658 * ignore overruns too (for real raw support).
659 */
660 if (termios->c_iflag & IGNPAR)
661 sport->port.ignore_status_mask |= URXD_OVRRUN;
662 }
663
664 del_timer_sync(&sport->timer);
665
666 /*
667 * Update the per-port timeout.
668 */
669 uart_update_timeout(port, termios->c_cflag, baud);
670
671 /*
672 * disable interrupts and drain transmitter
673 */
674 old_ucr1 = readl(sport->port.membase + UCR1);
675 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
676 sport->port.membase + UCR1);
677
678 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
679 barrier();
680
681 /* then, disable everything */
682 old_txrxen = readl(sport->port.membase + UCR2);
683 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
684 sport->port.membase + UCR2);
685 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
686
687 /* set the baud rate. We assume uartclk = 16 MHz
688 *
689 * baud * 16 UBIR - 1
690 * --------- = --------
691 * uartclk UBMR - 1
692 */
693 writel((baud / 100) - 1, sport->port.membase + UBIR);
694 writel(10000 - 1, sport->port.membase + UBMR);
695
696 writel(old_ucr1, sport->port.membase + UCR1);
697
698 /* set the parity, stop bits and data size */
699 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
700
701 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
702 imx_enable_ms(&sport->port);
703
704 spin_unlock_irqrestore(&sport->port.lock, flags);
705 }
706
707 static const char *imx_type(struct uart_port *port)
708 {
709 struct imx_port *sport = (struct imx_port *)port;
710
711 return sport->port.type == PORT_IMX ? "IMX" : NULL;
712 }
713
714 /*
715 * Release the memory region(s) being used by 'port'.
716 */
717 static void imx_release_port(struct uart_port *port)
718 {
719 struct platform_device *pdev = to_platform_device(port->dev);
720 struct resource *mmres;
721
722 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
723 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
724 }
725
726 /*
727 * Request the memory region(s) being used by 'port'.
728 */
729 static int imx_request_port(struct uart_port *port)
730 {
731 struct platform_device *pdev = to_platform_device(port->dev);
732 struct resource *mmres;
733 void *ret;
734
735 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
736 if (!mmres)
737 return -ENODEV;
738
739 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
740 "imx-uart");
741
742 return ret ? 0 : -EBUSY;
743 }
744
745 /*
746 * Configure/autoconfigure the port.
747 */
748 static void imx_config_port(struct uart_port *port, int flags)
749 {
750 struct imx_port *sport = (struct imx_port *)port;
751
752 if (flags & UART_CONFIG_TYPE &&
753 imx_request_port(&sport->port) == 0)
754 sport->port.type = PORT_IMX;
755 }
756
757 /*
758 * Verify the new serial_struct (for TIOCSSERIAL).
759 * The only change we allow are to the flags and type, and
760 * even then only between PORT_IMX and PORT_UNKNOWN
761 */
762 static int
763 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
764 {
765 struct imx_port *sport = (struct imx_port *)port;
766 int ret = 0;
767
768 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
769 ret = -EINVAL;
770 if (sport->port.irq != ser->irq)
771 ret = -EINVAL;
772 if (ser->io_type != UPIO_MEM)
773 ret = -EINVAL;
774 if (sport->port.uartclk / 16 != ser->baud_base)
775 ret = -EINVAL;
776 if ((void *)sport->port.mapbase != ser->iomem_base)
777 ret = -EINVAL;
778 if (sport->port.iobase != ser->port)
779 ret = -EINVAL;
780 if (ser->hub6 != 0)
781 ret = -EINVAL;
782 return ret;
783 }
784
785 static struct uart_ops imx_pops = {
786 .tx_empty = imx_tx_empty,
787 .set_mctrl = imx_set_mctrl,
788 .get_mctrl = imx_get_mctrl,
789 .stop_tx = imx_stop_tx,
790 .start_tx = imx_start_tx,
791 .stop_rx = imx_stop_rx,
792 .enable_ms = imx_enable_ms,
793 .break_ctl = imx_break_ctl,
794 .startup = imx_startup,
795 .shutdown = imx_shutdown,
796 .set_termios = imx_set_termios,
797 .type = imx_type,
798 .release_port = imx_release_port,
799 .request_port = imx_request_port,
800 .config_port = imx_config_port,
801 .verify_port = imx_verify_port,
802 };
803
804 static struct imx_port imx_ports[] = {
805 {
806 .txirq = UART1_MINT_TX,
807 .rxirq = UART1_MINT_RX,
808 .rtsirq = UART1_MINT_RTS,
809 .port = {
810 .type = PORT_IMX,
811 .iotype = UPIO_MEM,
812 .membase = (void *)IMX_UART1_BASE,
813 .mapbase = 0x00206000,
814 .irq = UART1_MINT_RX,
815 .uartclk = 16000000,
816 .fifosize = 32,
817 .flags = UPF_BOOT_AUTOCONF,
818 .ops = &imx_pops,
819 .line = 0,
820 },
821 }, {
822 .txirq = UART2_MINT_TX,
823 .rxirq = UART2_MINT_RX,
824 .rtsirq = UART2_MINT_RTS,
825 .port = {
826 .type = PORT_IMX,
827 .iotype = UPIO_MEM,
828 .membase = (void *)IMX_UART2_BASE,
829 .mapbase = 0x00207000,
830 .irq = UART2_MINT_RX,
831 .uartclk = 16000000,
832 .fifosize = 32,
833 .flags = UPF_BOOT_AUTOCONF,
834 .ops = &imx_pops,
835 .line = 1,
836 },
837 }
838 };
839
840 /*
841 * Setup the IMX serial ports.
842 * Note also that we support "console=ttySMXx" where "x" is either 0 or 1.
843 * Which serial port this ends up being depends on the machine you're
844 * running this kernel on. I'm not convinced that this is a good idea,
845 * but that's the way it traditionally works.
846 *
847 */
848 static void __init imx_init_ports(void)
849 {
850 static int first = 1;
851 int i;
852
853 if (!first)
854 return;
855 first = 0;
856
857 for (i = 0; i < ARRAY_SIZE(imx_ports); i++) {
858 init_timer(&imx_ports[i].timer);
859 imx_ports[i].timer.function = imx_timeout;
860 imx_ports[i].timer.data = (unsigned long)&imx_ports[i];
861 }
862 }
863
864 #ifdef CONFIG_SERIAL_IMX_CONSOLE
865 static void imx_console_putchar(struct uart_port *port, int ch)
866 {
867 struct imx_port *sport = (struct imx_port *)port;
868
869 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
870 barrier();
871
872 writel(ch, sport->port.membase + URTX0);
873 }
874
875 /*
876 * Interrupts are disabled on entering
877 */
878 static void
879 imx_console_write(struct console *co, const char *s, unsigned int count)
880 {
881 struct imx_port *sport = &imx_ports[co->index];
882 unsigned int old_ucr1, old_ucr2;
883
884 /*
885 * First, save UCR1/2 and then disable interrupts
886 */
887 old_ucr1 = readl(sport->port.membase + UCR1);
888 old_ucr2 = readl(sport->port.membase + UCR2);
889
890 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
891 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
892 sport->port.membase + UCR1);
893
894 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
895
896 uart_console_write(&sport->port, s, count, imx_console_putchar);
897
898 /*
899 * Finally, wait for transmitter to become empty
900 * and restore UCR1/2
901 */
902 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
903
904 writel(old_ucr1, sport->port.membase + UCR1);
905 writel(old_ucr2, sport->port.membase + UCR2);
906 }
907
908 /*
909 * If the port was already initialised (eg, by a boot loader),
910 * try to determine the current setup.
911 */
912 static void __init
913 imx_console_get_options(struct imx_port *sport, int *baud,
914 int *parity, int *bits)
915 {
916
917 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
918 /* ok, the port was enabled */
919 unsigned int ucr2, ubir,ubmr, uartclk;
920 unsigned int baud_raw;
921 unsigned int ucfr_rfdiv;
922
923 ucr2 = readl(sport->port.membase + UCR2);
924
925 *parity = 'n';
926 if (ucr2 & UCR2_PREN) {
927 if (ucr2 & UCR2_PROE)
928 *parity = 'o';
929 else
930 *parity = 'e';
931 }
932
933 if (ucr2 & UCR2_WS)
934 *bits = 8;
935 else
936 *bits = 7;
937
938 ubir = readl(sport->port.membase + UBIR) & 0xffff;
939 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
940
941 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
942 if (ucfr_rfdiv == 6)
943 ucfr_rfdiv = 7;
944 else
945 ucfr_rfdiv = 6 - ucfr_rfdiv;
946
947 uartclk = imx_get_perclk1();
948 uartclk /= ucfr_rfdiv;
949
950 { /*
951 * The next code provides exact computation of
952 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
953 * without need of float support or long long division,
954 * which would be required to prevent 32bit arithmetic overflow
955 */
956 unsigned int mul = ubir + 1;
957 unsigned int div = 16 * (ubmr + 1);
958 unsigned int rem = uartclk % div;
959
960 baud_raw = (uartclk / div) * mul;
961 baud_raw += (rem * mul + div / 2) / div;
962 *baud = (baud_raw + 50) / 100 * 100;
963 }
964
965 if(*baud != baud_raw)
966 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
967 baud_raw, *baud);
968 }
969 }
970
971 static int __init
972 imx_console_setup(struct console *co, char *options)
973 {
974 struct imx_port *sport;
975 int baud = 9600;
976 int bits = 8;
977 int parity = 'n';
978 int flow = 'n';
979
980 /*
981 * Check whether an invalid uart number has been specified, and
982 * if so, search for the first available port that does have
983 * console support.
984 */
985 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
986 co->index = 0;
987 sport = &imx_ports[co->index];
988
989 if (options)
990 uart_parse_options(options, &baud, &parity, &bits, &flow);
991 else
992 imx_console_get_options(sport, &baud, &parity, &bits);
993
994 imx_setup_ufcr(sport, 0);
995
996 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
997 }
998
999 static struct uart_driver imx_reg;
1000 static struct console imx_console = {
1001 .name = "ttySMX",
1002 .write = imx_console_write,
1003 .device = uart_console_device,
1004 .setup = imx_console_setup,
1005 .flags = CON_PRINTBUFFER,
1006 .index = -1,
1007 .data = &imx_reg,
1008 };
1009
1010 static int __init imx_rs_console_init(void)
1011 {
1012 imx_init_ports();
1013 register_console(&imx_console);
1014 return 0;
1015 }
1016 console_initcall(imx_rs_console_init);
1017
1018 #define IMX_CONSOLE &imx_console
1019 #else
1020 #define IMX_CONSOLE NULL
1021 #endif
1022
1023 static struct uart_driver imx_reg = {
1024 .owner = THIS_MODULE,
1025 .driver_name = DRIVER_NAME,
1026 .dev_name = "ttySMX",
1027 .major = SERIAL_IMX_MAJOR,
1028 .minor = MINOR_START,
1029 .nr = ARRAY_SIZE(imx_ports),
1030 .cons = IMX_CONSOLE,
1031 };
1032
1033 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1034 {
1035 struct imx_port *sport = platform_get_drvdata(dev);
1036
1037 if (sport)
1038 uart_suspend_port(&imx_reg, &sport->port);
1039
1040 return 0;
1041 }
1042
1043 static int serial_imx_resume(struct platform_device *dev)
1044 {
1045 struct imx_port *sport = platform_get_drvdata(dev);
1046
1047 if (sport)
1048 uart_resume_port(&imx_reg, &sport->port);
1049
1050 return 0;
1051 }
1052
1053 static int serial_imx_probe(struct platform_device *dev)
1054 {
1055 struct imxuart_platform_data *pdata;
1056
1057 imx_ports[dev->id].port.dev = &dev->dev;
1058
1059 pdata = (struct imxuart_platform_data *)dev->dev.platform_data;
1060 if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1061 imx_ports[dev->id].have_rtscts = 1;
1062
1063 uart_add_one_port(&imx_reg, &imx_ports[dev->id].port);
1064 platform_set_drvdata(dev, &imx_ports[dev->id]);
1065 return 0;
1066 }
1067
1068 static int serial_imx_remove(struct platform_device *dev)
1069 {
1070 struct imx_port *sport = platform_get_drvdata(dev);
1071
1072 platform_set_drvdata(dev, NULL);
1073
1074 if (sport)
1075 uart_remove_one_port(&imx_reg, &sport->port);
1076
1077 return 0;
1078 }
1079
1080 static struct platform_driver serial_imx_driver = {
1081 .probe = serial_imx_probe,
1082 .remove = serial_imx_remove,
1083
1084 .suspend = serial_imx_suspend,
1085 .resume = serial_imx_resume,
1086 .driver = {
1087 .name = "imx-uart",
1088 .owner = THIS_MODULE,
1089 },
1090 };
1091
1092 static int __init imx_serial_init(void)
1093 {
1094 int ret;
1095
1096 printk(KERN_INFO "Serial: IMX driver\n");
1097
1098 imx_init_ports();
1099
1100 ret = uart_register_driver(&imx_reg);
1101 if (ret)
1102 return ret;
1103
1104 ret = platform_driver_register(&serial_imx_driver);
1105 if (ret != 0)
1106 uart_unregister_driver(&imx_reg);
1107
1108 return 0;
1109 }
1110
1111 static void __exit imx_serial_exit(void)
1112 {
1113 platform_driver_unregister(&serial_imx_driver);
1114 uart_unregister_driver(&imx_reg);
1115 }
1116
1117 module_init(imx_serial_init);
1118 module_exit(imx_serial_exit);
1119
1120 MODULE_AUTHOR("Sascha Hauer");
1121 MODULE_DESCRIPTION("IMX generic serial port driver");
1122 MODULE_LICENSE("GPL");
1123 MODULE_ALIAS("platform:imx-uart");
Support for the Chinese Samsung S3C2440 based development boards