arch/x86/kernel/smp_32.c

   1 /*
   2  *      Intel SMP support routines.
   3  *
   4  *      (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
   5  *      (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
   6  *
   7  *      This code is released under the GNU General Public License version 2 or
   8  *      later.
   9  */
  10
  11 #include <linux/init.h>
  12
  13 #include <linux/mm.h>
  14 #include <linux/delay.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/mc146818rtc.h>
  18 #include <linux/cache.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/cpu.h>
  21 #include <linux/module.h>
  22
  23 #include <asm/mtrr.h>
  24 #include <asm/tlbflush.h>
  25 #include <asm/mmu_context.h>
  26 #include <mach_apic.h>
  27 #include <asm/proto.h>
  28
  29 /*
  30  *      Some notes on x86 processor bugs affecting SMP operation:
  31  *
  32  *      Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
  33  *      The Linux implications for SMP are handled as follows:
  34  *
  35  *      Pentium III / [Xeon]
  36  *              None of the E1AP-E3AP errata are visible to the user.
  37  *
  38  *      E1AP.   see PII A1AP
  39  *      E2AP.   see PII A2AP
  40  *      E3AP.   see PII A3AP
  41  *
  42  *      Pentium II / [Xeon]
  43  *              None of the A1AP-A3AP errata are visible to the user.
  44  *
  45  *      A1AP.   see PPro 1AP
  46  *      A2AP.   see PPro 2AP
  47  *      A3AP.   see PPro 7AP
  48  *
  49  *      Pentium Pro
  50  *              None of 1AP-9AP errata are visible to the normal user,
  51  *      except occasional delivery of 'spurious interrupt' as trap #15.
  52  *      This is very rare and a non-problem.
  53  *
  54  *      1AP.    Linux maps APIC as non-cacheable
  55  *      2AP.    worked around in hardware
  56  *      3AP.    fixed in C0 and above steppings microcode update.
  57  *              Linux does not use excessive STARTUP_IPIs.
  58  *      4AP.    worked around in hardware
  59  *      5AP.    symmetric IO mode (normal Linux operation) not affected.
  60  *              'noapic' mode has vector 0xf filled out properly.
  61  *      6AP.    'noapic' mode might be affected - fixed in later steppings
  62  *      7AP.    We do not assume writes to the LVT deassering IRQs
  63  *      8AP.    We do not enable low power mode (deep sleep) during MP bootup
  64  *      9AP.    We do not use mixed mode
  65  *
  66  *      Pentium
  67  *              There is a marginal case where REP MOVS on 100MHz SMP
  68  *      machines with B stepping processors can fail. XXX should provide
  69  *      an L1cache=Writethrough or L1cache=off option.
  70  *
  71  *              B stepping CPUs may hang. There are hardware work arounds
  72  *      for this. We warn about it in case your board doesn't have the work
  73  *      arounds. Basically that's so I can tell anyone with a B stepping
  74  *      CPU and SMP problems "tough".
  75  *
  76  *      Specific items [From Pentium Processor Specification Update]
  77  *
  78  *      1AP.    Linux doesn't use remote read
  79  *      2AP.    Linux doesn't trust APIC errors
  80  *      3AP.    We work around this
  81  *      4AP.    Linux never generated 3 interrupts of the same priority
  82  *              to cause a lost local interrupt.
  83  *      5AP.    Remote read is never used
  84  *      6AP.    not affected - worked around in hardware
  85  *      7AP.    not affected - worked around in hardware
  86  *      8AP.    worked around in hardware - we get explicit CS errors if not
  87  *      9AP.    only 'noapic' mode affected. Might generate spurious
  88  *              interrupts, we log only the first one and count the
  89  *              rest silently.
  90  *      10AP.   not affected - worked around in hardware
  91  *      11AP.   Linux reads the APIC between writes to avoid this, as per
  92  *              the documentation. Make sure you preserve this as it affects
  93  *              the C stepping chips too.
  94  *      12AP.   not affected - worked around in hardware
  95  *      13AP.   not affected - worked around in hardware
  96  *      14AP.   we always deassert INIT during bootup
  97  *      15AP.   not affected - worked around in hardware
  98  *      16AP.   not affected - worked around in hardware
  99  *      17AP.   not affected - worked around in hardware
 100  *      18AP.   not affected - worked around in hardware
 101  *      19AP.   not affected - worked around in BIOS
 102  *
 103  *      If this sounds worrying believe me these bugs are either ___RARE___,
 104  *      or are signal timing bugs worked around in hardware and there's
 105  *      about nothing of note with C stepping upwards.
 106  */
 107
 108 DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };
 109
 110 #include <mach_ipi.h> /* must come after the send_IPI functions above for inlining */
 111
 112 /*
 113  *      Smarter SMP flushing macros.
 114  *              c/o Linus Torvalds.
 115  *
 116  *      These mean you can really definitely utterly forget about
 117  *      writing to user space from interrupts. (Its not allowed anyway).
 118  *
 119  *      Optimizations Manfred Spraul <manfred@colorfullife.com>
 120  */
 121
 122 static cpumask_t flush_cpumask;
 123 static struct mm_struct * flush_mm;
 124 static unsigned long flush_va;
 125 static DEFINE_SPINLOCK(tlbstate_lock);
 126
 127 /*
 128  * We cannot call mmdrop() because we are in interrupt context,
 129  * instead update mm->cpu_vm_mask.
 130  *
 131  * We need to reload %cr3 since the page tables may be going
 132  * away from under us..
 133  */
 134 void leave_mm(int cpu)
 135 {
 136         if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
 137                 BUG();
 138         cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
 139         load_cr3(swapper_pg_dir);
 140 }
 141 EXPORT_SYMBOL_GPL(leave_mm);
 142
 143 /*
 144  *
 145  * The flush IPI assumes that a thread switch happens in this order:
 146  * [cpu0: the cpu that switches]
 147  * 1) switch_mm() either 1a) or 1b)
 148  * 1a) thread switch to a different mm
 149  * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
 150  *      Stop ipi delivery for the old mm. This is not synchronized with
 151  *      the other cpus, but smp_invalidate_interrupt ignore flush ipis
 152  *      for the wrong mm, and in the worst case we perform a superfluous
 153  *      tlb flush.
 154  * 1a2) set cpu_tlbstate to TLBSTATE_OK
 155  *      Now the smp_invalidate_interrupt won't call leave_mm if cpu0
 156  *      was in lazy tlb mode.
 157  * 1a3) update cpu_tlbstate[].active_mm
 158  *      Now cpu0 accepts tlb flushes for the new mm.
 159  * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
 160  *      Now the other cpus will send tlb flush ipis.
 161  * 1a4) change cr3.
 162  * 1b) thread switch without mm change
 163  *      cpu_tlbstate[].active_mm is correct, cpu0 already handles
 164  *      flush ipis.
 165  * 1b1) set cpu_tlbstate to TLBSTATE_OK
 166  * 1b2) test_and_set the cpu bit in cpu_vm_mask.
 167  *      Atomically set the bit [other cpus will start sending flush ipis],
 168  *      and test the bit.
 169  * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
 170  * 2) switch %%esp, ie current
 171  *
 172  * The interrupt must handle 2 special cases:
 173  * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
 174  * - the cpu performs speculative tlb reads, i.e. even if the cpu only
 175  *   runs in kernel space, the cpu could load tlb entries for user space
 176  *   pages.
 177  *
 178  * The good news is that cpu_tlbstate is local to each cpu, no
 179  * write/read ordering problems.
 180  */
 181
 182 /*
 183  * TLB flush IPI:
 184  *
 185  * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
 186  * 2) Leave the mm if we are in the lazy tlb mode.
 187  */
 188
 189 void smp_invalidate_interrupt(struct pt_regs *regs)
 190 {
 191         unsigned long cpu;
 192
 193         cpu = get_cpu();
 194
 195         if (!cpu_isset(cpu, flush_cpumask))
 196                 goto out;
 197                 /*
 198                  * This was a BUG() but until someone can quote me the
 199                  * line from the intel manual that guarantees an IPI to
 200                  * multiple CPUs is retried _only_ on the erroring CPUs
 201                  * its staying as a return
 202                  *
 203                  * BUG();
 204                  */
 205
 206         if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
 207                 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
 208                         if (flush_va == TLB_FLUSH_ALL)
 209                                 local_flush_tlb();
 210                         else
 211                                 __flush_tlb_one(flush_va);
 212                 } else
 213                         leave_mm(cpu);
 214         }
 215         ack_APIC_irq();
 216         smp_mb__before_clear_bit();
 217         cpu_clear(cpu, flush_cpumask);
 218         smp_mb__after_clear_bit();
 219 out:
 220         put_cpu_no_resched();
 221         __get_cpu_var(irq_stat).irq_tlb_count++;
 222 }
 223
 224 void native_flush_tlb_others(const cpumask_t *cpumaskp, struct mm_struct *mm,
 225                              unsigned long va)
 226 {
 227         cpumask_t cpumask = *cpumaskp;
 228
 229         /*
 230          * A couple of (to be removed) sanity checks:
 231          *
 232          * - current CPU must not be in mask
 233          * - mask must exist :)
 234          */
 235         BUG_ON(cpus_empty(cpumask));
 236         BUG_ON(cpu_isset(smp_processor_id(), cpumask));
 237         BUG_ON(!mm);
 238
 239 #ifdef CONFIG_HOTPLUG_CPU
 240         /* If a CPU which we ran on has gone down, OK. */
 241         cpus_and(cpumask, cpumask, cpu_online_map);
 242         if (unlikely(cpus_empty(cpumask)))
 243                 return;
 244 #endif
 245
 246         /*
 247          * i'm not happy about this global shared spinlock in the
 248          * MM hot path, but we'll see how contended it is.
 249          * AK: x86-64 has a faster method that could be ported.
 250          */
 251         spin_lock(&tlbstate_lock);
 252
 253         flush_mm = mm;
 254         flush_va = va;
 255         cpus_or(flush_cpumask, cpumask, flush_cpumask);
 256         /*
 257          * We have to send the IPI only to
 258          * CPUs affected.
 259          */
 260         send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
 261
 262         while (!cpus_empty(flush_cpumask))
 263                 /* nothing. lockup detection does not belong here */
 264                 cpu_relax();
 265
 266         flush_mm = NULL;
 267         flush_va = 0;
 268         spin_unlock(&tlbstate_lock);
 269 }
 270
 271 void flush_tlb_current_task(void)
 272 {
 273         struct mm_struct *mm = current->mm;
 274         cpumask_t cpu_mask;
 275
 276         preempt_disable();
 277         cpu_mask = mm->cpu_vm_mask;
 278         cpu_clear(smp_processor_id(), cpu_mask);
 279
 280         local_flush_tlb();
 281         if (!cpus_empty(cpu_mask))
 282                 flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
 283         preempt_enable();
 284 }
 285
 286 void flush_tlb_mm (struct mm_struct * mm)
 287 {
 288         cpumask_t cpu_mask;
 289
 290         preempt_disable();
 291         cpu_mask = mm->cpu_vm_mask;
 292         cpu_clear(smp_processor_id(), cpu_mask);
 293
 294         if (current->active_mm == mm) {
 295                 if (current->mm)
 296                         local_flush_tlb();
 297                 else
 298                         leave_mm(smp_processor_id());
 299         }
 300         if (!cpus_empty(cpu_mask))
 301                 flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
 302
 303         preempt_enable();
 304 }
 305
 306 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
 307 {
 308         struct mm_struct *mm = vma->vm_mm;
 309         cpumask_t cpu_mask;
 310
 311         preempt_disable();
 312         cpu_mask = mm->cpu_vm_mask;
 313         cpu_clear(smp_processor_id(), cpu_mask);
 314
 315         if (current->active_mm == mm) {
 316                 if(current->mm)
 317                         __flush_tlb_one(va);
 318                  else
 319                         leave_mm(smp_processor_id());
 320         }
 321
 322         if (!cpus_empty(cpu_mask))
 323                 flush_tlb_others(cpu_mask, mm, va);
 324
 325         preempt_enable();
 326 }
 327 EXPORT_SYMBOL(flush_tlb_page);
 328
 329 static void do_flush_tlb_all(void* info)
 330 {
 331         unsigned long cpu = smp_processor_id();
 332
 333         __flush_tlb_all();
 334         if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
 335                 leave_mm(cpu);
 336 }
 337
 338 void flush_tlb_all(void)
 339 {
 340         on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
 341 }