?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
libata: set device class to NONE if phys_offline
[linux-2.6/mini2440.git] / sound / pci / cmipci.c
blob1a74ca62c31484a8b8923f324771c43fcd1491a3
1 /*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
22
23 #include <asm/io.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/gameport.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mutex.h>
32 #include <sound/core.h>
33 #include <sound/info.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/rawmidi.h>
37 #include <sound/mpu401.h>
38 #include <sound/opl3.h>
39 #include <sound/sb.h>
40 #include <sound/asoundef.h>
41 #include <sound/initval.h>
42
43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45 MODULE_LICENSE("GPL");
46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
47 "{C-Media,CMI8738B},"
48 "{C-Media,CMI8338A},"
49 "{C-Media,CMI8338B}}");
50
51 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52 #define SUPPORT_JOYSTICK 1
53 #endif
54
55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
58 static long mpu_port[SNDRV_CARDS];
59 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
60 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 #ifdef SUPPORT_JOYSTICK
62 static int joystick_port[SNDRV_CARDS];
63 #endif
64
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
71 module_param_array(mpu_port, long, NULL, 0444);
72 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
73 module_param_array(fm_port, long, NULL, 0444);
74 MODULE_PARM_DESC(fm_port, "FM port.");
75 module_param_array(soft_ac3, bool, NULL, 0444);
76 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
77 #ifdef SUPPORT_JOYSTICK
78 module_param_array(joystick_port, int, NULL, 0444);
79 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
80 #endif
81
82 /*
83 * CM8x38 registers definition
84 */
85
86 #define CM_REG_FUNCTRL0 0x00
87 #define CM_RST_CH1 0x00080000
88 #define CM_RST_CH0 0x00040000
89 #define CM_CHEN1 0x00020000 /* ch1: enable */
90 #define CM_CHEN0 0x00010000 /* ch0: enable */
91 #define CM_PAUSE1 0x00000008 /* ch1: pause */
92 #define CM_PAUSE0 0x00000004 /* ch0: pause */
93 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
94 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
95
96 #define CM_REG_FUNCTRL1 0x04
97 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
98 #define CM_DSFC_SHIFT 13
99 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
100 #define CM_ASFC_SHIFT 10
101 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
102 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
103 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
104 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
105 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
106 #define CM_BREQ 0x00000010 /* bus master enabled */
107 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
108 #define CM_UART_EN 0x00000004 /* legacy UART */
109 #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
110 #define CM_ZVPORT 0x00000001 /* ZVPORT */
111
112 #define CM_REG_CHFORMAT 0x08
113
114 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
115 #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
116 #define CM_CHB3D 0x20000000 /* 4 channels */
117
118 #define CM_CHIP_MASK1 0x1f000000
119 #define CM_CHIP_037 0x01000000
120 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
121 #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
122 #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
123 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
124 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
125 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
126 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
127
128 #define CM_ADCBITLEN_MASK 0x0000C000
129 #define CM_ADCBITLEN_16 0x00000000
130 #define CM_ADCBITLEN_15 0x00004000
131 #define CM_ADCBITLEN_14 0x00008000
132 #define CM_ADCBITLEN_13 0x0000C000
133
134 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
135 #define CM_ADCDACLEN_060 0x00000000
136 #define CM_ADCDACLEN_066 0x00001000
137 #define CM_ADCDACLEN_130 0x00002000
138 #define CM_ADCDACLEN_280 0x00003000
139
140 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
141 #define CM_ADCDLEN_ORIGINAL 0x00000000
142 #define CM_ADCDLEN_EXTRA 0x00001000
143 #define CM_ADCDLEN_24K 0x00002000
144 #define CM_ADCDLEN_WEIGHT 0x00003000
145
146 #define CM_CH1_SRATE_176K 0x00000800
147 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
148 #define CM_CH1_SRATE_88K 0x00000400
149 #define CM_CH0_SRATE_176K 0x00000200
150 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
151 #define CM_CH0_SRATE_88K 0x00000100
152 #define CM_CH0_SRATE_128K 0x00000300
153 #define CM_CH0_SRATE_MASK 0x00000300
154
155 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
156 #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
157 #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
158 #define CM_SPDLOCKED 0x00000010
159
160 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
161 #define CM_CH1FMT_SHIFT 2
162 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
163 #define CM_CH0FMT_SHIFT 0
164
165 #define CM_REG_INT_HLDCLR 0x0C
166 #define CM_CHIP_MASK2 0xff000000
167 #define CM_CHIP_8768 0x20000000
168 #define CM_CHIP_055 0x08000000
169 #define CM_CHIP_039 0x04000000
170 #define CM_CHIP_039_6CH 0x01000000
171 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
172 #define CM_TDMA_INT_EN 0x00040000
173 #define CM_CH1_INT_EN 0x00020000
174 #define CM_CH0_INT_EN 0x00010000
175
176 #define CM_REG_INT_STATUS 0x10
177 #define CM_INTR 0x80000000
178 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
179 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
180 #define CM_UARTINT 0x00010000
181 #define CM_LTDMAINT 0x00008000
182 #define CM_HTDMAINT 0x00004000
183 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
184 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
185 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
186 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
187 #define CM_CH1BUSY 0x00000008
188 #define CM_CH0BUSY 0x00000004
189 #define CM_CHINT1 0x00000002
190 #define CM_CHINT0 0x00000001
191
192 #define CM_REG_LEGACY_CTRL 0x14
193 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
194 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
195 #define CM_VMPU_330 0x00000000
196 #define CM_VMPU_320 0x20000000
197 #define CM_VMPU_310 0x40000000
198 #define CM_VMPU_300 0x60000000
199 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
200 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
201 #define CM_VSBSEL_220 0x00000000
202 #define CM_VSBSEL_240 0x04000000
203 #define CM_VSBSEL_260 0x08000000
204 #define CM_VSBSEL_280 0x0C000000
205 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
206 #define CM_FMSEL_388 0x00000000
207 #define CM_FMSEL_3C8 0x01000000
208 #define CM_FMSEL_3E0 0x02000000
209 #define CM_FMSEL_3E8 0x03000000
210 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
211 #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
212 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
213 #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
214 #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
215 #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
216 #define CM_C_EECS 0x00040000
217 #define CM_C_EEDI46 0x00020000
218 #define CM_C_EECK46 0x00010000
219 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
220 #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
221 #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
222 #define CM_EXBASEN 0x00001000 /* external bass input enable */
223
224 #define CM_REG_MISC_CTRL 0x18
225 #define CM_PWD 0x80000000 /* power down */
226 #define CM_RESET 0x40000000
227 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
228 #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
229 #define CM_TXVX 0x08000000 /* model 037? */
230 #define CM_N4SPK3D 0x04000000 /* copy front to rear */
231 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
232 #define CM_SPDIF48K 0x01000000 /* write */
233 #define CM_SPATUS48K 0x01000000 /* read */
234 #define CM_ENDBDAC 0x00800000 /* enable double dac */
235 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
236 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
237 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
238 #define CM_FM_EN 0x00080000 /* enable legacy FM */
239 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
240 #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
241 #define CM_VIDWPDSB 0x00010000 /* model 037? */
242 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
243 #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
244 #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
245 #define CM_VIDWPPRT 0x00002000 /* model 037? */
246 #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
247 #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
248 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
249 #define CM_ENCENTER 0x00000080
250 #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
251 #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
252 #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
253 #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
254 #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
255 #define CM_UPDDMA_2048 0x00000000
256 #define CM_UPDDMA_1024 0x00000004
257 #define CM_UPDDMA_512 0x00000008
258 #define CM_UPDDMA_256 0x0000000C
259 #define CM_TWAIT_MASK 0x00000003 /* model 037 */
260 #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
261 #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
262
263 #define CM_REG_TDMA_POSITION 0x1C
264 #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
265 #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
266
267 /* byte */
268 #define CM_REG_MIXER0 0x20
269 #define CM_REG_SBVR 0x20 /* write: sb16 version */
270 #define CM_REG_DEV 0x20 /* read: hardware device version */
271
272 #define CM_REG_MIXER21 0x21
273 #define CM_UNKNOWN_21_MASK 0x78 /* ? */
274 #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
275 #define CM_PROINV 0x02 /* SBPro left/right channel switching */
276 #define CM_X_SB16 0x01 /* SB16 compatible */
277
278 #define CM_REG_SB16_DATA 0x22
279 #define CM_REG_SB16_ADDR 0x23
280
281 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
282 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
283 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
284 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
285
286 #define CM_REG_MIXER1 0x24
287 #define CM_FMMUTE 0x80 /* mute FM */
288 #define CM_FMMUTE_SHIFT 7
289 #define CM_WSMUTE 0x40 /* mute PCM */
290 #define CM_WSMUTE_SHIFT 6
291 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
292 #define CM_REAR2LIN_SHIFT 5
293 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
294 #define CM_REAR2FRONT_SHIFT 4
295 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
296 #define CM_WAVEINL_SHIFT 3
297 #define CM_WAVEINR 0x04 /* digical wave rec. right */
298 #define CM_WAVEINR_SHIFT 2
299 #define CM_X3DEN 0x02 /* 3D surround enable */
300 #define CM_X3DEN_SHIFT 1
301 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
302 #define CM_CDPLAY_SHIFT 0
303
304 #define CM_REG_MIXER2 0x25
305 #define CM_RAUXREN 0x80 /* AUX right capture */
306 #define CM_RAUXREN_SHIFT 7
307 #define CM_RAUXLEN 0x40 /* AUX left capture */
308 #define CM_RAUXLEN_SHIFT 6
309 #define CM_VAUXRM 0x20 /* AUX right mute */
310 #define CM_VAUXRM_SHIFT 5
311 #define CM_VAUXLM 0x10 /* AUX left mute */
312 #define CM_VAUXLM_SHIFT 4
313 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
314 #define CM_VADMIC_SHIFT 1
315 #define CM_MICGAINZ 0x01 /* mic boost */
316 #define CM_MICGAINZ_SHIFT 0
317
318 #define CM_REG_MIXER3 0x24
319 #define CM_REG_AUX_VOL 0x26
320 #define CM_VAUXL_MASK 0xf0
321 #define CM_VAUXR_MASK 0x0f
322
323 #define CM_REG_MISC 0x27
324 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
325 #define CM_XGPO1 0x20
326 // #define CM_XGPBIO 0x04
327 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
328 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
329 #define CM_SPDVALID 0x02 /* spdif input valid check */
330 #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
331
332 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
333 /*
334 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
335 * or identical with AC97 codec?
336 */
337 #define CM_REG_EXTERN_CODEC CM_REG_AC97
338
339 /*
340 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
341 */
342 #define CM_REG_MPU_PCI 0x40
343
344 /*
345 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
346 */
347 #define CM_REG_FM_PCI 0x50
348
349 /*
350 * access from SB-mixer port
351 */
352 #define CM_REG_EXTENT_IND 0xf0
353 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
354 #define CM_VPHONE_SHIFT 5
355 #define CM_VPHOM 0x10 /* Phone mute control */
356 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
357 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
358 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
359 #define CM_VADMIC3 0x01 /* Mic record boost */
360
361 /*
362 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
363 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
364 * unit (readonly?).
365 */
366 #define CM_REG_PLL 0xf8
367
368 /*
369 * extended registers
370 */
371 #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
372 #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
373 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
374 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
375
376 #define CM_REG_EXT_MISC 0x90
377 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
378 #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
379 #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
380 #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
381 #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
382 #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
383 #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
384 #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
385
386 /*
387 * size of i/o region
388 */
389 #define CM_EXTENT_CODEC 0x100
390 #define CM_EXTENT_MIDI 0x2
391 #define CM_EXTENT_SYNTH 0x4
392
393
394 /*
395 * channels for playback / capture
396 */
397 #define CM_CH_PLAY 0
398 #define CM_CH_CAPT 1
399
400 /*
401 * flags to check device open/close
402 */
403 #define CM_OPEN_NONE 0
404 #define CM_OPEN_CH_MASK 0x01
405 #define CM_OPEN_DAC 0x10
406 #define CM_OPEN_ADC 0x20
407 #define CM_OPEN_SPDIF 0x40
408 #define CM_OPEN_MCHAN 0x80
409 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
410 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
411 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
412 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
413 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
414 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
415
416
417 #if CM_CH_PLAY == 1
418 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
419 #define CM_PLAYBACK_SPDF CM_SPDF_1
420 #define CM_CAPTURE_SPDF CM_SPDF_0
421 #else
422 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
423 #define CM_PLAYBACK_SPDF CM_SPDF_0
424 #define CM_CAPTURE_SPDF CM_SPDF_1
425 #endif
426
427
428 /*
429 * driver data
430 */
431
432 struct cmipci_pcm {
433 struct snd_pcm_substream *substream;
434 u8 running; /* dac/adc running? */
435 u8 fmt; /* format bits */
436 u8 is_dac;
437 u8 needs_silencing;
438 unsigned int dma_size; /* in frames */
439 unsigned int shift;
440 unsigned int ch; /* channel (0/1) */
441 unsigned int offset; /* physical address of the buffer */
442 };
443
444 /* mixer elements toggled/resumed during ac3 playback */
445 struct cmipci_mixer_auto_switches {
446 const char *name; /* switch to toggle */
447 int toggle_on; /* value to change when ac3 mode */
448 };
449 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
450 {"PCM Playback Switch", 0},
451 {"IEC958 Output Switch", 1},
452 {"IEC958 Mix Analog", 0},
453 // {"IEC958 Out To DAC", 1}, // no longer used
454 {"IEC958 Loop", 0},
455 };
456 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
457
458 struct cmipci {
459 struct snd_card *card;
460
461 struct pci_dev *pci;
462 unsigned int device; /* device ID */
463 int irq;
464
465 unsigned long iobase;
466 unsigned int ctrl; /* FUNCTRL0 current value */
467
468 struct snd_pcm *pcm; /* DAC/ADC PCM */
469 struct snd_pcm *pcm2; /* 2nd DAC */
470 struct snd_pcm *pcm_spdif; /* SPDIF */
471
472 int chip_version;
473 int max_channels;
474 unsigned int can_ac3_sw: 1;
475 unsigned int can_ac3_hw: 1;
476 unsigned int can_multi_ch: 1;
477 unsigned int can_96k: 1; /* samplerate above 48k */
478 unsigned int do_soft_ac3: 1;
479
480 unsigned int spdif_playback_avail: 1; /* spdif ready? */
481 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
482 int spdif_counter; /* for software AC3 */
483
484 unsigned int dig_status;
485 unsigned int dig_pcm_status;
486
487 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
488
489 int opened[2]; /* open mode */
490 struct mutex open_mutex;
491
492 unsigned int mixer_insensitive: 1;
493 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
494 int mixer_res_status[CM_SAVED_MIXERS];
495
496 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
497
498 /* external MIDI */
499 struct snd_rawmidi *rmidi;
500
501 #ifdef SUPPORT_JOYSTICK
502 struct gameport *gameport;
503 #endif
504
505 spinlock_t reg_lock;
506
507 #ifdef CONFIG_PM
508 unsigned int saved_regs[0x20];
509 unsigned char saved_mixers[0x20];
510 #endif
511 };
512
513
514 /* read/write operations for dword register */
515 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
516 {
517 outl(data, cm->iobase + cmd);
518 }
519
520 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
521 {
522 return inl(cm->iobase + cmd);
523 }
524
525 /* read/write operations for word register */
526 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
527 {
528 outw(data, cm->iobase + cmd);
529 }
530
531 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
532 {
533 return inw(cm->iobase + cmd);
534 }
535
536 /* read/write operations for byte register */
537 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
538 {
539 outb(data, cm->iobase + cmd);
540 }
541
542 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
543 {
544 return inb(cm->iobase + cmd);
545 }
546
547 /* bit operations for dword register */
548 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
549 {
550 unsigned int val, oval;
551 val = oval = inl(cm->iobase + cmd);
552 val |= flag;
553 if (val == oval)
554 return 0;
555 outl(val, cm->iobase + cmd);
556 return 1;
557 }
558
559 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
560 {
561 unsigned int val, oval;
562 val = oval = inl(cm->iobase + cmd);
563 val &= ~flag;
564 if (val == oval)
565 return 0;
566 outl(val, cm->iobase + cmd);
567 return 1;
568 }
569
570 /* bit operations for byte register */
571 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
572 {
573 unsigned char val, oval;
574 val = oval = inb(cm->iobase + cmd);
575 val |= flag;
576 if (val == oval)
577 return 0;
578 outb(val, cm->iobase + cmd);
579 return 1;
580 }
581
582 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
583 {
584 unsigned char val, oval;
585 val = oval = inb(cm->iobase + cmd);
586 val &= ~flag;
587 if (val == oval)
588 return 0;
589 outb(val, cm->iobase + cmd);
590 return 1;
591 }
592
593
594 /*
595 * PCM interface
596 */
597
598 /*
599 * calculate frequency
600 */
601
602 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
603
604 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
605 {
606 unsigned int i;
607
608 for (i = 0; i < ARRAY_SIZE(rates); i++) {
609 if (rates[i] == rate)
610 return i;
611 }
612 snd_BUG();
613 return 0;
614 }
615
616 #ifdef USE_VAR48KRATE
617 /*
618 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
619 * does it this way .. maybe not. Never get any information from C-Media about
620 * that <werner@suse.de>.
621 */
622 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
623 {
624 unsigned int delta, tolerance;
625 int xm, xn, xr;
626
627 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
628 rate <<= 1;
629 *n = -1;
630 if (*r > 0xff)
631 goto out;
632 tolerance = rate*CM_TOLERANCE_RATE;
633
634 for (xn = (1+2); xn < (0x1f+2); xn++) {
635 for (xm = (1+2); xm < (0xff+2); xm++) {
636 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
637
638 if (xr < rate)
639 delta = rate - xr;
640 else
641 delta = xr - rate;
642
643 /*
644 * If we found one, remember this,
645 * and try to find a closer one
646 */
647 if (delta < tolerance) {
648 tolerance = delta;
649 *m = xm - 2;
650 *n = xn - 2;
651 }
652 }
653 }
654 out:
655 return (*n > -1);
656 }
657
658 /*
659 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
660 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
661 * at the register CM_REG_FUNCTRL1 (0x04).
662 * Problem: other ways are also possible (any information about that?)
663 */
664 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
665 {
666 unsigned int reg = CM_REG_PLL + slot;
667 /*
668 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
669 * for DSFC/ASFC (000 upto 111).
670 */
671
672 /* FIXME: Init (Do we've to set an other register first before programming?) */
673
674 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
675 snd_cmipci_write_b(cm, reg, rate>>8);
676 snd_cmipci_write_b(cm, reg, rate&0xff);
677
678 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
679 }
680 #endif /* USE_VAR48KRATE */
681
682 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
683 struct snd_pcm_hw_params *hw_params)
684 {
685 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
686 }
687
688 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
689 struct snd_pcm_hw_params *hw_params)
690 {
691 struct cmipci *cm = snd_pcm_substream_chip(substream);
692 if (params_channels(hw_params) > 2) {
693 mutex_lock(&cm->open_mutex);
694 if (cm->opened[CM_CH_PLAY]) {
695 mutex_unlock(&cm->open_mutex);
696 return -EBUSY;
697 }
698 /* reserve the channel A */
699 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
700 mutex_unlock(&cm->open_mutex);
701 }
702 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
703 }
704
705 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
706 {
707 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
708 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
709 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
710 udelay(10);
711 }
712
713 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
714 {
715 return snd_pcm_lib_free_pages(substream);
716 }
717
718
719 /*
720 */
721
722 static unsigned int hw_channels[] = {1, 2, 4, 6, 8};
723 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
724 .count = 3,
725 .list = hw_channels,
726 .mask = 0,
727 };
728 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
729 .count = 4,
730 .list = hw_channels,
731 .mask = 0,
732 };
733 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
734 .count = 5,
735 .list = hw_channels,
736 .mask = 0,
737 };
738
739 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
740 {
741 if (channels > 2) {
742 if (!cm->can_multi_ch || !rec->ch)
743 return -EINVAL;
744 if (rec->fmt != 0x03) /* stereo 16bit only */
745 return -EINVAL;
746 }
747
748 if (cm->can_multi_ch) {
749 spin_lock_irq(&cm->reg_lock);
750 if (channels > 2) {
751 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
752 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
753 } else {
754 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
755 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
756 }
757 if (channels == 8)
758 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
759 else
760 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
761 if (channels == 6) {
762 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
763 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
764 } else {
765 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
766 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
767 }
768 if (channels == 4)
769 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
770 else
771 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
772 spin_unlock_irq(&cm->reg_lock);
773 }
774 return 0;
775 }
776
777
778 /*
779 * prepare playback/capture channel
780 * channel to be used must have been set in rec->ch.
781 */
782 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
783 struct snd_pcm_substream *substream)
784 {
785 unsigned int reg, freq, freq_ext, val;
786 unsigned int period_size;
787 struct snd_pcm_runtime *runtime = substream->runtime;
788
789 rec->fmt = 0;
790 rec->shift = 0;
791 if (snd_pcm_format_width(runtime->format) >= 16) {
792 rec->fmt |= 0x02;
793 if (snd_pcm_format_width(runtime->format) > 16)
794 rec->shift++; /* 24/32bit */
795 }
796 if (runtime->channels > 1)
797 rec->fmt |= 0x01;
798 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
799 snd_printd("cannot set dac channels\n");
800 return -EINVAL;
801 }
802
803 rec->offset = runtime->dma_addr;
804 /* buffer and period sizes in frame */
805 rec->dma_size = runtime->buffer_size << rec->shift;
806 period_size = runtime->period_size << rec->shift;
807 if (runtime->channels > 2) {
808 /* multi-channels */
809 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
810 period_size = (period_size * runtime->channels) / 2;
811 }
812
813 spin_lock_irq(&cm->reg_lock);
814
815 /* set buffer address */
816 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
817 snd_cmipci_write(cm, reg, rec->offset);
818 /* program sample counts */
819 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
820 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
821 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
822
823 /* set adc/dac flag */
824 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
825 if (rec->is_dac)
826 cm->ctrl &= ~val;
827 else
828 cm->ctrl |= val;
829 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
830 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
831
832 /* set sample rate */
833 freq = 0;
834 freq_ext = 0;
835 if (runtime->rate > 48000)
836 switch (runtime->rate) {
837 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
838 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
839 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
840 default: snd_BUG(); break;
841 }
842 else
843 freq = snd_cmipci_rate_freq(runtime->rate);
844 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
845 if (rec->ch) {
846 val &= ~CM_DSFC_MASK;
847 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
848 } else {
849 val &= ~CM_ASFC_MASK;
850 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
851 }
852 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
853 //snd_printd("cmipci: functrl1 = %08x\n", val);
854
855 /* set format */
856 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
857 if (rec->ch) {
858 val &= ~CM_CH1FMT_MASK;
859 val |= rec->fmt << CM_CH1FMT_SHIFT;
860 } else {
861 val &= ~CM_CH0FMT_MASK;
862 val |= rec->fmt << CM_CH0FMT_SHIFT;
863 }
864 if (cm->can_96k) {
865 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
866 val |= freq_ext << (rec->ch * 2);
867 }
868 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
869 //snd_printd("cmipci: chformat = %08x\n", val);
870
871 if (!rec->is_dac && cm->chip_version) {
872 if (runtime->rate > 44100)
873 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
874 else
875 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
876 }
877
878 rec->running = 0;
879 spin_unlock_irq(&cm->reg_lock);
880
881 return 0;
882 }
883
884 /*
885 * PCM trigger/stop
886 */
887 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
888 int cmd)
889 {
890 unsigned int inthld, chen, reset, pause;
891 int result = 0;
892
893 inthld = CM_CH0_INT_EN << rec->ch;
894 chen = CM_CHEN0 << rec->ch;
895 reset = CM_RST_CH0 << rec->ch;
896 pause = CM_PAUSE0 << rec->ch;
897
898 spin_lock(&cm->reg_lock);
899 switch (cmd) {
900 case SNDRV_PCM_TRIGGER_START:
901 rec->running = 1;
902 /* set interrupt */
903 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
904 cm->ctrl |= chen;
905 /* enable channel */
906 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
907 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
908 break;
909 case SNDRV_PCM_TRIGGER_STOP:
910 rec->running = 0;
911 /* disable interrupt */
912 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
913 /* reset */
914 cm->ctrl &= ~chen;
915 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
916 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
917 rec->needs_silencing = rec->is_dac;
918 break;
919 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
920 case SNDRV_PCM_TRIGGER_SUSPEND:
921 cm->ctrl |= pause;
922 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
923 break;
924 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
925 case SNDRV_PCM_TRIGGER_RESUME:
926 cm->ctrl &= ~pause;
927 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
928 break;
929 default:
930 result = -EINVAL;
931 break;
932 }
933 spin_unlock(&cm->reg_lock);
934 return result;
935 }
936
937 /*
938 * return the current pointer
939 */
940 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
941 struct snd_pcm_substream *substream)
942 {
943 size_t ptr;
944 unsigned int reg;
945 if (!rec->running)
946 return 0;
947 #if 1 // this seems better..
948 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
949 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
950 ptr >>= rec->shift;
951 #else
952 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
953 ptr = snd_cmipci_read(cm, reg) - rec->offset;
954 ptr = bytes_to_frames(substream->runtime, ptr);
955 #endif
956 if (substream->runtime->channels > 2)
957 ptr = (ptr * 2) / substream->runtime->channels;
958 return ptr;
959 }
960
961 /*
962 * playback
963 */
964
965 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
966 int cmd)
967 {
968 struct cmipci *cm = snd_pcm_substream_chip(substream);
969 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
970 }
971
972 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
973 {
974 struct cmipci *cm = snd_pcm_substream_chip(substream);
975 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
976 }
977
978
979
980 /*
981 * capture
982 */
983
984 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
985 int cmd)
986 {
987 struct cmipci *cm = snd_pcm_substream_chip(substream);
988 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
989 }
990
991 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
992 {
993 struct cmipci *cm = snd_pcm_substream_chip(substream);
994 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
995 }
996
997
998 /*
999 * hw preparation for spdif
1000 */
1001
1002 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
1003 struct snd_ctl_elem_info *uinfo)
1004 {
1005 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1006 uinfo->count = 1;
1007 return 0;
1008 }
1009
1010 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1011 struct snd_ctl_elem_value *ucontrol)
1012 {
1013 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1014 int i;
1015
1016 spin_lock_irq(&chip->reg_lock);
1017 for (i = 0; i < 4; i++)
1018 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1019 spin_unlock_irq(&chip->reg_lock);
1020 return 0;
1021 }
1022
1023 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1024 struct snd_ctl_elem_value *ucontrol)
1025 {
1026 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1027 int i, change;
1028 unsigned int val;
1029
1030 val = 0;
1031 spin_lock_irq(&chip->reg_lock);
1032 for (i = 0; i < 4; i++)
1033 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1034 change = val != chip->dig_status;
1035 chip->dig_status = val;
1036 spin_unlock_irq(&chip->reg_lock);
1037 return change;
1038 }
1039
1040 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
1041 {
1042 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1043 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1044 .info = snd_cmipci_spdif_default_info,
1045 .get = snd_cmipci_spdif_default_get,
1046 .put = snd_cmipci_spdif_default_put
1047 };
1048
1049 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1050 struct snd_ctl_elem_info *uinfo)
1051 {
1052 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1053 uinfo->count = 1;
1054 return 0;
1055 }
1056
1057 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1058 struct snd_ctl_elem_value *ucontrol)
1059 {
1060 ucontrol->value.iec958.status[0] = 0xff;
1061 ucontrol->value.iec958.status[1] = 0xff;
1062 ucontrol->value.iec958.status[2] = 0xff;
1063 ucontrol->value.iec958.status[3] = 0xff;
1064 return 0;
1065 }
1066
1067 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1068 {
1069 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1070 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1071 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1072 .info = snd_cmipci_spdif_mask_info,
1073 .get = snd_cmipci_spdif_mask_get,
1074 };
1075
1076 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1077 struct snd_ctl_elem_info *uinfo)
1078 {
1079 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1080 uinfo->count = 1;
1081 return 0;
1082 }
1083
1084 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1085 struct snd_ctl_elem_value *ucontrol)
1086 {
1087 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1088 int i;
1089
1090 spin_lock_irq(&chip->reg_lock);
1091 for (i = 0; i < 4; i++)
1092 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1093 spin_unlock_irq(&chip->reg_lock);
1094 return 0;
1095 }
1096
1097 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1098 struct snd_ctl_elem_value *ucontrol)
1099 {
1100 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1101 int i, change;
1102 unsigned int val;
1103
1104 val = 0;
1105 spin_lock_irq(&chip->reg_lock);
1106 for (i = 0; i < 4; i++)
1107 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1108 change = val != chip->dig_pcm_status;
1109 chip->dig_pcm_status = val;
1110 spin_unlock_irq(&chip->reg_lock);
1111 return change;
1112 }
1113
1114 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1115 {
1116 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1117 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1118 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1119 .info = snd_cmipci_spdif_stream_info,
1120 .get = snd_cmipci_spdif_stream_get,
1121 .put = snd_cmipci_spdif_stream_put
1122 };
1123
1124 /*
1125 */
1126
1127 /* save mixer setting and mute for AC3 playback */
1128 static int save_mixer_state(struct cmipci *cm)
1129 {
1130 if (! cm->mixer_insensitive) {
1131 struct snd_ctl_elem_value *val;
1132 unsigned int i;
1133
1134 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1135 if (!val)
1136 return -ENOMEM;
1137 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1138 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1139 if (ctl) {
1140 int event;
1141 memset(val, 0, sizeof(*val));
1142 ctl->get(ctl, val);
1143 cm->mixer_res_status[i] = val->value.integer.value[0];
1144 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1145 event = SNDRV_CTL_EVENT_MASK_INFO;
1146 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1147 ctl->put(ctl, val); /* toggle */
1148 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1149 }
1150 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1151 snd_ctl_notify(cm->card, event, &ctl->id);
1152 }
1153 }
1154 kfree(val);
1155 cm->mixer_insensitive = 1;
1156 }
1157 return 0;
1158 }
1159
1160
1161 /* restore the previously saved mixer status */
1162 static void restore_mixer_state(struct cmipci *cm)
1163 {
1164 if (cm->mixer_insensitive) {
1165 struct snd_ctl_elem_value *val;
1166 unsigned int i;
1167
1168 val = kmalloc(sizeof(*val), GFP_KERNEL);
1169 if (!val)
1170 return;
1171 cm->mixer_insensitive = 0; /* at first clear this;
1172 otherwise the changes will be ignored */
1173 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1174 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1175 if (ctl) {
1176 int event;
1177
1178 memset(val, 0, sizeof(*val));
1179 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1180 ctl->get(ctl, val);
1181 event = SNDRV_CTL_EVENT_MASK_INFO;
1182 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1183 val->value.integer.value[0] = cm->mixer_res_status[i];
1184 ctl->put(ctl, val);
1185 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1186 }
1187 snd_ctl_notify(cm->card, event, &ctl->id);
1188 }
1189 }
1190 kfree(val);
1191 }
1192 }
1193
1194 /* spinlock held! */
1195 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1196 {
1197 if (do_ac3) {
1198 /* AC3EN for 037 */
1199 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1200 /* AC3EN for 039 */
1201 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1202
1203 if (cm->can_ac3_hw) {
1204 /* SPD24SEL for 037, 0x02 */
1205 /* SPD24SEL for 039, 0x20, but cannot be set */
1206 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1207 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1208 } else { /* can_ac3_sw */
1209 /* SPD32SEL for 037 & 039, 0x20 */
1210 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1211 /* set 176K sample rate to fix 033 HW bug */
1212 if (cm->chip_version == 33) {
1213 if (rate >= 48000) {
1214 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1215 } else {
1216 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1217 }
1218 }
1219 }
1220
1221 } else {
1222 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1223 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1224
1225 if (cm->can_ac3_hw) {
1226 /* chip model >= 37 */
1227 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1228 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1229 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1230 } else {
1231 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1232 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1233 }
1234 } else {
1235 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1236 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1237 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1238 }
1239 }
1240 }
1241
1242 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1243 {
1244 int rate, err;
1245
1246 rate = subs->runtime->rate;
1247
1248 if (up && do_ac3)
1249 if ((err = save_mixer_state(cm)) < 0)
1250 return err;
1251
1252 spin_lock_irq(&cm->reg_lock);
1253 cm->spdif_playback_avail = up;
1254 if (up) {
1255 /* they are controlled via "IEC958 Output Switch" */
1256 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1257 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1258 if (cm->spdif_playback_enabled)
1259 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1260 setup_ac3(cm, subs, do_ac3, rate);
1261
1262 if (rate == 48000 || rate == 96000)
1263 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1264 else
1265 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1266 if (rate > 48000)
1267 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1268 else
1269 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1270 } else {
1271 /* they are controlled via "IEC958 Output Switch" */
1272 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1273 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1274 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1275 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1276 setup_ac3(cm, subs, 0, 0);
1277 }
1278 spin_unlock_irq(&cm->reg_lock);
1279 return 0;
1280 }
1281
1282
1283 /*
1284 * preparation
1285 */
1286
1287 /* playback - enable spdif only on the certain condition */
1288 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1289 {
1290 struct cmipci *cm = snd_pcm_substream_chip(substream);
1291 int rate = substream->runtime->rate;
1292 int err, do_spdif, do_ac3 = 0;
1293
1294 do_spdif = (rate >= 44100 && rate <= 96000 &&
1295 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1296 substream->runtime->channels == 2);
1297 if (do_spdif && cm->can_ac3_hw)
1298 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1299 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1300 return err;
1301 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1302 }
1303
1304 /* playback (via device #2) - enable spdif always */
1305 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1306 {
1307 struct cmipci *cm = snd_pcm_substream_chip(substream);
1308 int err, do_ac3;
1309
1310 if (cm->can_ac3_hw)
1311 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1312 else
1313 do_ac3 = 1; /* doesn't matter */
1314 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1315 return err;
1316 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1317 }
1318
1319 /*
1320 * Apparently, the samples last played on channel A stay in some buffer, even
1321 * after the channel is reset, and get added to the data for the rear DACs when
1322 * playing a multichannel stream on channel B. This is likely to generate
1323 * wraparounds and thus distortions.
1324 * To avoid this, we play at least one zero sample after the actual stream has
1325 * stopped.
1326 */
1327 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1328 {
1329 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1330 unsigned int reg, val;
1331
1332 if (rec->needs_silencing && runtime && runtime->dma_area) {
1333 /* set up a small silence buffer */
1334 memset(runtime->dma_area, 0, PAGE_SIZE);
1335 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1336 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1337 snd_cmipci_write(cm, reg, val);
1338
1339 /* configure for 16 bits, 2 channels, 8 kHz */
1340 if (runtime->channels > 2)
1341 set_dac_channels(cm, rec, 2);
1342 spin_lock_irq(&cm->reg_lock);
1343 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1344 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1345 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1346 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1347 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1348 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1349 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1350 if (cm->can_96k)
1351 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1352 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1353
1354 /* start stream (we don't need interrupts) */
1355 cm->ctrl |= CM_CHEN0 << rec->ch;
1356 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1357 spin_unlock_irq(&cm->reg_lock);
1358
1359 msleep(1);
1360
1361 /* stop and reset stream */
1362 spin_lock_irq(&cm->reg_lock);
1363 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1364 val = CM_RST_CH0 << rec->ch;
1365 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1366 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1367 spin_unlock_irq(&cm->reg_lock);
1368
1369 rec->needs_silencing = 0;
1370 }
1371 }
1372
1373 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1374 {
1375 struct cmipci *cm = snd_pcm_substream_chip(substream);
1376 setup_spdif_playback(cm, substream, 0, 0);
1377 restore_mixer_state(cm);
1378 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1379 return snd_cmipci_hw_free(substream);
1380 }
1381
1382 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1383 {
1384 struct cmipci *cm = snd_pcm_substream_chip(substream);
1385 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1386 return snd_cmipci_hw_free(substream);
1387 }
1388
1389 /* capture */
1390 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1391 {
1392 struct cmipci *cm = snd_pcm_substream_chip(substream);
1393 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1394 }
1395
1396 /* capture with spdif (via device #2) */
1397 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1398 {
1399 struct cmipci *cm = snd_pcm_substream_chip(substream);
1400
1401 spin_lock_irq(&cm->reg_lock);
1402 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1403 if (cm->can_96k) {
1404 if (substream->runtime->rate > 48000)
1405 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1406 else
1407 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1408 }
1409 if (snd_pcm_format_width(substream->runtime->format) > 16)
1410 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1411 else
1412 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1413
1414 spin_unlock_irq(&cm->reg_lock);
1415
1416 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1417 }
1418
1419 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1420 {
1421 struct cmipci *cm = snd_pcm_substream_chip(subs);
1422
1423 spin_lock_irq(&cm->reg_lock);
1424 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1425 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1426 spin_unlock_irq(&cm->reg_lock);
1427
1428 return snd_cmipci_hw_free(subs);
1429 }
1430
1431
1432 /*
1433 * interrupt handler
1434 */
1435 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1436 {
1437 struct cmipci *cm = dev_id;
1438 unsigned int status, mask = 0;
1439
1440 /* fastpath out, to ease interrupt sharing */
1441 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1442 if (!(status & CM_INTR))
1443 return IRQ_NONE;
1444
1445 /* acknowledge interrupt */
1446 spin_lock(&cm->reg_lock);
1447 if (status & CM_CHINT0)
1448 mask |= CM_CH0_INT_EN;
1449 if (status & CM_CHINT1)
1450 mask |= CM_CH1_INT_EN;
1451 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1452 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1453 spin_unlock(&cm->reg_lock);
1454
1455 if (cm->rmidi && (status & CM_UARTINT))
1456 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1457
1458 if (cm->pcm) {
1459 if ((status & CM_CHINT0) && cm->channel[0].running)
1460 snd_pcm_period_elapsed(cm->channel[0].substream);
1461 if ((status & CM_CHINT1) && cm->channel[1].running)
1462 snd_pcm_period_elapsed(cm->channel[1].substream);
1463 }
1464 return IRQ_HANDLED;
1465 }
1466
1467 /*
1468 * h/w infos
1469 */
1470
1471 /* playback on channel A */
1472 static struct snd_pcm_hardware snd_cmipci_playback =
1473 {
1474 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1475 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1476 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1477 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1478 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1479 .rate_min = 5512,
1480 .rate_max = 48000,
1481 .channels_min = 1,
1482 .channels_max = 2,
1483 .buffer_bytes_max = (128*1024),
1484 .period_bytes_min = 64,
1485 .period_bytes_max = (128*1024),
1486 .periods_min = 2,
1487 .periods_max = 1024,
1488 .fifo_size = 0,
1489 };
1490
1491 /* capture on channel B */
1492 static struct snd_pcm_hardware snd_cmipci_capture =
1493 {
1494 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1495 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1496 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1497 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1498 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1499 .rate_min = 5512,
1500 .rate_max = 48000,
1501 .channels_min = 1,
1502 .channels_max = 2,
1503 .buffer_bytes_max = (128*1024),
1504 .period_bytes_min = 64,
1505 .period_bytes_max = (128*1024),
1506 .periods_min = 2,
1507 .periods_max = 1024,
1508 .fifo_size = 0,
1509 };
1510
1511 /* playback on channel B - stereo 16bit only? */
1512 static struct snd_pcm_hardware snd_cmipci_playback2 =
1513 {
1514 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1515 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1516 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1517 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1518 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1519 .rate_min = 5512,
1520 .rate_max = 48000,
1521 .channels_min = 2,
1522 .channels_max = 2,
1523 .buffer_bytes_max = (128*1024),
1524 .period_bytes_min = 64,
1525 .period_bytes_max = (128*1024),
1526 .periods_min = 2,
1527 .periods_max = 1024,
1528 .fifo_size = 0,
1529 };
1530
1531 /* spdif playback on channel A */
1532 static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1533 {
1534 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1535 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1536 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1537 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1538 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1539 .rate_min = 44100,
1540 .rate_max = 48000,
1541 .channels_min = 2,
1542 .channels_max = 2,
1543 .buffer_bytes_max = (128*1024),
1544 .period_bytes_min = 64,
1545 .period_bytes_max = (128*1024),
1546 .periods_min = 2,
1547 .periods_max = 1024,
1548 .fifo_size = 0,
1549 };
1550
1551 /* spdif playback on channel A (32bit, IEC958 subframes) */
1552 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1553 {
1554 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1555 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1556 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1557 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1558 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1559 .rate_min = 44100,
1560 .rate_max = 48000,
1561 .channels_min = 2,
1562 .channels_max = 2,
1563 .buffer_bytes_max = (128*1024),
1564 .period_bytes_min = 64,
1565 .period_bytes_max = (128*1024),
1566 .periods_min = 2,
1567 .periods_max = 1024,
1568 .fifo_size = 0,
1569 };
1570
1571 /* spdif capture on channel B */
1572 static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1573 {
1574 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1575 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1576 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1577 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1578 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1579 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1580 .rate_min = 44100,
1581 .rate_max = 48000,
1582 .channels_min = 2,
1583 .channels_max = 2,
1584 .buffer_bytes_max = (128*1024),
1585 .period_bytes_min = 64,
1586 .period_bytes_max = (128*1024),
1587 .periods_min = 2,
1588 .periods_max = 1024,
1589 .fifo_size = 0,
1590 };
1591
1592 static unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1593 32000, 44100, 48000, 88200, 96000, 128000 };
1594 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1595 .count = ARRAY_SIZE(rate_constraints),
1596 .list = rate_constraints,
1597 .mask = 0,
1598 };
1599
1600 /*
1601 * check device open/close
1602 */
1603 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1604 {
1605 int ch = mode & CM_OPEN_CH_MASK;
1606
1607 /* FIXME: a file should wait until the device becomes free
1608 * when it's opened on blocking mode. however, since the current
1609 * pcm framework doesn't pass file pointer before actually opened,
1610 * we can't know whether blocking mode or not in open callback..
1611 */
1612 mutex_lock(&cm->open_mutex);
1613 if (cm->opened[ch]) {
1614 mutex_unlock(&cm->open_mutex);
1615 return -EBUSY;
1616 }
1617 cm->opened[ch] = mode;
1618 cm->channel[ch].substream = subs;
1619 if (! (mode & CM_OPEN_DAC)) {
1620 /* disable dual DAC mode */
1621 cm->channel[ch].is_dac = 0;
1622 spin_lock_irq(&cm->reg_lock);
1623 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1624 spin_unlock_irq(&cm->reg_lock);
1625 }
1626 mutex_unlock(&cm->open_mutex);
1627 return 0;
1628 }
1629
1630 static void close_device_check(struct cmipci *cm, int mode)
1631 {
1632 int ch = mode & CM_OPEN_CH_MASK;
1633
1634 mutex_lock(&cm->open_mutex);
1635 if (cm->opened[ch] == mode) {
1636 if (cm->channel[ch].substream) {
1637 snd_cmipci_ch_reset(cm, ch);
1638 cm->channel[ch].running = 0;
1639 cm->channel[ch].substream = NULL;
1640 }
1641 cm->opened[ch] = 0;
1642 if (! cm->channel[ch].is_dac) {
1643 /* enable dual DAC mode again */
1644 cm->channel[ch].is_dac = 1;
1645 spin_lock_irq(&cm->reg_lock);
1646 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1647 spin_unlock_irq(&cm->reg_lock);
1648 }
1649 }
1650 mutex_unlock(&cm->open_mutex);
1651 }
1652
1653 /*
1654 */
1655
1656 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1657 {
1658 struct cmipci *cm = snd_pcm_substream_chip(substream);
1659 struct snd_pcm_runtime *runtime = substream->runtime;
1660 int err;
1661
1662 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1663 return err;
1664 runtime->hw = snd_cmipci_playback;
1665 if (cm->chip_version == 68) {
1666 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1667 SNDRV_PCM_RATE_96000;
1668 runtime->hw.rate_max = 96000;
1669 } else if (cm->chip_version == 55) {
1670 err = snd_pcm_hw_constraint_list(runtime, 0,
1671 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1672 if (err < 0)
1673 return err;
1674 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1675 runtime->hw.rate_max = 128000;
1676 }
1677 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1678 cm->dig_pcm_status = cm->dig_status;
1679 return 0;
1680 }
1681
1682 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1683 {
1684 struct cmipci *cm = snd_pcm_substream_chip(substream);
1685 struct snd_pcm_runtime *runtime = substream->runtime;
1686 int err;
1687
1688 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1689 return err;
1690 runtime->hw = snd_cmipci_capture;
1691 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1692 runtime->hw.rate_min = 41000;
1693 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1694 } else if (cm->chip_version == 55) {
1695 err = snd_pcm_hw_constraint_list(runtime, 0,
1696 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1697 if (err < 0)
1698 return err;
1699 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1700 runtime->hw.rate_max = 128000;
1701 }
1702 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1703 return 0;
1704 }
1705
1706 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1707 {
1708 struct cmipci *cm = snd_pcm_substream_chip(substream);
1709 struct snd_pcm_runtime *runtime = substream->runtime;
1710 int err;
1711
1712 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1713 return err;
1714 runtime->hw = snd_cmipci_playback2;
1715 mutex_lock(&cm->open_mutex);
1716 if (! cm->opened[CM_CH_PLAY]) {
1717 if (cm->can_multi_ch) {
1718 runtime->hw.channels_max = cm->max_channels;
1719 if (cm->max_channels == 4)
1720 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1721 else if (cm->max_channels == 6)
1722 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1723 else if (cm->max_channels == 8)
1724 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1725 }
1726 }
1727 mutex_unlock(&cm->open_mutex);
1728 if (cm->chip_version == 68) {
1729 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1730 SNDRV_PCM_RATE_96000;
1731 runtime->hw.rate_max = 96000;
1732 } else if (cm->chip_version == 55) {
1733 err = snd_pcm_hw_constraint_list(runtime, 0,
1734 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1735 if (err < 0)
1736 return err;
1737 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1738 runtime->hw.rate_max = 128000;
1739 }
1740 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1741 return 0;
1742 }
1743
1744 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1745 {
1746 struct cmipci *cm = snd_pcm_substream_chip(substream);
1747 struct snd_pcm_runtime *runtime = substream->runtime;
1748 int err;
1749
1750 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1751 return err;
1752 if (cm->can_ac3_hw) {
1753 runtime->hw = snd_cmipci_playback_spdif;
1754 if (cm->chip_version >= 37) {
1755 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1756 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1757 }
1758 if (cm->can_96k) {
1759 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1760 SNDRV_PCM_RATE_96000;
1761 runtime->hw.rate_max = 96000;
1762 }
1763 } else {
1764 runtime->hw = snd_cmipci_playback_iec958_subframe;
1765 }
1766 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1767 cm->dig_pcm_status = cm->dig_status;
1768 return 0;
1769 }
1770
1771 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1772 {
1773 struct cmipci *cm = snd_pcm_substream_chip(substream);
1774 struct snd_pcm_runtime *runtime = substream->runtime;
1775 int err;
1776
1777 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1778 return err;
1779 runtime->hw = snd_cmipci_capture_spdif;
1780 if (cm->can_96k && !(cm->chip_version == 68)) {
1781 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1782 SNDRV_PCM_RATE_96000;
1783 runtime->hw.rate_max = 96000;
1784 }
1785 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1786 return 0;
1787 }
1788
1789
1790 /*
1791 */
1792
1793 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1794 {
1795 struct cmipci *cm = snd_pcm_substream_chip(substream);
1796 close_device_check(cm, CM_OPEN_PLAYBACK);
1797 return 0;
1798 }
1799
1800 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1801 {
1802 struct cmipci *cm = snd_pcm_substream_chip(substream);
1803 close_device_check(cm, CM_OPEN_CAPTURE);
1804 return 0;
1805 }
1806
1807 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1808 {
1809 struct cmipci *cm = snd_pcm_substream_chip(substream);
1810 close_device_check(cm, CM_OPEN_PLAYBACK2);
1811 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1812 return 0;
1813 }
1814
1815 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1816 {
1817 struct cmipci *cm = snd_pcm_substream_chip(substream);
1818 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1819 return 0;
1820 }
1821
1822 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1823 {
1824 struct cmipci *cm = snd_pcm_substream_chip(substream);
1825 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1826 return 0;
1827 }
1828
1829
1830 /*
1831 */
1832
1833 static struct snd_pcm_ops snd_cmipci_playback_ops = {
1834 .open = snd_cmipci_playback_open,
1835 .close = snd_cmipci_playback_close,
1836 .ioctl = snd_pcm_lib_ioctl,
1837 .hw_params = snd_cmipci_hw_params,
1838 .hw_free = snd_cmipci_playback_hw_free,
1839 .prepare = snd_cmipci_playback_prepare,
1840 .trigger = snd_cmipci_playback_trigger,
1841 .pointer = snd_cmipci_playback_pointer,
1842 };
1843
1844 static struct snd_pcm_ops snd_cmipci_capture_ops = {
1845 .open = snd_cmipci_capture_open,
1846 .close = snd_cmipci_capture_close,
1847 .ioctl = snd_pcm_lib_ioctl,
1848 .hw_params = snd_cmipci_hw_params,
1849 .hw_free = snd_cmipci_hw_free,
1850 .prepare = snd_cmipci_capture_prepare,
1851 .trigger = snd_cmipci_capture_trigger,
1852 .pointer = snd_cmipci_capture_pointer,
1853 };
1854
1855 static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1856 .open = snd_cmipci_playback2_open,
1857 .close = snd_cmipci_playback2_close,
1858 .ioctl = snd_pcm_lib_ioctl,
1859 .hw_params = snd_cmipci_playback2_hw_params,
1860 .hw_free = snd_cmipci_playback2_hw_free,
1861 .prepare = snd_cmipci_capture_prepare, /* channel B */
1862 .trigger = snd_cmipci_capture_trigger, /* channel B */
1863 .pointer = snd_cmipci_capture_pointer, /* channel B */
1864 };
1865
1866 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1867 .open = snd_cmipci_playback_spdif_open,
1868 .close = snd_cmipci_playback_spdif_close,
1869 .ioctl = snd_pcm_lib_ioctl,
1870 .hw_params = snd_cmipci_hw_params,
1871 .hw_free = snd_cmipci_playback_hw_free,
1872 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1873 .trigger = snd_cmipci_playback_trigger,
1874 .pointer = snd_cmipci_playback_pointer,
1875 };
1876
1877 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1878 .open = snd_cmipci_capture_spdif_open,
1879 .close = snd_cmipci_capture_spdif_close,
1880 .ioctl = snd_pcm_lib_ioctl,
1881 .hw_params = snd_cmipci_hw_params,
1882 .hw_free = snd_cmipci_capture_spdif_hw_free,
1883 .prepare = snd_cmipci_capture_spdif_prepare,
1884 .trigger = snd_cmipci_capture_trigger,
1885 .pointer = snd_cmipci_capture_pointer,
1886 };
1887
1888
1889 /*
1890 */
1891
1892 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1893 {
1894 struct snd_pcm *pcm;
1895 int err;
1896
1897 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1898 if (err < 0)
1899 return err;
1900
1901 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1902 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1903
1904 pcm->private_data = cm;
1905 pcm->info_flags = 0;
1906 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1907 cm->pcm = pcm;
1908
1909 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1910 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1911
1912 return 0;
1913 }
1914
1915 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1916 {
1917 struct snd_pcm *pcm;
1918 int err;
1919
1920 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1921 if (err < 0)
1922 return err;
1923
1924 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1925
1926 pcm->private_data = cm;
1927 pcm->info_flags = 0;
1928 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1929 cm->pcm2 = pcm;
1930
1931 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1932 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1933
1934 return 0;
1935 }
1936
1937 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1938 {
1939 struct snd_pcm *pcm;
1940 int err;
1941
1942 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1943 if (err < 0)
1944 return err;
1945
1946 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1947 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1948
1949 pcm->private_data = cm;
1950 pcm->info_flags = 0;
1951 strcpy(pcm->name, "C-Media PCI IEC958");
1952 cm->pcm_spdif = pcm;
1953
1954 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1955 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1956
1957 return 0;
1958 }
1959
1960 /*
1961 * mixer interface:
1962 * - CM8338/8738 has a compatible mixer interface with SB16, but
1963 * lack of some elements like tone control, i/o gain and AGC.
1964 * - Access to native registers:
1965 * - A 3D switch
1966 * - Output mute switches
1967 */
1968
1969 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1970 {
1971 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1972 outb(data, s->iobase + CM_REG_SB16_DATA);
1973 }
1974
1975 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1976 {
1977 unsigned char v;
1978
1979 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1980 v = inb(s->iobase + CM_REG_SB16_DATA);
1981 return v;
1982 }
1983
1984 /*
1985 * general mixer element
1986 */
1987 struct cmipci_sb_reg {
1988 unsigned int left_reg, right_reg;
1989 unsigned int left_shift, right_shift;
1990 unsigned int mask;
1991 unsigned int invert: 1;
1992 unsigned int stereo: 1;
1993 };
1994
1995 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1996 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1997
1998 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1999 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2000 .info = snd_cmipci_info_volume, \
2001 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
2002 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
2003 }
2004
2005 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2006 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2007 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2008 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2009
2010 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2011 {
2012 r->left_reg = val & 0xff;
2013 r->right_reg = (val >> 8) & 0xff;
2014 r->left_shift = (val >> 16) & 0x07;
2015 r->right_shift = (val >> 19) & 0x07;
2016 r->invert = (val >> 22) & 1;
2017 r->stereo = (val >> 23) & 1;
2018 r->mask = (val >> 24) & 0xff;
2019 }
2020
2021 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2022 struct snd_ctl_elem_info *uinfo)
2023 {
2024 struct cmipci_sb_reg reg;
2025
2026 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2027 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2028 uinfo->count = reg.stereo + 1;
2029 uinfo->value.integer.min = 0;
2030 uinfo->value.integer.max = reg.mask;
2031 return 0;
2032 }
2033
2034 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2035 struct snd_ctl_elem_value *ucontrol)
2036 {
2037 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2038 struct cmipci_sb_reg reg;
2039 int val;
2040
2041 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2042 spin_lock_irq(&cm->reg_lock);
2043 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2044 if (reg.invert)
2045 val = reg.mask - val;
2046 ucontrol->value.integer.value[0] = val;
2047 if (reg.stereo) {
2048 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2049 if (reg.invert)
2050 val = reg.mask - val;
2051 ucontrol->value.integer.value[1] = val;
2052 }
2053 spin_unlock_irq(&cm->reg_lock);
2054 return 0;
2055 }
2056
2057 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2058 struct snd_ctl_elem_value *ucontrol)
2059 {
2060 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2061 struct cmipci_sb_reg reg;
2062 int change;
2063 int left, right, oleft, oright;
2064
2065 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2066 left = ucontrol->value.integer.value[0] & reg.mask;
2067 if (reg.invert)
2068 left = reg.mask - left;
2069 left <<= reg.left_shift;
2070 if (reg.stereo) {
2071 right = ucontrol->value.integer.value[1] & reg.mask;
2072 if (reg.invert)
2073 right = reg.mask - right;
2074 right <<= reg.right_shift;
2075 } else
2076 right = 0;
2077 spin_lock_irq(&cm->reg_lock);
2078 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2079 left |= oleft & ~(reg.mask << reg.left_shift);
2080 change = left != oleft;
2081 if (reg.stereo) {
2082 if (reg.left_reg != reg.right_reg) {
2083 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2084 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2085 } else
2086 oright = left;
2087 right |= oright & ~(reg.mask << reg.right_shift);
2088 change |= right != oright;
2089 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2090 } else
2091 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2092 spin_unlock_irq(&cm->reg_lock);
2093 return change;
2094 }
2095
2096 /*
2097 * input route (left,right) -> (left,right)
2098 */
2099 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2100 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2101 .info = snd_cmipci_info_input_sw, \
2102 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2103 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2104 }
2105
2106 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2107 struct snd_ctl_elem_info *uinfo)
2108 {
2109 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2110 uinfo->count = 4;
2111 uinfo->value.integer.min = 0;
2112 uinfo->value.integer.max = 1;
2113 return 0;
2114 }
2115
2116 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2117 struct snd_ctl_elem_value *ucontrol)
2118 {
2119 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2120 struct cmipci_sb_reg reg;
2121 int val1, val2;
2122
2123 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2124 spin_lock_irq(&cm->reg_lock);
2125 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2126 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2127 spin_unlock_irq(&cm->reg_lock);
2128 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2129 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2130 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2131 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2132 return 0;
2133 }
2134
2135 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2136 struct snd_ctl_elem_value *ucontrol)
2137 {
2138 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2139 struct cmipci_sb_reg reg;
2140 int change;
2141 int val1, val2, oval1, oval2;
2142
2143 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2144 spin_lock_irq(&cm->reg_lock);
2145 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2146 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2147 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2148 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2149 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2150 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2151 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2152 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2153 change = val1 != oval1 || val2 != oval2;
2154 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2155 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2156 spin_unlock_irq(&cm->reg_lock);
2157 return change;
2158 }
2159
2160 /*
2161 * native mixer switches/volumes
2162 */
2163
2164 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2165 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2166 .info = snd_cmipci_info_native_mixer, \
2167 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2168 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2169 }
2170
2171 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2172 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2173 .info = snd_cmipci_info_native_mixer, \
2174 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2175 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2176 }
2177
2178 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2179 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2180 .info = snd_cmipci_info_native_mixer, \
2181 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2182 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2183 }
2184
2185 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2186 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2187 .info = snd_cmipci_info_native_mixer, \
2188 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2189 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2190 }
2191
2192 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2193 struct snd_ctl_elem_info *uinfo)
2194 {
2195 struct cmipci_sb_reg reg;
2196
2197 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2198 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2199 uinfo->count = reg.stereo + 1;
2200 uinfo->value.integer.min = 0;
2201 uinfo->value.integer.max = reg.mask;
2202 return 0;
2203
2204 }
2205
2206 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2207 struct snd_ctl_elem_value *ucontrol)
2208 {
2209 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2210 struct cmipci_sb_reg reg;
2211 unsigned char oreg, val;
2212
2213 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2214 spin_lock_irq(&cm->reg_lock);
2215 oreg = inb(cm->iobase + reg.left_reg);
2216 val = (oreg >> reg.left_shift) & reg.mask;
2217 if (reg.invert)
2218 val = reg.mask - val;
2219 ucontrol->value.integer.value[0] = val;
2220 if (reg.stereo) {
2221 val = (oreg >> reg.right_shift) & reg.mask;
2222 if (reg.invert)
2223 val = reg.mask - val;
2224 ucontrol->value.integer.value[1] = val;
2225 }
2226 spin_unlock_irq(&cm->reg_lock);
2227 return 0;
2228 }
2229
2230 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2231 struct snd_ctl_elem_value *ucontrol)
2232 {
2233 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2234 struct cmipci_sb_reg reg;
2235 unsigned char oreg, nreg, val;
2236
2237 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2238 spin_lock_irq(&cm->reg_lock);
2239 oreg = inb(cm->iobase + reg.left_reg);
2240 val = ucontrol->value.integer.value[0] & reg.mask;
2241 if (reg.invert)
2242 val = reg.mask - val;
2243 nreg = oreg & ~(reg.mask << reg.left_shift);
2244 nreg |= (val << reg.left_shift);
2245 if (reg.stereo) {
2246 val = ucontrol->value.integer.value[1] & reg.mask;
2247 if (reg.invert)
2248 val = reg.mask - val;
2249 nreg &= ~(reg.mask << reg.right_shift);
2250 nreg |= (val << reg.right_shift);
2251 }
2252 outb(nreg, cm->iobase + reg.left_reg);
2253 spin_unlock_irq(&cm->reg_lock);
2254 return (nreg != oreg);
2255 }
2256
2257 /*
2258 * special case - check mixer sensitivity
2259 */
2260 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2261 struct snd_ctl_elem_value *ucontrol)
2262 {
2263 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2264 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2265 }
2266
2267 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2268 struct snd_ctl_elem_value *ucontrol)
2269 {
2270 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2271 if (cm->mixer_insensitive) {
2272 /* ignored */
2273 return 0;
2274 }
2275 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2276 }
2277
2278
2279 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2280 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2281 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2282 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2283 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2284 { /* switch with sensitivity */
2285 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2286 .name = "PCM Playback Switch",
2287 .info = snd_cmipci_info_native_mixer,
2288 .get = snd_cmipci_get_native_mixer_sensitive,
2289 .put = snd_cmipci_put_native_mixer_sensitive,
2290 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2291 },
2292 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2293 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2294 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2295 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2296 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2297 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2298 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2299 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2300 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2301 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2302 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2303 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2304 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2305 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2306 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2307 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2308 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2309 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2310 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2311 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2312 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2313 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2314 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2315 };
2316
2317 /*
2318 * other switches
2319 */
2320
2321 struct cmipci_switch_args {
2322 int reg; /* register index */
2323 unsigned int mask; /* mask bits */
2324 unsigned int mask_on; /* mask bits to turn on */
2325 unsigned int is_byte: 1; /* byte access? */
2326 unsigned int ac3_sensitive: 1; /* access forbidden during
2327 * non-audio operation?
2328 */
2329 };
2330
2331 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2332
2333 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2334 struct snd_ctl_elem_value *ucontrol,
2335 struct cmipci_switch_args *args)
2336 {
2337 unsigned int val;
2338 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2339
2340 spin_lock_irq(&cm->reg_lock);
2341 if (args->ac3_sensitive && cm->mixer_insensitive) {
2342 ucontrol->value.integer.value[0] = 0;
2343 spin_unlock_irq(&cm->reg_lock);
2344 return 0;
2345 }
2346 if (args->is_byte)
2347 val = inb(cm->iobase + args->reg);
2348 else
2349 val = snd_cmipci_read(cm, args->reg);
2350 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2351 spin_unlock_irq(&cm->reg_lock);
2352 return 0;
2353 }
2354
2355 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2356 struct snd_ctl_elem_value *ucontrol)
2357 {
2358 struct cmipci_switch_args *args;
2359 args = (struct cmipci_switch_args *)kcontrol->private_value;
2360 if (snd_BUG_ON(!args))
2361 return -EINVAL;
2362 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2363 }
2364
2365 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2366 struct snd_ctl_elem_value *ucontrol,
2367 struct cmipci_switch_args *args)
2368 {
2369 unsigned int val;
2370 int change;
2371 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2372
2373 spin_lock_irq(&cm->reg_lock);
2374 if (args->ac3_sensitive && cm->mixer_insensitive) {
2375 /* ignored */
2376 spin_unlock_irq(&cm->reg_lock);
2377 return 0;
2378 }
2379 if (args->is_byte)
2380 val = inb(cm->iobase + args->reg);
2381 else
2382 val = snd_cmipci_read(cm, args->reg);
2383 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2384 args->mask_on : (args->mask & ~args->mask_on));
2385 if (change) {
2386 val &= ~args->mask;
2387 if (ucontrol->value.integer.value[0])
2388 val |= args->mask_on;
2389 else
2390 val |= (args->mask & ~args->mask_on);
2391 if (args->is_byte)
2392 outb((unsigned char)val, cm->iobase + args->reg);
2393 else
2394 snd_cmipci_write(cm, args->reg, val);
2395 }
2396 spin_unlock_irq(&cm->reg_lock);
2397 return change;
2398 }
2399
2400 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2401 struct snd_ctl_elem_value *ucontrol)
2402 {
2403 struct cmipci_switch_args *args;
2404 args = (struct cmipci_switch_args *)kcontrol->private_value;
2405 if (snd_BUG_ON(!args))
2406 return -EINVAL;
2407 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2408 }
2409
2410 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2411 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2412 .reg = xreg, \
2413 .mask = xmask, \
2414 .mask_on = xmask_on, \
2415 .is_byte = xis_byte, \
2416 .ac3_sensitive = xac3, \
2417 }
2418
2419 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2420 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2421
2422 #if 0 /* these will be controlled in pcm device */
2423 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2424 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2425 #endif
2426 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2427 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2428 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2429 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2430 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2431 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2432 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2433 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2434 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2435 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2436 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2437 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2438 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2439 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2440 #if CM_CH_PLAY == 1
2441 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2442 #else
2443 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2444 #endif
2445 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2446 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2447 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2448 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2449 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2450
2451 #define DEFINE_SWITCH(sname, stype, sarg) \
2452 { .name = sname, \
2453 .iface = stype, \
2454 .info = snd_cmipci_uswitch_info, \
2455 .get = snd_cmipci_uswitch_get, \
2456 .put = snd_cmipci_uswitch_put, \
2457 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2458 }
2459
2460 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2461 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2462
2463
2464 /*
2465 * callbacks for spdif output switch
2466 * needs toggle two registers..
2467 */
2468 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2469 struct snd_ctl_elem_value *ucontrol)
2470 {
2471 int changed;
2472 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2473 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2474 return changed;
2475 }
2476
2477 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2478 struct snd_ctl_elem_value *ucontrol)
2479 {
2480 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2481 int changed;
2482 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2483 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2484 if (changed) {
2485 if (ucontrol->value.integer.value[0]) {
2486 if (chip->spdif_playback_avail)
2487 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2488 } else {
2489 if (chip->spdif_playback_avail)
2490 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2491 }
2492 }
2493 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2494 return changed;
2495 }
2496
2497
2498 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2499 struct snd_ctl_elem_info *uinfo)
2500 {
2501 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2502 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2503 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2504 uinfo->count = 1;
2505 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2506 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2507 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2508 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2509 return 0;
2510 }
2511
2512 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2513 {
2514 unsigned int val;
2515 if (cm->chip_version >= 39) {
2516 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2517 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2518 return 2;
2519 }
2520 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2521 if (val & CM_REAR2LIN)
2522 return 1;
2523 return 0;
2524 }
2525
2526 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2527 struct snd_ctl_elem_value *ucontrol)
2528 {
2529 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2530
2531 spin_lock_irq(&cm->reg_lock);
2532 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2533 spin_unlock_irq(&cm->reg_lock);
2534 return 0;
2535 }
2536
2537 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2538 struct snd_ctl_elem_value *ucontrol)
2539 {
2540 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2541 int change;
2542
2543 spin_lock_irq(&cm->reg_lock);
2544 if (ucontrol->value.enumerated.item[0] == 2)
2545 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2546 else
2547 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2548 if (ucontrol->value.enumerated.item[0] == 1)
2549 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2550 else
2551 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2552 spin_unlock_irq(&cm->reg_lock);
2553 return change;
2554 }
2555
2556 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2557 struct snd_ctl_elem_info *uinfo)
2558 {
2559 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2560 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2561 uinfo->count = 1;
2562 uinfo->value.enumerated.items = 2;
2563 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2564 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2565 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2566 return 0;
2567 }
2568
2569 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2570 struct snd_ctl_elem_value *ucontrol)
2571 {
2572 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2573 /* same bit as spdi_phase */
2574 spin_lock_irq(&cm->reg_lock);
2575 ucontrol->value.enumerated.item[0] =
2576 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2577 spin_unlock_irq(&cm->reg_lock);
2578 return 0;
2579 }
2580
2581 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2582 struct snd_ctl_elem_value *ucontrol)
2583 {
2584 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2585 int change;
2586
2587 spin_lock_irq(&cm->reg_lock);
2588 if (ucontrol->value.enumerated.item[0])
2589 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2590 else
2591 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2592 spin_unlock_irq(&cm->reg_lock);
2593 return change;
2594 }
2595
2596 /* both for CM8338/8738 */
2597 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2598 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2599 {
2600 .name = "Line-In Mode",
2601 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2602 .info = snd_cmipci_line_in_mode_info,
2603 .get = snd_cmipci_line_in_mode_get,
2604 .put = snd_cmipci_line_in_mode_put,
2605 },
2606 };
2607
2608 /* for non-multichannel chips */
2609 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2610 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2611
2612 /* only for CM8738 */
2613 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2614 #if 0 /* controlled in pcm device */
2615 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2616 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2617 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2618 #endif
2619 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2620 { .name = "IEC958 Output Switch",
2621 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2622 .info = snd_cmipci_uswitch_info,
2623 .get = snd_cmipci_spdout_enable_get,
2624 .put = snd_cmipci_spdout_enable_put,
2625 },
2626 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2627 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2628 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2629 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2630 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2631 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2632 };
2633
2634 /* only for model 033/037 */
2635 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2636 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2637 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2638 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2639 };
2640
2641 /* only for model 039 or later */
2642 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2643 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2644 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2645 {
2646 .name = "Mic-In Mode",
2647 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2648 .info = snd_cmipci_mic_in_mode_info,
2649 .get = snd_cmipci_mic_in_mode_get,
2650 .put = snd_cmipci_mic_in_mode_put,
2651 }
2652 };
2653
2654 /* card control switches */
2655 static struct snd_kcontrol_new snd_cmipci_modem_switch __devinitdata =
2656 DEFINE_CARD_SWITCH("Modem", modem);
2657
2658
2659 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2660 {
2661 struct snd_card *card;
2662 struct snd_kcontrol_new *sw;
2663 struct snd_kcontrol *kctl;
2664 unsigned int idx;
2665 int err;
2666
2667 if (snd_BUG_ON(!cm || !cm->card))
2668 return -EINVAL;
2669
2670 card = cm->card;
2671
2672 strcpy(card->mixername, "CMedia PCI");
2673
2674 spin_lock_irq(&cm->reg_lock);
2675 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2676 spin_unlock_irq(&cm->reg_lock);
2677
2678 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2679 if (cm->chip_version == 68) { // 8768 has no PCM volume
2680 if (!strcmp(snd_cmipci_mixers[idx].name,
2681 "PCM Playback Volume"))
2682 continue;
2683 }
2684 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2685 return err;
2686 }
2687
2688 /* mixer switches */
2689 sw = snd_cmipci_mixer_switches;
2690 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2691 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2692 if (err < 0)
2693 return err;
2694 }
2695 if (! cm->can_multi_ch) {
2696 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2697 if (err < 0)
2698 return err;
2699 }
2700 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2701 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2702 sw = snd_cmipci_8738_mixer_switches;
2703 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2704 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2705 if (err < 0)
2706 return err;
2707 }
2708 if (cm->can_ac3_hw) {
2709 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2710 return err;
2711 kctl->id.device = pcm_spdif_device;
2712 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2713 return err;
2714 kctl->id.device = pcm_spdif_device;
2715 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2716 return err;
2717 kctl->id.device = pcm_spdif_device;
2718 }
2719 if (cm->chip_version <= 37) {
2720 sw = snd_cmipci_old_mixer_switches;
2721 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2722 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2723 if (err < 0)
2724 return err;
2725 }
2726 }
2727 }
2728 if (cm->chip_version >= 39) {
2729 sw = snd_cmipci_extra_mixer_switches;
2730 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2731 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2732 if (err < 0)
2733 return err;
2734 }
2735 }
2736
2737 /* card switches */
2738 /*
2739 * newer chips don't have the register bits to force modem link
2740 * detection; the bit that was FLINKON now mutes CH1
2741 */
2742 if (cm->chip_version < 39) {
2743 err = snd_ctl_add(cm->card,
2744 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2745 if (err < 0)
2746 return err;
2747 }
2748
2749 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2750 struct snd_ctl_elem_id elem_id;
2751 struct snd_kcontrol *ctl;
2752 memset(&elem_id, 0, sizeof(elem_id));
2753 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2754 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2755 ctl = snd_ctl_find_id(cm->card, &elem_id);
2756 if (ctl)
2757 cm->mixer_res_ctl[idx] = ctl;
2758 }
2759
2760 return 0;
2761 }
2762
2763
2764 /*
2765 * proc interface
2766 */
2767
2768 #ifdef CONFIG_PROC_FS
2769 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2770 struct snd_info_buffer *buffer)
2771 {
2772 struct cmipci *cm = entry->private_data;
2773 int i, v;
2774
2775 snd_iprintf(buffer, "%s\n", cm->card->longname);
2776 for (i = 0; i < 0x94; i++) {
2777 if (i == 0x28)
2778 i = 0x90;
2779 v = inb(cm->iobase + i);
2780 if (i % 4 == 0)
2781 snd_iprintf(buffer, "\n%02x:", i);
2782 snd_iprintf(buffer, " %02x", v);
2783 }
2784 snd_iprintf(buffer, "\n");
2785 }
2786
2787 static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2788 {
2789 struct snd_info_entry *entry;
2790
2791 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2792 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2793 }
2794 #else /* !CONFIG_PROC_FS */
2795 static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2796 #endif
2797
2798
2799 static struct pci_device_id snd_cmipci_ids[] = {
2800 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2801 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2802 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2803 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2804 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2805 {0,},
2806 };
2807
2808
2809 /*
2810 * check chip version and capabilities
2811 * driver name is modified according to the chip model
2812 */
2813 static void __devinit query_chip(struct cmipci *cm)
2814 {
2815 unsigned int detect;
2816
2817 /* check reg 0Ch, bit 24-31 */
2818 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2819 if (! detect) {
2820 /* check reg 08h, bit 24-28 */
2821 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2822 switch (detect) {
2823 case 0:
2824 cm->chip_version = 33;
2825 if (cm->do_soft_ac3)
2826 cm->can_ac3_sw = 1;
2827 else
2828 cm->can_ac3_hw = 1;
2829 break;
2830 case CM_CHIP_037:
2831 cm->chip_version = 37;
2832 cm->can_ac3_hw = 1;
2833 break;
2834 default:
2835 cm->chip_version = 39;
2836 cm->can_ac3_hw = 1;
2837 break;
2838 }
2839 cm->max_channels = 2;
2840 } else {
2841 if (detect & CM_CHIP_039) {
2842 cm->chip_version = 39;
2843 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2844 cm->max_channels = 6;
2845 else
2846 cm->max_channels = 4;
2847 } else if (detect & CM_CHIP_8768) {
2848 cm->chip_version = 68;
2849 cm->max_channels = 8;
2850 cm->can_96k = 1;
2851 } else {
2852 cm->chip_version = 55;
2853 cm->max_channels = 6;
2854 cm->can_96k = 1;
2855 }
2856 cm->can_ac3_hw = 1;
2857 cm->can_multi_ch = 1;
2858 }
2859 }
2860
2861 #ifdef SUPPORT_JOYSTICK
2862 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2863 {
2864 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2865 struct gameport *gp;
2866 struct resource *r = NULL;
2867 int i, io_port = 0;
2868
2869 if (joystick_port[dev] == 0)
2870 return -ENODEV;
2871
2872 if (joystick_port[dev] == 1) { /* auto-detect */
2873 for (i = 0; ports[i]; i++) {
2874 io_port = ports[i];
2875 r = request_region(io_port, 1, "CMIPCI gameport");
2876 if (r)
2877 break;
2878 }
2879 } else {
2880 io_port = joystick_port[dev];
2881 r = request_region(io_port, 1, "CMIPCI gameport");
2882 }
2883
2884 if (!r) {
2885 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2886 return -EBUSY;
2887 }
2888
2889 cm->gameport = gp = gameport_allocate_port();
2890 if (!gp) {
2891 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2892 release_and_free_resource(r);
2893 return -ENOMEM;
2894 }
2895 gameport_set_name(gp, "C-Media Gameport");
2896 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2897 gameport_set_dev_parent(gp, &cm->pci->dev);
2898 gp->io = io_port;
2899 gameport_set_port_data(gp, r);
2900
2901 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2902
2903 gameport_register_port(cm->gameport);
2904
2905 return 0;
2906 }
2907
2908 static void snd_cmipci_free_gameport(struct cmipci *cm)
2909 {
2910 if (cm->gameport) {
2911 struct resource *r = gameport_get_port_data(cm->gameport);
2912
2913 gameport_unregister_port(cm->gameport);
2914 cm->gameport = NULL;
2915
2916 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2917 release_and_free_resource(r);
2918 }
2919 }
2920 #else
2921 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2922 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2923 #endif
2924
2925 static int snd_cmipci_free(struct cmipci *cm)
2926 {
2927 if (cm->irq >= 0) {
2928 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2929 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2930 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2931 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2932 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2933 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2934 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2935
2936 /* reset mixer */
2937 snd_cmipci_mixer_write(cm, 0, 0);
2938
2939 free_irq(cm->irq, cm);
2940 }
2941
2942 snd_cmipci_free_gameport(cm);
2943 pci_release_regions(cm->pci);
2944 pci_disable_device(cm->pci);
2945 kfree(cm);
2946 return 0;
2947 }
2948
2949 static int snd_cmipci_dev_free(struct snd_device *device)
2950 {
2951 struct cmipci *cm = device->device_data;
2952 return snd_cmipci_free(cm);
2953 }
2954
2955 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2956 {
2957 long iosynth;
2958 unsigned int val;
2959 struct snd_opl3 *opl3;
2960 int err;
2961
2962 if (!fm_port)
2963 goto disable_fm;
2964
2965 if (cm->chip_version >= 39) {
2966 /* first try FM regs in PCI port range */
2967 iosynth = cm->iobase + CM_REG_FM_PCI;
2968 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2969 OPL3_HW_OPL3, 1, &opl3);
2970 } else {
2971 err = -EIO;
2972 }
2973 if (err < 0) {
2974 /* then try legacy ports */
2975 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2976 iosynth = fm_port;
2977 switch (iosynth) {
2978 case 0x3E8: val |= CM_FMSEL_3E8; break;
2979 case 0x3E0: val |= CM_FMSEL_3E0; break;
2980 case 0x3C8: val |= CM_FMSEL_3C8; break;
2981 case 0x388: val |= CM_FMSEL_388; break;
2982 default:
2983 goto disable_fm;
2984 }
2985 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2986 /* enable FM */
2987 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2988
2989 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2990 OPL3_HW_OPL3, 0, &opl3) < 0) {
2991 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2992 "skipping...\n", iosynth);
2993 goto disable_fm;
2994 }
2995 }
2996 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2997 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2998 return err;
2999 }
3000 return 0;
3001
3002 disable_fm:
3003 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
3004 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
3005 return 0;
3006 }
3007
3008 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
3009 int dev, struct cmipci **rcmipci)
3010 {
3011 struct cmipci *cm;
3012 int err;
3013 static struct snd_device_ops ops = {
3014 .dev_free = snd_cmipci_dev_free,
3015 };
3016 unsigned int val;
3017 long iomidi;
3018 int integrated_midi = 0;
3019 char modelstr[16];
3020 int pcm_index, pcm_spdif_index;
3021 static struct pci_device_id intel_82437vx[] = {
3022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3023 { },
3024 };
3025
3026 *rcmipci = NULL;
3027
3028 if ((err = pci_enable_device(pci)) < 0)
3029 return err;
3030
3031 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3032 if (cm == NULL) {
3033 pci_disable_device(pci);
3034 return -ENOMEM;
3035 }
3036
3037 spin_lock_init(&cm->reg_lock);
3038 mutex_init(&cm->open_mutex);
3039 cm->device = pci->device;
3040 cm->card = card;
3041 cm->pci = pci;
3042 cm->irq = -1;
3043 cm->channel[0].ch = 0;
3044 cm->channel[1].ch = 1;
3045 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3046
3047 if ((err = pci_request_regions(pci, card->driver)) < 0) {
3048 kfree(cm);
3049 pci_disable_device(pci);
3050 return err;
3051 }
3052 cm->iobase = pci_resource_start(pci, 0);
3053
3054 if (request_irq(pci->irq, snd_cmipci_interrupt,
3055 IRQF_SHARED, card->driver, cm)) {
3056 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3057 snd_cmipci_free(cm);
3058 return -EBUSY;
3059 }
3060 cm->irq = pci->irq;
3061
3062 pci_set_master(cm->pci);
3063
3064 /*
3065 * check chip version, max channels and capabilities
3066 */
3067
3068 cm->chip_version = 0;
3069 cm->max_channels = 2;
3070 cm->do_soft_ac3 = soft_ac3[dev];
3071
3072 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3073 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3074 query_chip(cm);
3075 /* added -MCx suffix for chip supporting multi-channels */
3076 if (cm->can_multi_ch)
3077 sprintf(cm->card->driver + strlen(cm->card->driver),
3078 "-MC%d", cm->max_channels);
3079 else if (cm->can_ac3_sw)
3080 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3081
3082 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3083 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3084
3085 #if CM_CH_PLAY == 1
3086 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3087 #else
3088 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3089 #endif
3090
3091 /* initialize codec registers */
3092 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3093 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3094 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3095 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3096 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3097 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3098 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3099
3100 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3101 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3102 #if CM_CH_PLAY == 1
3103 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3104 #else
3105 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3106 #endif
3107 if (cm->chip_version) {
3108 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3109 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3110 }
3111 /* Set Bus Master Request */
3112 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3113
3114 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3115 switch (pci->device) {
3116 case PCI_DEVICE_ID_CMEDIA_CM8738:
3117 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3118 if (!pci_dev_present(intel_82437vx))
3119 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3120 break;
3121 default:
3122 break;
3123 }
3124
3125 if (cm->chip_version < 68) {
3126 val = pci->device < 0x110 ? 8338 : 8738;
3127 } else {
3128 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3129 case 0:
3130 val = 8769;
3131 break;
3132 case 2:
3133 val = 8762;
3134 break;
3135 default:
3136 switch ((pci->subsystem_vendor << 16) |
3137 pci->subsystem_device) {
3138 case 0x13f69761:
3139 case 0x584d3741:
3140 case 0x584d3751:
3141 case 0x584d3761:
3142 case 0x584d3771:
3143 case 0x72848384:
3144 val = 8770;
3145 break;
3146 default:
3147 val = 8768;
3148 break;
3149 }
3150 }
3151 }
3152 sprintf(card->shortname, "C-Media CMI%d", val);
3153 if (cm->chip_version < 68)
3154 sprintf(modelstr, " (model %d)", cm->chip_version);
3155 else
3156 modelstr[0] = '\0';
3157 sprintf(card->longname, "%s%s at %#lx, irq %i",
3158 card->shortname, modelstr, cm->iobase, cm->irq);
3159
3160 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3161 snd_cmipci_free(cm);
3162 return err;
3163 }
3164
3165 if (cm->chip_version >= 39) {
3166 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3167 if (val != 0x00 && val != 0xff) {
3168 iomidi = cm->iobase + CM_REG_MPU_PCI;
3169 integrated_midi = 1;
3170 }
3171 }
3172 if (!integrated_midi) {
3173 val = 0;
3174 iomidi = mpu_port[dev];
3175 switch (iomidi) {
3176 case 0x320: val = CM_VMPU_320; break;
3177 case 0x310: val = CM_VMPU_310; break;
3178 case 0x300: val = CM_VMPU_300; break;
3179 case 0x330: val = CM_VMPU_330; break;
3180 default:
3181 iomidi = 0; break;
3182 }
3183 if (iomidi > 0) {
3184 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3185 /* enable UART */
3186 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3187 if (inb(iomidi + 1) == 0xff) {
3188 snd_printk(KERN_ERR "cannot enable MPU-401 port"
3189 " at %#lx\n", iomidi);
3190 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3191 CM_UART_EN);
3192 iomidi = 0;
3193 }
3194 }
3195 }
3196
3197 if (cm->chip_version < 68) {
3198 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3199 if (err < 0)
3200 return err;
3201 }
3202
3203 /* reset mixer */
3204 snd_cmipci_mixer_write(cm, 0, 0);
3205
3206 snd_cmipci_proc_init(cm);
3207
3208 /* create pcm devices */
3209 pcm_index = pcm_spdif_index = 0;
3210 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3211 return err;
3212 pcm_index++;
3213 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3214 return err;
3215 pcm_index++;
3216 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3217 pcm_spdif_index = pcm_index;
3218 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3219 return err;
3220 }
3221
3222 /* create mixer interface & switches */
3223 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3224 return err;
3225
3226 if (iomidi > 0) {
3227 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3228 iomidi,
3229 (integrated_midi ?
3230 MPU401_INFO_INTEGRATED : 0),
3231 cm->irq, 0, &cm->rmidi)) < 0) {
3232 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
3233 }
3234 }
3235
3236 #ifdef USE_VAR48KRATE
3237 for (val = 0; val < ARRAY_SIZE(rates); val++)
3238 snd_cmipci_set_pll(cm, rates[val], val);
3239
3240 /*
3241 * (Re-)Enable external switch spdo_48k
3242 */
3243 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3244 #endif /* USE_VAR48KRATE */
3245
3246 if (snd_cmipci_create_gameport(cm, dev) < 0)
3247 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3248
3249 snd_card_set_dev(card, &pci->dev);
3250
3251 *rcmipci = cm;
3252 return 0;
3253 }
3254
3255 /*
3256 */
3257
3258 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3259
3260 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3261 const struct pci_device_id *pci_id)
3262 {
3263 static int dev;
3264 struct snd_card *card;
3265 struct cmipci *cm;
3266 int err;
3267
3268 if (dev >= SNDRV_CARDS)
3269 return -ENODEV;
3270 if (! enable[dev]) {
3271 dev++;
3272 return -ENOENT;
3273 }
3274
3275 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3276 if (card == NULL)
3277 return -ENOMEM;
3278
3279 switch (pci->device) {
3280 case PCI_DEVICE_ID_CMEDIA_CM8738:
3281 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3282 strcpy(card->driver, "CMI8738");
3283 break;
3284 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3285 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3286 strcpy(card->driver, "CMI8338");
3287 break;
3288 default:
3289 strcpy(card->driver, "CMIPCI");
3290 break;
3291 }
3292
3293 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3294 snd_card_free(card);
3295 return err;
3296 }
3297 card->private_data = cm;
3298
3299 if ((err = snd_card_register(card)) < 0) {
3300 snd_card_free(card);
3301 return err;
3302 }
3303 pci_set_drvdata(pci, card);
3304 dev++;
3305 return 0;
3306
3307 }
3308
3309 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3310 {
3311 snd_card_free(pci_get_drvdata(pci));
3312 pci_set_drvdata(pci, NULL);
3313 }
3314
3315
3316 #ifdef CONFIG_PM
3317 /*
3318 * power management
3319 */
3320 static unsigned char saved_regs[] = {
3321 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3322 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3323 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3324 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3325 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3326 };
3327
3328 static unsigned char saved_mixers[] = {
3329 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3330 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3331 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3332 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3333 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3334 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3335 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3336 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3337 };
3338
3339 static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3340 {
3341 struct snd_card *card = pci_get_drvdata(pci);
3342 struct cmipci *cm = card->private_data;
3343 int i;
3344
3345 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3346
3347 snd_pcm_suspend_all(cm->pcm);
3348 snd_pcm_suspend_all(cm->pcm2);
3349 snd_pcm_suspend_all(cm->pcm_spdif);
3350
3351 /* save registers */
3352 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3353 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3354 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3355 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3356
3357 /* disable ints */
3358 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3359
3360 pci_disable_device(pci);
3361 pci_save_state(pci);
3362 pci_set_power_state(pci, pci_choose_state(pci, state));
3363 return 0;
3364 }
3365
3366 static int snd_cmipci_resume(struct pci_dev *pci)
3367 {
3368 struct snd_card *card = pci_get_drvdata(pci);
3369 struct cmipci *cm = card->private_data;
3370 int i;
3371
3372 pci_set_power_state(pci, PCI_D0);
3373 pci_restore_state(pci);
3374 if (pci_enable_device(pci) < 0) {
3375 printk(KERN_ERR "cmipci: pci_enable_device failed, "
3376 "disabling device\n");
3377 snd_card_disconnect(card);
3378 return -EIO;
3379 }
3380 pci_set_master(pci);
3381
3382 /* reset / initialize to a sane state */
3383 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3384 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3385 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3386 snd_cmipci_mixer_write(cm, 0, 0);
3387
3388 /* restore registers */
3389 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3390 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3391 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3392 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3393
3394 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3395 return 0;
3396 }
3397 #endif /* CONFIG_PM */
3398
3399 static struct pci_driver driver = {
3400 .name = "C-Media PCI",
3401 .id_table = snd_cmipci_ids,
3402 .probe = snd_cmipci_probe,
3403 .remove = __devexit_p(snd_cmipci_remove),
3404 #ifdef CONFIG_PM
3405 .suspend = snd_cmipci_suspend,
3406 .resume = snd_cmipci_resume,
3407 #endif
3408 };
3409
3410 static int __init alsa_card_cmipci_init(void)
3411 {
3412 return pci_register_driver(&driver);
3413 }
3414
3415 static void __exit alsa_card_cmipci_exit(void)
3416 {
3417 pci_unregister_driver(&driver);
3418 }
3419
3420 module_init(alsa_card_cmipci_init)
3421 module_exit(alsa_card_cmipci_exit)
Support for the Chinese Samsung S3C2440 based development boards