2 * linux/arch/arm/mm/alignment.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2001 Russell King
6 * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
8 * Copyright (C) 1996, Cygnus Software Technologies Ltd.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/compiler.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/proc_fs.h>
19 #include <linux/init.h>
20 #include <linux/uaccess.h>
22 #include <asm/unaligned.h>
27 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
28 * /proc/sys/debug/alignment, modified and integrated into
29 * Linux 2.1 by Russell King
31 * Speed optimisations and better fault handling by Russell King.
34 * This code is not portable to processors with late data abort handling.
36 #define CODING_BITS(i) (i & 0x0e000000)
38 #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
39 #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
40 #define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
41 #define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
42 #define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
44 #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
46 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
47 #define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
49 #define RN_BITS(i) ((i >> 16) & 15) /* Rn */
50 #define RD_BITS(i) ((i >> 12) & 15) /* Rd */
51 #define RM_BITS(i) (i & 15) /* Rm */
53 #define REGMASK_BITS(i) (i & 0xffff)
54 #define OFFSET_BITS(i) (i & 0x0fff)
56 #define IS_SHIFT(i) (i & 0x0ff0)
57 #define SHIFT_BITS(i) ((i >> 7) & 0x1f)
58 #define SHIFT_TYPE(i) (i & 0x60)
59 #define SHIFT_LSL 0x00
60 #define SHIFT_LSR 0x20
61 #define SHIFT_ASR 0x40
62 #define SHIFT_RORRRX 0x60
64 static unsigned long ai_user
;
65 static unsigned long ai_sys
;
66 static unsigned long ai_skipped
;
67 static unsigned long ai_half
;
68 static unsigned long ai_word
;
69 static unsigned long ai_dword
;
70 static unsigned long ai_multi
;
71 static int ai_usermode
;
74 static const char *usermode_action
[] = {
84 proc_alignment_read(char *page
, char **start
, off_t off
, int count
, int *eof
,
90 p
+= sprintf(p
, "User:\t\t%lu\n", ai_user
);
91 p
+= sprintf(p
, "System:\t\t%lu\n", ai_sys
);
92 p
+= sprintf(p
, "Skipped:\t%lu\n", ai_skipped
);
93 p
+= sprintf(p
, "Half:\t\t%lu\n", ai_half
);
94 p
+= sprintf(p
, "Word:\t\t%lu\n", ai_word
);
95 if (cpu_architecture() >= CPU_ARCH_ARMv5TE
)
96 p
+= sprintf(p
, "DWord:\t\t%lu\n", ai_dword
);
97 p
+= sprintf(p
, "Multi:\t\t%lu\n", ai_multi
);
98 p
+= sprintf(p
, "User faults:\t%i (%s)\n", ai_usermode
,
99 usermode_action
[ai_usermode
]);
101 len
= (p
- page
) - off
;
105 *eof
= (len
<= count
) ? 1 : 0;
111 static int proc_alignment_write(struct file
*file
, const char __user
*buffer
,
112 unsigned long count
, void *data
)
117 if (get_user(mode
, buffer
))
119 if (mode
>= '0' && mode
<= '5')
120 ai_usermode
= mode
- '0';
125 #endif /* CONFIG_PROC_FS */
139 #define FIRST_BYTE_16 "mov %1, %1, ror #8\n"
140 #define FIRST_BYTE_32 "mov %1, %1, ror #24\n"
141 #define NEXT_BYTE "ror #24"
144 #define FIRST_BYTE_16
145 #define FIRST_BYTE_32
146 #define NEXT_BYTE "lsr #8"
149 #define __get8_unaligned_check(ins,val,addr,err) \
151 "1: "ins" %1, [%2], #1\n" \
153 " .section .fixup,\"ax\"\n" \
158 " .section __ex_table,\"a\"\n" \
162 : "=r" (err), "=&r" (val), "=r" (addr) \
163 : "0" (err), "2" (addr))
165 #define __get16_unaligned_check(ins,val,addr) \
167 unsigned int err = 0, v, a = addr; \
168 __get8_unaligned_check(ins,v,a,err); \
169 val = v << ((BE) ? 8 : 0); \
170 __get8_unaligned_check(ins,v,a,err); \
171 val |= v << ((BE) ? 0 : 8); \
176 #define get16_unaligned_check(val,addr) \
177 __get16_unaligned_check("ldrb",val,addr)
179 #define get16t_unaligned_check(val,addr) \
180 __get16_unaligned_check("ldrbt",val,addr)
182 #define __get32_unaligned_check(ins,val,addr) \
184 unsigned int err = 0, v, a = addr; \
185 __get8_unaligned_check(ins,v,a,err); \
186 val = v << ((BE) ? 24 : 0); \
187 __get8_unaligned_check(ins,v,a,err); \
188 val |= v << ((BE) ? 16 : 8); \
189 __get8_unaligned_check(ins,v,a,err); \
190 val |= v << ((BE) ? 8 : 16); \
191 __get8_unaligned_check(ins,v,a,err); \
192 val |= v << ((BE) ? 0 : 24); \
197 #define get32_unaligned_check(val,addr) \
198 __get32_unaligned_check("ldrb",val,addr)
200 #define get32t_unaligned_check(val,addr) \
201 __get32_unaligned_check("ldrbt",val,addr)
203 #define __put16_unaligned_check(ins,val,addr) \
205 unsigned int err = 0, v = val, a = addr; \
206 __asm__( FIRST_BYTE_16 \
207 "1: "ins" %1, [%2], #1\n" \
208 " mov %1, %1, "NEXT_BYTE"\n" \
209 "2: "ins" %1, [%2]\n" \
211 " .section .fixup,\"ax\"\n" \
216 " .section __ex_table,\"a\"\n" \
221 : "=r" (err), "=&r" (v), "=&r" (a) \
222 : "0" (err), "1" (v), "2" (a)); \
227 #define put16_unaligned_check(val,addr) \
228 __put16_unaligned_check("strb",val,addr)
230 #define put16t_unaligned_check(val,addr) \
231 __put16_unaligned_check("strbt",val,addr)
233 #define __put32_unaligned_check(ins,val,addr) \
235 unsigned int err = 0, v = val, a = addr; \
236 __asm__( FIRST_BYTE_32 \
237 "1: "ins" %1, [%2], #1\n" \
238 " mov %1, %1, "NEXT_BYTE"\n" \
239 "2: "ins" %1, [%2], #1\n" \
240 " mov %1, %1, "NEXT_BYTE"\n" \
241 "3: "ins" %1, [%2], #1\n" \
242 " mov %1, %1, "NEXT_BYTE"\n" \
243 "4: "ins" %1, [%2]\n" \
245 " .section .fixup,\"ax\"\n" \
250 " .section __ex_table,\"a\"\n" \
257 : "=r" (err), "=&r" (v), "=&r" (a) \
258 : "0" (err), "1" (v), "2" (a)); \
263 #define put32_unaligned_check(val,addr) \
264 __put32_unaligned_check("strb", val, addr)
266 #define put32t_unaligned_check(val,addr) \
267 __put32_unaligned_check("strbt", val, addr)
270 do_alignment_finish_ldst(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
, union offset_union offset
)
272 if (!LDST_U_BIT(instr
))
273 offset
.un
= -offset
.un
;
275 if (!LDST_P_BIT(instr
))
278 if (!LDST_P_BIT(instr
) || LDST_W_BIT(instr
))
279 regs
->uregs
[RN_BITS(instr
)] = addr
;
283 do_alignment_ldrhstrh(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
)
285 unsigned int rd
= RD_BITS(instr
);
292 if (LDST_L_BIT(instr
)) {
294 get16_unaligned_check(val
, addr
);
296 /* signed half-word? */
298 val
= (signed long)((signed short) val
);
300 regs
->uregs
[rd
] = val
;
302 put16_unaligned_check(regs
->uregs
[rd
], addr
);
307 if (LDST_L_BIT(instr
)) {
309 get16t_unaligned_check(val
, addr
);
311 /* signed half-word? */
313 val
= (signed long)((signed short) val
);
315 regs
->uregs
[rd
] = val
;
317 put16t_unaligned_check(regs
->uregs
[rd
], addr
);
326 do_alignment_ldrdstrd(unsigned long addr
, unsigned long instr
,
327 struct pt_regs
*regs
)
329 unsigned int rd
= RD_BITS(instr
);
331 if (((rd
& 1) == 1) || (rd
== 14))
339 if ((instr
& 0xf0) == 0xd0) {
341 get32_unaligned_check(val
, addr
);
342 regs
->uregs
[rd
] = val
;
343 get32_unaligned_check(val
, addr
+ 4);
344 regs
->uregs
[rd
+ 1] = val
;
346 put32_unaligned_check(regs
->uregs
[rd
], addr
);
347 put32_unaligned_check(regs
->uregs
[rd
+ 1], addr
+ 4);
353 if ((instr
& 0xf0) == 0xd0) {
355 get32t_unaligned_check(val
, addr
);
356 regs
->uregs
[rd
] = val
;
357 get32t_unaligned_check(val
, addr
+ 4);
358 regs
->uregs
[rd
+ 1] = val
;
360 put32t_unaligned_check(regs
->uregs
[rd
], addr
);
361 put32t_unaligned_check(regs
->uregs
[rd
+ 1], addr
+ 4);
372 do_alignment_ldrstr(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
)
374 unsigned int rd
= RD_BITS(instr
);
378 if ((!LDST_P_BIT(instr
) && LDST_W_BIT(instr
)) || user_mode(regs
))
381 if (LDST_L_BIT(instr
)) {
383 get32_unaligned_check(val
, addr
);
384 regs
->uregs
[rd
] = val
;
386 put32_unaligned_check(regs
->uregs
[rd
], addr
);
390 if (LDST_L_BIT(instr
)) {
392 get32t_unaligned_check(val
, addr
);
393 regs
->uregs
[rd
] = val
;
395 put32t_unaligned_check(regs
->uregs
[rd
], addr
);
403 * LDM/STM alignment handler.
405 * There are 4 variants of this instruction:
407 * B = rn pointer before instruction, A = rn pointer after instruction
408 * ------ increasing address ----->
409 * | | r0 | r1 | ... | rx | |
416 do_alignment_ldmstm(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
)
418 unsigned int rd
, rn
, correction
, nr_regs
, regbits
;
419 unsigned long eaddr
, newaddr
;
421 if (LDM_S_BIT(instr
))
424 correction
= 4; /* processor implementation defined */
425 regs
->ARM_pc
+= correction
;
429 /* count the number of registers in the mask to be transferred */
430 nr_regs
= hweight16(REGMASK_BITS(instr
)) * 4;
433 newaddr
= eaddr
= regs
->uregs
[rn
];
435 if (!LDST_U_BIT(instr
))
438 if (!LDST_U_BIT(instr
))
441 if (LDST_P_EQ_U(instr
)) /* U = P */
445 * For alignment faults on the ARM922T/ARM920T the MMU makes
446 * the FSR (and hence addr) equal to the updated base address
447 * of the multiple access rather than the restored value.
448 * Switch this message off if we've got a ARM92[02], otherwise
449 * [ls]dm alignment faults are noisy!
451 #if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T)
453 * This is a "hint" - we already have eaddr worked out by the
457 printk(KERN_ERR
"LDMSTM: PC = %08lx, instr = %08lx, "
458 "addr = %08lx, eaddr = %08lx\n",
459 instruction_pointer(regs
), instr
, addr
, eaddr
);
464 if (user_mode(regs
)) {
465 for (regbits
= REGMASK_BITS(instr
), rd
= 0; regbits
;
466 regbits
>>= 1, rd
+= 1)
468 if (LDST_L_BIT(instr
)) {
470 get32t_unaligned_check(val
, eaddr
);
471 regs
->uregs
[rd
] = val
;
473 put32t_unaligned_check(regs
->uregs
[rd
], eaddr
);
477 for (regbits
= REGMASK_BITS(instr
), rd
= 0; regbits
;
478 regbits
>>= 1, rd
+= 1)
480 if (LDST_L_BIT(instr
)) {
482 get32_unaligned_check(val
, eaddr
);
483 regs
->uregs
[rd
] = val
;
485 put32_unaligned_check(regs
->uregs
[rd
], eaddr
);
490 if (LDST_W_BIT(instr
))
491 regs
->uregs
[rn
] = newaddr
;
492 if (!LDST_L_BIT(instr
) || !(REGMASK_BITS(instr
) & (1 << 15)))
493 regs
->ARM_pc
-= correction
;
497 regs
->ARM_pc
-= correction
;
501 printk(KERN_ERR
"Alignment trap: not handling ldm with s-bit set\n");
506 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
507 * we can reuse ARM userland alignment fault fixups for Thumb.
509 * This implementation was initially based on the algorithm found in
510 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
511 * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
514 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
515 * 2. If for some reason we're passed an non-ld/st Thumb instruction to
516 * decode, we return 0xdeadc0de. This should never happen under normal
517 * circumstances but if it does, we've got other problems to deal with
518 * elsewhere and we obviously can't fix those problems here.
522 thumb2arm(u16 tinstr
)
524 u32 L
= (tinstr
& (1<<11)) >> 11;
526 switch ((tinstr
& 0xf800) >> 11) {
527 /* 6.5.1 Format 1: */
528 case 0x6000 >> 11: /* 7.1.52 STR(1) */
529 case 0x6800 >> 11: /* 7.1.26 LDR(1) */
530 case 0x7000 >> 11: /* 7.1.55 STRB(1) */
531 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */
533 ((tinstr
& (1<<12)) << (22-12)) | /* fixup */
534 (L
<<20) | /* L==1? */
535 ((tinstr
& (7<<0)) << (12-0)) | /* Rd */
536 ((tinstr
& (7<<3)) << (16-3)) | /* Rn */
537 ((tinstr
& (31<<6)) >> /* immed_5 */
538 (6 - ((tinstr
& (1<<12)) ? 0 : 2)));
539 case 0x8000 >> 11: /* 7.1.57 STRH(1) */
540 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */
542 (L
<<20) | /* L==1? */
543 ((tinstr
& (7<<0)) << (12-0)) | /* Rd */
544 ((tinstr
& (7<<3)) << (16-3)) | /* Rn */
545 ((tinstr
& (7<<6)) >> (6-1)) | /* immed_5[2:0] */
546 ((tinstr
& (3<<9)) >> (9-8)); /* immed_5[4:3] */
548 /* 6.5.1 Format 2: */
552 static const u32 subset
[8] = {
553 0xe7800000, /* 7.1.53 STR(2) */
554 0xe18000b0, /* 7.1.58 STRH(2) */
555 0xe7c00000, /* 7.1.56 STRB(2) */
556 0xe19000d0, /* 7.1.34 LDRSB */
557 0xe7900000, /* 7.1.27 LDR(2) */
558 0xe19000b0, /* 7.1.33 LDRH(2) */
559 0xe7d00000, /* 7.1.31 LDRB(2) */
560 0xe19000f0 /* 7.1.35 LDRSH */
562 return subset
[(tinstr
& (7<<9)) >> 9] |
563 ((tinstr
& (7<<0)) << (12-0)) | /* Rd */
564 ((tinstr
& (7<<3)) << (16-3)) | /* Rn */
565 ((tinstr
& (7<<6)) >> (6-0)); /* Rm */
568 /* 6.5.1 Format 3: */
569 case 0x4800 >> 11: /* 7.1.28 LDR(3) */
570 /* NOTE: This case is not technically possible. We're
571 * loading 32-bit memory data via PC relative
572 * addressing mode. So we can and should eliminate
573 * this case. But I'll leave it here for now.
576 ((tinstr
& (7<<8)) << (12-8)) | /* Rd */
577 ((tinstr
& 255) << (2-0)); /* immed_8 */
579 /* 6.5.1 Format 4: */
580 case 0x9000 >> 11: /* 7.1.54 STR(3) */
581 case 0x9800 >> 11: /* 7.1.29 LDR(4) */
583 (L
<<20) | /* L==1? */
584 ((tinstr
& (7<<8)) << (12-8)) | /* Rd */
585 ((tinstr
& 255) << 2); /* immed_8 */
587 /* 6.6.1 Format 1: */
588 case 0xc000 >> 11: /* 7.1.51 STMIA */
589 case 0xc800 >> 11: /* 7.1.25 LDMIA */
591 u32 Rn
= (tinstr
& (7<<8)) >> 8;
592 u32 W
= ((L
<<Rn
) & (tinstr
&255)) ? 0 : 1<<21;
594 return 0xe8800000 | W
| (L
<<20) | (Rn
<<16) |
598 /* 6.6.1 Format 2: */
599 case 0xb000 >> 11: /* 7.1.48 PUSH */
600 case 0xb800 >> 11: /* 7.1.47 POP */
601 if ((tinstr
& (3 << 9)) == 0x0400) {
602 static const u32 subset
[4] = {
603 0xe92d0000, /* STMDB sp!,{registers} */
604 0xe92d4000, /* STMDB sp!,{registers,lr} */
605 0xe8bd0000, /* LDMIA sp!,{registers} */
606 0xe8bd8000 /* LDMIA sp!,{registers,pc} */
608 return subset
[(L
<<1) | ((tinstr
& (1<<8)) >> 8)] |
609 (tinstr
& 255); /* register_list */
611 /* Else fall through for illegal instruction case */
619 do_alignment(unsigned long addr
, unsigned int fsr
, struct pt_regs
*regs
)
621 union offset_union offset
;
622 unsigned long instr
= 0, instrptr
;
623 int (*handler
)(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
);
629 instrptr
= instruction_pointer(regs
);
633 if (thumb_mode(regs
)) {
634 fault
= __get_user(tinstr
, (u16
*)(instrptr
& ~1));
636 instr
= thumb2arm(tinstr
);
638 fault
= __get_user(instr
, (u32
*)instrptr
);
653 regs
->ARM_pc
+= thumb_mode(regs
) ? 2 : 4;
655 switch (CODING_BITS(instr
)) {
656 case 0x00000000: /* 3.13.4 load/store instruction extensions */
657 if (LDSTHD_I_BIT(instr
))
658 offset
.un
= (instr
& 0xf00) >> 4 | (instr
& 15);
660 offset
.un
= regs
->uregs
[RM_BITS(instr
)];
662 if ((instr
& 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
663 (instr
& 0x001000f0) == 0x001000f0) /* LDRSH */
664 handler
= do_alignment_ldrhstrh
;
665 else if ((instr
& 0x001000f0) == 0x000000d0 || /* LDRD */
666 (instr
& 0x001000f0) == 0x000000f0) /* STRD */
667 handler
= do_alignment_ldrdstrd
;
668 else if ((instr
& 0x01f00ff0) == 0x01000090) /* SWP */
674 case 0x04000000: /* ldr or str immediate */
675 offset
.un
= OFFSET_BITS(instr
);
676 handler
= do_alignment_ldrstr
;
679 case 0x06000000: /* ldr or str register */
680 offset
.un
= regs
->uregs
[RM_BITS(instr
)];
682 if (IS_SHIFT(instr
)) {
683 unsigned int shiftval
= SHIFT_BITS(instr
);
685 switch(SHIFT_TYPE(instr
)) {
687 offset
.un
<<= shiftval
;
691 offset
.un
>>= shiftval
;
695 offset
.sn
>>= shiftval
;
701 if (regs
->ARM_cpsr
& PSR_C_BIT
)
702 offset
.un
|= 1 << 31;
704 offset
.un
= offset
.un
>> shiftval
|
705 offset
.un
<< (32 - shiftval
);
709 handler
= do_alignment_ldrstr
;
712 case 0x08000000: /* ldm or stm */
713 handler
= do_alignment_ldmstm
;
720 type
= handler(addr
, instr
, regs
);
722 if (type
== TYPE_ERROR
|| type
== TYPE_FAULT
)
725 if (type
== TYPE_LDST
)
726 do_alignment_finish_ldst(addr
, instr
, regs
, offset
);
731 if (type
== TYPE_ERROR
)
733 regs
->ARM_pc
-= thumb_mode(regs
) ? 2 : 4;
735 * We got a fault - fix it up, or die.
737 do_bad_area(addr
, fsr
, regs
);
741 printk(KERN_ERR
"Alignment trap: not handling swp instruction\n");
745 * Oops, we didn't handle the instruction.
747 printk(KERN_ERR
"Alignment trap: not handling instruction "
748 "%0*lx at [<%08lx>]\n",
749 thumb_mode(regs
) ? 4 : 8,
750 thumb_mode(regs
) ? tinstr
: instr
, instrptr
);
758 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
759 "Address=0x%08lx FSR 0x%03x\n", current
->comm
,
760 task_pid_nr(current
), instrptr
,
761 thumb_mode(regs
) ? 4 : 8,
762 thumb_mode(regs
) ? tinstr
: instr
,
769 force_sig(SIGBUS
, current
);
771 set_cr(cr_no_alignment
);
777 * This needs to be done after sysctl_init, otherwise sys/ will be
778 * overwritten. Actually, this shouldn't be in sys/ at all since
779 * it isn't a sysctl, and it doesn't contain sysctl information.
780 * We now locate it in /proc/cpu/alignment instead.
782 static int __init
alignment_init(void)
784 #ifdef CONFIG_PROC_FS
785 struct proc_dir_entry
*res
;
787 res
= proc_mkdir("cpu", NULL
);
791 res
= create_proc_entry("alignment", S_IWUSR
| S_IRUGO
, res
);
795 res
->read_proc
= proc_alignment_read
;
796 res
->write_proc
= proc_alignment_write
;
799 hook_fault_code(1, do_alignment
, SIGILL
, "alignment exception");
800 hook_fault_code(3, do_alignment
, SIGILL
, "alignment exception");
805 fs_initcall(alignment_init
);