drivers/scsi/sata_sis.c

   1 /*
   2  *  sata_sis.c - Silicon Integrated Systems SATA
   3  *
   4  *  Maintained by:  Uwe Koziolek
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2004 Uwe Koziolek
   9  *
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; see the file COPYING.  If not, write to
  23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  *
  26  *  libata documentation is available via 'make {ps|pdf}docs',
  27  *  as Documentation/DocBook/libata.*
  28  *
  29  *  Hardware documentation available under NDA.
  30  *
  31  */
  32
  33 #include <linux/config.h>
  34 #include <linux/kernel.h>
  35 #include <linux/module.h>
  36 #include <linux/pci.h>
  37 #include <linux/init.h>
  38 #include <linux/blkdev.h>
  39 #include <linux/delay.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/device.h>
  42 #include <scsi/scsi_host.h>
  43 #include <linux/libata.h>
  44
  45 #define DRV_NAME        "sata_sis"
  46 #define DRV_VERSION     "0.5"
  47
  48 enum {
  49         sis_180                 = 0,
  50         SIS_SCR_PCI_BAR         = 5,
  51
  52         /* PCI configuration registers */
  53         SIS_GENCTL              = 0x54, /* IDE General Control register */
  54         SIS_SCR_BASE            = 0xc0, /* sata0 phy SCR registers */
  55         SIS180_SATA1_OFS        = 0x10, /* offset from sata0->sata1 phy regs */
  56         SIS182_SATA1_OFS        = 0x20, /* offset from sata0->sata1 phy regs */
  57         SIS_PMR                 = 0x90, /* port mapping register */
  58         SIS_PMR_COMBINED        = 0x30,
  59
  60         /* random bits */
  61         SIS_FLAG_CFGSCR         = (1 << 30), /* host flag: SCRs via PCI cfg */
  62
  63         GENCTL_IOMAPPED_SCR     = (1 << 26), /* if set, SCRs are in IO space */
  64 };
  65
  66 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  67 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
  68 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
  69
  70 static const struct pci_device_id sis_pci_tbl[] = {
  71         { PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
  72         { PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
  73         { PCI_VENDOR_ID_SI, 0x182, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
  74         { }     /* terminate list */
  75 };
  76
  77
  78 static struct pci_driver sis_pci_driver = {
  79         .name                   = DRV_NAME,
  80         .id_table               = sis_pci_tbl,
  81         .probe                  = sis_init_one,
  82         .remove                 = ata_pci_remove_one,
  83 };
  84
  85 static struct scsi_host_template sis_sht = {
  86         .module                 = THIS_MODULE,
  87         .name                   = DRV_NAME,
  88         .ioctl                  = ata_scsi_ioctl,
  89         .queuecommand           = ata_scsi_queuecmd,
  90         .eh_strategy_handler    = ata_scsi_error,
  91         .can_queue              = ATA_DEF_QUEUE,
  92         .this_id                = ATA_SHT_THIS_ID,
  93         .sg_tablesize           = ATA_MAX_PRD,
  94         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
  95         .emulated               = ATA_SHT_EMULATED,
  96         .use_clustering         = ATA_SHT_USE_CLUSTERING,
  97         .proc_name              = DRV_NAME,
  98         .dma_boundary           = ATA_DMA_BOUNDARY,
  99         .slave_configure        = ata_scsi_slave_config,
 100         .bios_param             = ata_std_bios_param,
 101 };
 102
 103 static const struct ata_port_operations sis_ops = {
 104         .port_disable           = ata_port_disable,
 105         .tf_load                = ata_tf_load,
 106         .tf_read                = ata_tf_read,
 107         .check_status           = ata_check_status,
 108         .exec_command           = ata_exec_command,
 109         .dev_select             = ata_std_dev_select,
 110         .phy_reset              = sata_phy_reset,
 111         .bmdma_setup            = ata_bmdma_setup,
 112         .bmdma_start            = ata_bmdma_start,
 113         .bmdma_stop             = ata_bmdma_stop,
 114         .bmdma_status           = ata_bmdma_status,
 115         .qc_prep                = ata_qc_prep,
 116         .qc_issue               = ata_qc_issue_prot,
 117         .eng_timeout            = ata_eng_timeout,
 118         .irq_handler            = ata_interrupt,
 119         .irq_clear              = ata_bmdma_irq_clear,
 120         .scr_read               = sis_scr_read,
 121         .scr_write              = sis_scr_write,
 122         .port_start             = ata_port_start,
 123         .port_stop              = ata_port_stop,
 124         .host_stop              = ata_host_stop,
 125 };
 126
 127 static struct ata_port_info sis_port_info = {
 128         .sht            = &sis_sht,
 129         .host_flags     = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
 130                           ATA_FLAG_NO_LEGACY,
 131         .pio_mask       = 0x1f,
 132         .mwdma_mask     = 0x7,
 133         .udma_mask      = 0x7f,
 134         .port_ops       = &sis_ops,
 135 };
 136
 137
 138 MODULE_AUTHOR("Uwe Koziolek");
 139 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
 140 MODULE_LICENSE("GPL");
 141 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
 142 MODULE_VERSION(DRV_VERSION);
 143
 144 static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device)
 145 {
 146         unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
 147
 148         if (port_no)  {
 149                 if (device == 0x182)
 150                         addr += SIS182_SATA1_OFS;
 151                 else
 152                         addr += SIS180_SATA1_OFS;
 153         }
 154
 155         return addr;
 156 }
 157
 158 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
 159 {
 160         struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
 161         unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
 162         u32 val, val2 = 0;
 163         u8 pmr;
 164
 165         if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
 166                 return 0xffffffff;
 167
 168         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 169
 170         pci_read_config_dword(pdev, cfg_addr, &val);
 171
 172         if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
 173                 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
 174
 175         return val|val2;
 176 }
 177
 178 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
 179 {
 180         struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
 181         unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device);
 182         u8 pmr;
 183
 184         if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
 185                 return;
 186
 187         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 188
 189         pci_write_config_dword(pdev, cfg_addr, val);
 190
 191         if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
 192                 pci_write_config_dword(pdev, cfg_addr+0x10, val);
 193 }
 194
 195 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
 196 {
 197         struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
 198         u32 val, val2 = 0;
 199         u8 pmr;
 200
 201         if (sc_reg > SCR_CONTROL)
 202                 return 0xffffffffU;
 203
 204         if (ap->flags & SIS_FLAG_CFGSCR)
 205                 return sis_scr_cfg_read(ap, sc_reg);
 206
 207         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 208
 209         val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
 210
 211         if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
 212                 val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
 213
 214         return val | val2;
 215 }
 216
 217 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
 218 {
 219         struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
 220         u8 pmr;
 221
 222         if (sc_reg > SCR_CONTROL)
 223                 return;
 224
 225         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 226
 227         if (ap->flags & SIS_FLAG_CFGSCR)
 228                 sis_scr_cfg_write(ap, sc_reg, val);
 229         else {
 230                 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
 231                 if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
 232                         outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
 233         }
 234 }
 235
 236 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 237 {
 238         static int printed_version;
 239         struct ata_probe_ent *probe_ent = NULL;
 240         int rc;
 241         u32 genctl;
 242         struct ata_port_info *ppi;
 243         int pci_dev_busy = 0;
 244         u8 pmr;
 245         u8 port2_start;
 246
 247         if (!printed_version++)
 248                 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
 249
 250         rc = pci_enable_device(pdev);
 251         if (rc)
 252                 return rc;
 253
 254         rc = pci_request_regions(pdev, DRV_NAME);
 255         if (rc) {
 256                 pci_dev_busy = 1;
 257                 goto err_out;
 258         }
 259
 260         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 261         if (rc)
 262                 goto err_out_regions;
 263         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 264         if (rc)
 265                 goto err_out_regions;
 266
 267         ppi = &sis_port_info;
 268         probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
 269         if (!probe_ent) {
 270                 rc = -ENOMEM;
 271                 goto err_out_regions;
 272         }
 273
 274         /* check and see if the SCRs are in IO space or PCI cfg space */
 275         pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
 276         if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
 277                 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
 278
 279         /* if hardware thinks SCRs are in IO space, but there are
 280          * no IO resources assigned, change to PCI cfg space.
 281          */
 282         if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
 283             ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
 284              (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
 285                 genctl &= ~GENCTL_IOMAPPED_SCR;
 286                 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
 287                 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
 288         }
 289
 290         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 291         if (ent->device != 0x182) {
 292                 if ((pmr & SIS_PMR_COMBINED) == 0) {
 293                         dev_printk(KERN_INFO, &pdev->dev,
 294                                    "Detected SiS 180/181 chipset in SATA mode\n");
 295                         port2_start = 64;
 296                 }
 297                 else {
 298                         dev_printk(KERN_INFO, &pdev->dev,
 299                                    "Detected SiS 180/181 chipset in combined mode\n");
 300                         port2_start=0;
 301                 }
 302         }
 303         else {
 304                 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182 chipset\n");
 305                 port2_start = 0x20;
 306         }
 307
 308         if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
 309                 probe_ent->port[0].scr_addr =
 310                         pci_resource_start(pdev, SIS_SCR_PCI_BAR);
 311                 probe_ent->port[1].scr_addr =
 312                         pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start;
 313         }
 314
 315         pci_set_master(pdev);
 316         pci_intx(pdev, 1);
 317
 318         /* FIXME: check ata_device_add return value */
 319         ata_device_add(probe_ent);
 320         kfree(probe_ent);
 321
 322         return 0;
 323
 324 err_out_regions:
 325         pci_release_regions(pdev);
 326
 327 err_out:
 328         if (!pci_dev_busy)
 329                 pci_disable_device(pdev);
 330         return rc;
 331
 332 }
 333
 334 static int __init sis_init(void)
 335 {
 336         return pci_module_init(&sis_pci_driver);
 337 }
 338
 339 static void __exit sis_exit(void)
 340 {
 341         pci_unregister_driver(&sis_pci_driver);
 342 }
 343
 344 module_init(sis_init);
 345 module_exit(sis_exit);
 346