1 /* arch/arm/plat-s3c64xx/irq-eint.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX - Interrupt handling for IRQ_EINT(x)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
20 #include <asm/hardware/vic.h>
22 #include <plat/regs-irqtype.h>
27 /* GPIO is 0x7F008xxx, */
28 #define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x))
30 #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
31 #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
32 #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
33 #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
34 #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
35 #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
37 #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
38 #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
41 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
42 #define eint_irq_to_bit(irq) (1 << eint_offset(irq))
44 static inline void s3c_irq_eint_mask(unsigned int irq
)
48 mask
= __raw_readl(S3C64XX_EINT0MASK
);
49 mask
|= eint_irq_to_bit(irq
);
50 __raw_writel(mask
, S3C64XX_EINT0MASK
);
53 static void s3c_irq_eint_unmask(unsigned int irq
)
57 mask
= __raw_readl(S3C64XX_EINT0MASK
);
58 mask
|= eint_irq_to_bit(irq
);
59 __raw_writel(mask
, S3C64XX_EINT0MASK
);
62 static inline void s3c_irq_eint_ack(unsigned int irq
)
64 __raw_writel(eint_irq_to_bit(irq
), S3C64XX_EINT0PEND
);
67 static void s3c_irq_eint_maskack(unsigned int irq
)
69 /* compiler should in-line these */
70 s3c_irq_eint_mask(irq
);
71 s3c_irq_eint_ack(irq
);
74 static int s3c_irq_eint_set_type(unsigned int irq
, unsigned int type
)
76 int offs
= eint_offset(irq
);
86 reg
= S3C64XX_EINT0CON0
;
88 reg
= S3C64XX_EINT0CON1
;
92 printk(KERN_WARNING
"No edge setting!\n");
95 case IRQ_TYPE_EDGE_RISING
:
96 newvalue
= S3C2410_EXTINT_RISEEDGE
;
99 case IRQ_TYPE_EDGE_FALLING
:
100 newvalue
= S3C2410_EXTINT_FALLEDGE
;
103 case IRQ_TYPE_EDGE_BOTH
:
104 newvalue
= S3C2410_EXTINT_BOTHEDGE
;
107 case IRQ_TYPE_LEVEL_LOW
:
108 newvalue
= S3C2410_EXTINT_LOWLEV
;
111 case IRQ_TYPE_LEVEL_HIGH
:
112 newvalue
= S3C2410_EXTINT_HILEV
;
116 printk(KERN_ERR
"No such irq type %d", type
);
120 shift
= (offs
/ 2) * 4;
123 ctrl
= __raw_readl(reg
);
125 ctrl
|= newvalue
<< shift
;
126 __raw_writel(ctrl
, reg
);
131 static struct irq_chip s3c_irq_eint
= {
133 .mask
= s3c_irq_eint_mask
,
134 .unmask
= s3c_irq_eint_unmask
,
135 .mask_ack
= s3c_irq_eint_maskack
,
136 .ack
= s3c_irq_eint_ack
,
137 .set_type
= s3c_irq_eint_set_type
,
140 /* s3c_irq_demux_eint
142 * This function demuxes the IRQ from the group0 external interrupts,
143 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
144 * the specific handlers s3c_irq_demux_eintX_Y.
146 static inline void s3c_irq_demux_eint(unsigned int start
, unsigned int end
)
148 u32 status
= __raw_readl(S3C64XX_EINT0PEND
);
149 u32 mask
= __raw_readl(S3C64XX_EINT0MASK
);
154 status
&= (1 << (end
- start
+ 1)) - 1;
156 for (irq
= IRQ_EINT(start
); irq
<= IRQ_EINT(end
); irq
++) {
158 generic_handle_irq(irq
);
164 static void s3c_irq_demux_eint0_3(unsigned int irq
, struct irq_desc
*desc
)
166 s3c_irq_demux_eint(0, 3);
169 static void s3c_irq_demux_eint4_11(unsigned int irq
, struct irq_desc
*desc
)
171 s3c_irq_demux_eint(4, 11);
174 static void s3c_irq_demux_eint12_19(unsigned int irq
, struct irq_desc
*desc
)
176 s3c_irq_demux_eint(12, 19);
179 static void s3c_irq_demux_eint20_27(unsigned int irq
, struct irq_desc
*desc
)
181 s3c_irq_demux_eint(20, 27);
184 int __init
s3c64xx_init_irq_eint(void)
188 for (irq
= IRQ_EINT(0); irq
<= IRQ_EINT(27); irq
++) {
189 set_irq_chip(irq
, &s3c_irq_eint
);
190 set_irq_handler(irq
, handle_level_irq
);
191 set_irq_flags(irq
, IRQF_VALID
);
194 set_irq_chained_handler(IRQ_EINT0_3
, s3c_irq_demux_eint0_3
);
195 set_irq_chained_handler(IRQ_EINT4_11
, s3c_irq_demux_eint4_11
);
196 set_irq_chained_handler(IRQ_EINT12_19
, s3c_irq_demux_eint12_19
);
197 set_irq_chained_handler(IRQ_EINT20_27
, s3c_irq_demux_eint20_27
);
202 arch_initcall(s3c64xx_init_irq_eint
);