2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/init.h>
39 #include <linux/kernel.h>
42 #include <linux/sched.h>
43 #include <linux/kernel_stat.h>
44 #include <linux/smp_lock.h>
45 #include <linux/bootmem.h>
46 #include <linux/notifier.h>
47 #include <linux/cpu.h>
48 #include <linux/percpu.h>
50 #include <linux/delay.h>
51 #include <linux/mc146818rtc.h>
52 #include <asm/tlbflush.h>
54 #include <asm/arch_hooks.h>
56 #include <mach_apic.h>
57 #include <mach_wakecpu.h>
58 #include <smpboot_hooks.h>
60 /* Set if we find a B stepping CPU */
61 static int __devinitdata smp_b_stepping
;
63 /* Number of siblings per CPU package */
64 int smp_num_siblings
= 1;
66 EXPORT_SYMBOL(smp_num_siblings
);
69 /* Package ID of each logical CPU */
70 int phys_proc_id
[NR_CPUS
] __read_mostly
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
72 /* Core ID of each logical CPU */
73 int cpu_core_id
[NR_CPUS
] __read_mostly
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
75 /* Last level cache ID of each logical CPU */
76 int cpu_llc_id
[NR_CPUS
] __cpuinitdata
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
78 /* representing HT siblings of each logical CPU */
79 cpumask_t cpu_sibling_map
[NR_CPUS
] __read_mostly
;
80 EXPORT_SYMBOL(cpu_sibling_map
);
82 /* representing HT and core siblings of each logical CPU */
83 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
;
84 EXPORT_SYMBOL(cpu_core_map
);
86 /* bitmap of online cpus */
87 cpumask_t cpu_online_map __read_mostly
;
88 EXPORT_SYMBOL(cpu_online_map
);
90 cpumask_t cpu_callin_map
;
91 cpumask_t cpu_callout_map
;
92 EXPORT_SYMBOL(cpu_callout_map
);
93 cpumask_t cpu_possible_map
;
94 EXPORT_SYMBOL(cpu_possible_map
);
95 static cpumask_t smp_commenced_mask
;
97 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
98 * is no way to resync one AP against BP. TBD: for prescott and above, we
99 * should use IA64's algorithm
101 static int __devinitdata tsc_sync_disabled
;
103 /* Per CPU bogomips and other parameters */
104 struct cpuinfo_x86 cpu_data
[NR_CPUS
] __cacheline_aligned
;
105 EXPORT_SYMBOL(cpu_data
);
107 u8 x86_cpu_to_apicid
[NR_CPUS
] __read_mostly
=
108 { [0 ... NR_CPUS
-1] = 0xff };
109 EXPORT_SYMBOL(x86_cpu_to_apicid
);
112 * Trampoline 80x86 program as an array.
115 extern unsigned char trampoline_data
[];
116 extern unsigned char trampoline_end
[];
117 static unsigned char *trampoline_base
;
118 static int trampoline_exec
;
120 static void map_cpu_to_logical_apicid(void);
122 /* State of each CPU. */
123 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
126 * Currently trivial. Write the real->protected mode
127 * bootstrap into the page concerned. The caller
128 * has made sure it's suitably aligned.
131 static unsigned long __devinit
setup_trampoline(void)
133 memcpy(trampoline_base
, trampoline_data
, trampoline_end
- trampoline_data
);
134 return virt_to_phys(trampoline_base
);
138 * We are called very early to get the low memory for the
139 * SMP bootup trampoline page.
141 void __init
smp_alloc_memory(void)
143 trampoline_base
= (void *) alloc_bootmem_low_pages(PAGE_SIZE
);
145 * Has to be in very low memory so we can execute
148 if (__pa(trampoline_base
) >= 0x9F000)
151 * Make the SMP trampoline executable:
153 trampoline_exec
= set_kernel_exec((unsigned long)trampoline_base
, 1);
157 * The bootstrap kernel entry code has set these up. Save them for
161 static void __devinit
smp_store_cpu_info(int id
)
163 struct cpuinfo_x86
*c
= cpu_data
+ id
;
169 * Mask B, Pentium, but not Pentium MMX
171 if (c
->x86_vendor
== X86_VENDOR_INTEL
&&
173 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
176 * Remember we have B step Pentia with bugs
181 * Certain Athlons might work (for various values of 'work') in SMP
182 * but they are not certified as MP capable.
184 if ((c
->x86_vendor
== X86_VENDOR_AMD
) && (c
->x86
== 6)) {
186 /* Athlon 660/661 is valid. */
187 if ((c
->x86_model
==6) && ((c
->x86_mask
==0) || (c
->x86_mask
==1)))
190 /* Duron 670 is valid */
191 if ((c
->x86_model
==7) && (c
->x86_mask
==0))
195 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
196 * It's worth noting that the A5 stepping (662) of some Athlon XP's
197 * have the MP bit set.
198 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
200 if (((c
->x86_model
==6) && (c
->x86_mask
>=2)) ||
201 ((c
->x86_model
==7) && (c
->x86_mask
>=1)) ||
206 /* If we get here, it's not a certified SMP capable AMD system. */
207 add_taint(TAINT_UNSAFE_SMP
);
215 * TSC synchronization.
217 * We first check whether all CPUs have their TSC's synchronized,
218 * then we print a warning if not, and always resync.
221 static atomic_t tsc_start_flag
= ATOMIC_INIT(0);
222 static atomic_t tsc_count_start
= ATOMIC_INIT(0);
223 static atomic_t tsc_count_stop
= ATOMIC_INIT(0);
224 static unsigned long long tsc_values
[NR_CPUS
];
228 static void __init
synchronize_tsc_bp (void)
231 unsigned long long t0
;
232 unsigned long long sum
, avg
;
234 unsigned int one_usec
;
237 printk(KERN_INFO
"checking TSC synchronization across %u CPUs: ", num_booting_cpus());
239 /* convert from kcyc/sec to cyc/usec */
240 one_usec
= cpu_khz
/ 1000;
242 atomic_set(&tsc_start_flag
, 1);
246 * We loop a few times to get a primed instruction cache,
247 * then the last pass is more or less synchronized and
248 * the BP and APs set their cycle counters to zero all at
249 * once. This reduces the chance of having random offsets
250 * between the processors, and guarantees that the maximum
251 * delay between the cycle counters is never bigger than
252 * the latency of information-passing (cachelines) between
255 for (i
= 0; i
< NR_LOOPS
; i
++) {
257 * all APs synchronize but they loop on '== num_cpus'
259 while (atomic_read(&tsc_count_start
) != num_booting_cpus()-1)
261 atomic_set(&tsc_count_stop
, 0);
264 * this lets the APs save their current TSC:
266 atomic_inc(&tsc_count_start
);
268 rdtscll(tsc_values
[smp_processor_id()]);
270 * We clear the TSC in the last loop:
276 * Wait for all APs to leave the synchronization point:
278 while (atomic_read(&tsc_count_stop
) != num_booting_cpus()-1)
280 atomic_set(&tsc_count_start
, 0);
282 atomic_inc(&tsc_count_stop
);
286 for (i
= 0; i
< NR_CPUS
; i
++) {
287 if (cpu_isset(i
, cpu_callout_map
)) {
293 do_div(avg
, num_booting_cpus());
296 for (i
= 0; i
< NR_CPUS
; i
++) {
297 if (!cpu_isset(i
, cpu_callout_map
))
299 delta
= tsc_values
[i
] - avg
;
303 * We report bigger than 2 microseconds clock differences.
305 if (delta
> 2*one_usec
) {
312 do_div(realdelta
, one_usec
);
313 if (tsc_values
[i
] < avg
)
314 realdelta
= -realdelta
;
317 printk(KERN_INFO
"CPU#%d had %ld usecs TSC "
318 "skew, fixed it up.\n", i
, realdelta
);
327 static void __init
synchronize_tsc_ap (void)
332 * Not every cpu is online at the time
333 * this gets called, so we first wait for the BP to
334 * finish SMP initialization:
336 while (!atomic_read(&tsc_start_flag
)) mb();
338 for (i
= 0; i
< NR_LOOPS
; i
++) {
339 atomic_inc(&tsc_count_start
);
340 while (atomic_read(&tsc_count_start
) != num_booting_cpus())
343 rdtscll(tsc_values
[smp_processor_id()]);
347 atomic_inc(&tsc_count_stop
);
348 while (atomic_read(&tsc_count_stop
) != num_booting_cpus()) mb();
353 extern void calibrate_delay(void);
355 static atomic_t init_deasserted
;
357 static void __devinit
smp_callin(void)
360 unsigned long timeout
;
363 * If waken up by an INIT in an 82489DX configuration
364 * we may get here before an INIT-deassert IPI reaches
365 * our local APIC. We have to wait for the IPI or we'll
366 * lock up on an APIC access.
368 wait_for_init_deassert(&init_deasserted
);
371 * (This works even if the APIC is not enabled.)
373 phys_id
= GET_APIC_ID(apic_read(APIC_ID
));
374 cpuid
= smp_processor_id();
375 if (cpu_isset(cpuid
, cpu_callin_map
)) {
376 printk("huh, phys CPU#%d, CPU#%d already present??\n",
380 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
383 * STARTUP IPIs are fragile beasts as they might sometimes
384 * trigger some glue motherboard logic. Complete APIC bus
385 * silence for 1 second, this overestimates the time the
386 * boot CPU is spending to send the up to 2 STARTUP IPIs
387 * by a factor of two. This should be enough.
391 * Waiting 2s total for startup (udelay is not yet working)
393 timeout
= jiffies
+ 2*HZ
;
394 while (time_before(jiffies
, timeout
)) {
396 * Has the boot CPU finished it's STARTUP sequence?
398 if (cpu_isset(cpuid
, cpu_callout_map
))
403 if (!time_before(jiffies
, timeout
)) {
404 printk("BUG: CPU%d started up but did not get a callout!\n",
410 * the boot CPU has finished the init stage and is spinning
411 * on callin_map until we finish. We are free to set up this
412 * CPU, first the APIC. (this is probably redundant on most
416 Dprintk("CALLIN, before setup_local_APIC().\n");
417 smp_callin_clear_local_apic();
419 map_cpu_to_logical_apicid();
425 Dprintk("Stack at about %p\n",&cpuid
);
428 * Save our processor parameters
430 smp_store_cpu_info(cpuid
);
432 disable_APIC_timer();
435 * Allow the master to continue.
437 cpu_set(cpuid
, cpu_callin_map
);
440 * Synchronize the TSC with the BP
442 if (cpu_has_tsc
&& cpu_khz
&& !tsc_sync_disabled
)
443 synchronize_tsc_ap();
448 /* maps the cpu to the sched domain representing multi-core */
449 cpumask_t
cpu_coregroup_map(int cpu
)
451 struct cpuinfo_x86
*c
= cpu_data
+ cpu
;
453 * For perf, we return last level cache shared map.
454 * TBD: when power saving sched policy is added, we will return
455 * cpu_core_map when power saving policy is enabled
457 return c
->llc_shared_map
;
460 /* representing cpus for which sibling maps can be computed */
461 static cpumask_t cpu_sibling_setup_map
;
464 set_cpu_sibling_map(int cpu
)
467 struct cpuinfo_x86
*c
= cpu_data
;
469 cpu_set(cpu
, cpu_sibling_setup_map
);
471 if (smp_num_siblings
> 1) {
472 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
473 if (phys_proc_id
[cpu
] == phys_proc_id
[i
] &&
474 cpu_core_id
[cpu
] == cpu_core_id
[i
]) {
475 cpu_set(i
, cpu_sibling_map
[cpu
]);
476 cpu_set(cpu
, cpu_sibling_map
[i
]);
477 cpu_set(i
, cpu_core_map
[cpu
]);
478 cpu_set(cpu
, cpu_core_map
[i
]);
479 cpu_set(i
, c
[cpu
].llc_shared_map
);
480 cpu_set(cpu
, c
[i
].llc_shared_map
);
484 cpu_set(cpu
, cpu_sibling_map
[cpu
]);
487 cpu_set(cpu
, c
[cpu
].llc_shared_map
);
489 if (current_cpu_data
.x86_max_cores
== 1) {
490 cpu_core_map
[cpu
] = cpu_sibling_map
[cpu
];
491 c
[cpu
].booted_cores
= 1;
495 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
496 if (cpu_llc_id
[cpu
] != BAD_APICID
&&
497 cpu_llc_id
[cpu
] == cpu_llc_id
[i
]) {
498 cpu_set(i
, c
[cpu
].llc_shared_map
);
499 cpu_set(cpu
, c
[i
].llc_shared_map
);
501 if (phys_proc_id
[cpu
] == phys_proc_id
[i
]) {
502 cpu_set(i
, cpu_core_map
[cpu
]);
503 cpu_set(cpu
, cpu_core_map
[i
]);
505 * Does this new cpu bringup a new core?
507 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1) {
509 * for each core in package, increment
510 * the booted_cores for this new cpu
512 if (first_cpu(cpu_sibling_map
[i
]) == i
)
513 c
[cpu
].booted_cores
++;
515 * increment the core count for all
516 * the other cpus in this package
520 } else if (i
!= cpu
&& !c
[cpu
].booted_cores
)
521 c
[cpu
].booted_cores
= c
[i
].booted_cores
;
527 * Activate a secondary processor.
529 static void __devinit
start_secondary(void *unused
)
532 * Dont put anything before smp_callin(), SMP
533 * booting is too fragile that we want to limit the
534 * things done here to the most necessary things.
539 while (!cpu_isset(smp_processor_id(), smp_commenced_mask
))
541 setup_secondary_APIC_clock();
542 if (nmi_watchdog
== NMI_IO_APIC
) {
543 disable_8259A_irq(0);
544 enable_NMI_through_LVT0(NULL
);
549 * low-memory mappings have been cleared, flush them from
550 * the local TLBs too.
554 /* This must be done before setting cpu_online_map */
555 set_cpu_sibling_map(raw_smp_processor_id());
559 * We need to hold call_lock, so there is no inconsistency
560 * between the time smp_call_function() determines number of
561 * IPI receipients, and the time when the determination is made
562 * for which cpus receive the IPI. Holding this
563 * lock helps us to not include this cpu in a currently in progress
564 * smp_call_function().
566 lock_ipi_call_lock();
567 cpu_set(smp_processor_id(), cpu_online_map
);
568 unlock_ipi_call_lock();
569 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
571 /* We can take interrupts now: we're officially "up". */
579 * Everything has been set up for the secondary
580 * CPUs - they just need to reload everything
581 * from the task structure
582 * This function must not return.
584 void __devinit
initialize_secondary(void)
587 * We don't actually need to load the full TSS,
588 * basically just the stack pointer and the eip.
595 :"r" (current
->thread
.esp
),"r" (current
->thread
.eip
));
605 /* which logical CPUs are on which nodes */
606 cpumask_t node_2_cpu_mask
[MAX_NUMNODES
] __read_mostly
=
607 { [0 ... MAX_NUMNODES
-1] = CPU_MASK_NONE
};
608 /* which node each logical CPU is on */
609 int cpu_2_node
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = 0 };
610 EXPORT_SYMBOL(cpu_2_node
);
612 /* set up a mapping between cpu and node. */
613 static inline void map_cpu_to_node(int cpu
, int node
)
615 printk("Mapping cpu %d to node %d\n", cpu
, node
);
616 cpu_set(cpu
, node_2_cpu_mask
[node
]);
617 cpu_2_node
[cpu
] = node
;
620 /* undo a mapping between cpu and node. */
621 static inline void unmap_cpu_to_node(int cpu
)
625 printk("Unmapping cpu %d from all nodes\n", cpu
);
626 for (node
= 0; node
< MAX_NUMNODES
; node
++)
627 cpu_clear(cpu
, node_2_cpu_mask
[node
]);
630 #else /* !CONFIG_NUMA */
632 #define map_cpu_to_node(cpu, node) ({})
633 #define unmap_cpu_to_node(cpu) ({})
635 #endif /* CONFIG_NUMA */
637 u8 cpu_2_logical_apicid
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = BAD_APICID
};
639 static void map_cpu_to_logical_apicid(void)
641 int cpu
= smp_processor_id();
642 int apicid
= logical_smp_processor_id();
644 cpu_2_logical_apicid
[cpu
] = apicid
;
645 map_cpu_to_node(cpu
, apicid_to_node(apicid
));
648 static void unmap_cpu_to_logical_apicid(int cpu
)
650 cpu_2_logical_apicid
[cpu
] = BAD_APICID
;
651 unmap_cpu_to_node(cpu
);
655 static inline void __inquire_remote_apic(int apicid
)
657 int i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
658 char *names
[] = { "ID", "VERSION", "SPIV" };
661 printk("Inquiring remote APIC #%d...\n", apicid
);
663 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
664 printk("... APIC #%d %s: ", apicid
, names
[i
]);
669 apic_wait_icr_idle();
671 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(apicid
));
672 apic_write_around(APIC_ICR
, APIC_DM_REMRD
| regs
[i
]);
677 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
678 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
681 case APIC_ICR_RR_VALID
:
682 status
= apic_read(APIC_RRR
);
683 printk("%08x\n", status
);
692 #ifdef WAKE_SECONDARY_VIA_NMI
694 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
695 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
696 * won't ... remember to clear down the APIC, etc later.
699 wakeup_secondary_cpu(int logical_apicid
, unsigned long start_eip
)
701 unsigned long send_status
= 0, accept_status
= 0;
705 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(logical_apicid
));
707 /* Boot on the stack */
708 /* Kick the second */
709 apic_write_around(APIC_ICR
, APIC_DM_NMI
| APIC_DEST_LOGICAL
);
711 Dprintk("Waiting for send to finish...\n");
716 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
717 } while (send_status
&& (timeout
++ < 1000));
720 * Give the other CPU some time to accept the IPI.
724 * Due to the Pentium erratum 3AP.
726 maxlvt
= get_maxlvt();
728 apic_read_around(APIC_SPIV
);
729 apic_write(APIC_ESR
, 0);
731 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
732 Dprintk("NMI sent.\n");
735 printk("APIC never delivered???\n");
737 printk("APIC delivery error (%lx).\n", accept_status
);
739 return (send_status
| accept_status
);
741 #endif /* WAKE_SECONDARY_VIA_NMI */
743 #ifdef WAKE_SECONDARY_VIA_INIT
745 wakeup_secondary_cpu(int phys_apicid
, unsigned long start_eip
)
747 unsigned long send_status
= 0, accept_status
= 0;
748 int maxlvt
, timeout
, num_starts
, j
;
751 * Be paranoid about clearing APIC errors.
753 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
754 apic_read_around(APIC_SPIV
);
755 apic_write(APIC_ESR
, 0);
759 Dprintk("Asserting INIT.\n");
762 * Turn INIT on target chip
764 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
769 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
772 Dprintk("Waiting for send to finish...\n");
777 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
778 } while (send_status
&& (timeout
++ < 1000));
782 Dprintk("Deasserting INIT.\n");
785 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
788 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
790 Dprintk("Waiting for send to finish...\n");
795 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
796 } while (send_status
&& (timeout
++ < 1000));
798 atomic_set(&init_deasserted
, 1);
801 * Should we send STARTUP IPIs ?
803 * Determine this based on the APIC version.
804 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
806 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
812 * Run STARTUP IPI loop.
814 Dprintk("#startup loops: %d.\n", num_starts
);
816 maxlvt
= get_maxlvt();
818 for (j
= 1; j
<= num_starts
; j
++) {
819 Dprintk("Sending STARTUP #%d.\n",j
);
820 apic_read_around(APIC_SPIV
);
821 apic_write(APIC_ESR
, 0);
823 Dprintk("After apic_write.\n");
830 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
832 /* Boot on the stack */
833 /* Kick the second */
834 apic_write_around(APIC_ICR
, APIC_DM_STARTUP
835 | (start_eip
>> 12));
838 * Give the other CPU some time to accept the IPI.
842 Dprintk("Startup point 1.\n");
844 Dprintk("Waiting for send to finish...\n");
849 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
850 } while (send_status
&& (timeout
++ < 1000));
853 * Give the other CPU some time to accept the IPI.
857 * Due to the Pentium erratum 3AP.
860 apic_read_around(APIC_SPIV
);
861 apic_write(APIC_ESR
, 0);
863 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
864 if (send_status
|| accept_status
)
867 Dprintk("After Startup.\n");
870 printk("APIC never delivered???\n");
872 printk("APIC delivery error (%lx).\n", accept_status
);
874 return (send_status
| accept_status
);
876 #endif /* WAKE_SECONDARY_VIA_INIT */
878 extern cpumask_t cpu_initialized
;
879 static inline int alloc_cpu_id(void)
883 cpus_complement(tmp_map
, cpu_present_map
);
884 cpu
= first_cpu(tmp_map
);
890 #ifdef CONFIG_HOTPLUG_CPU
891 static struct task_struct
* __devinitdata cpu_idle_tasks
[NR_CPUS
];
892 static inline struct task_struct
* alloc_idle_task(int cpu
)
894 struct task_struct
*idle
;
896 if ((idle
= cpu_idle_tasks
[cpu
]) != NULL
) {
897 /* initialize thread_struct. we really want to avoid destroy
900 idle
->thread
.esp
= (unsigned long)task_pt_regs(idle
);
901 init_idle(idle
, cpu
);
904 idle
= fork_idle(cpu
);
907 cpu_idle_tasks
[cpu
] = idle
;
911 #define alloc_idle_task(cpu) fork_idle(cpu)
914 static int __devinit
do_boot_cpu(int apicid
, int cpu
)
916 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
917 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
918 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
921 struct task_struct
*idle
;
922 unsigned long boot_error
;
924 unsigned long start_eip
;
925 unsigned short nmi_high
= 0, nmi_low
= 0;
928 alternatives_smp_switch(1);
931 * We can't use kernel_thread since we must avoid to
932 * reschedule the child.
934 idle
= alloc_idle_task(cpu
);
936 panic("failed fork for CPU %d", cpu
);
937 idle
->thread
.eip
= (unsigned long) start_secondary
;
938 /* start_eip had better be page-aligned! */
939 start_eip
= setup_trampoline();
941 /* So we see what's up */
942 printk("Booting processor %d/%d eip %lx\n", cpu
, apicid
, start_eip
);
943 /* Stack for startup_32 can be just as for start_secondary onwards */
944 stack_start
.esp
= (void *) idle
->thread
.esp
;
949 * This grunge runs the startup process for
950 * the targeted processor.
953 atomic_set(&init_deasserted
, 0);
955 Dprintk("Setting warm reset code and vector.\n");
957 store_NMI_vector(&nmi_high
, &nmi_low
);
959 smpboot_setup_warm_reset_vector(start_eip
);
962 * Starting actual IPI sequence...
964 boot_error
= wakeup_secondary_cpu(apicid
, start_eip
);
968 * allow APs to start initializing.
970 Dprintk("Before Callout %d.\n", cpu
);
971 cpu_set(cpu
, cpu_callout_map
);
972 Dprintk("After Callout %d.\n", cpu
);
975 * Wait 5s total for a response
977 for (timeout
= 0; timeout
< 50000; timeout
++) {
978 if (cpu_isset(cpu
, cpu_callin_map
))
979 break; /* It has booted */
983 if (cpu_isset(cpu
, cpu_callin_map
)) {
984 /* number CPUs logically, starting from 1 (BSP is 0) */
986 printk("CPU%d: ", cpu
);
987 print_cpu_info(&cpu_data
[cpu
]);
988 Dprintk("CPU has booted.\n");
991 if (*((volatile unsigned char *)trampoline_base
)
993 /* trampoline started but...? */
994 printk("Stuck ??\n");
996 /* trampoline code not run */
997 printk("Not responding.\n");
998 inquire_remote_apic(apicid
);
1003 /* Try to put things back the way they were before ... */
1004 unmap_cpu_to_logical_apicid(cpu
);
1005 cpu_clear(cpu
, cpu_callout_map
); /* was set here (do_boot_cpu()) */
1006 cpu_clear(cpu
, cpu_initialized
); /* was set by cpu_init() */
1009 x86_cpu_to_apicid
[cpu
] = apicid
;
1010 cpu_set(cpu
, cpu_present_map
);
1013 /* mark "stuck" area as not stuck */
1014 *((volatile unsigned long *)trampoline_base
) = 0;
1019 #ifdef CONFIG_HOTPLUG_CPU
1020 void cpu_exit_clear(void)
1022 int cpu
= raw_smp_processor_id();
1030 cpu_clear(cpu
, cpu_callout_map
);
1031 cpu_clear(cpu
, cpu_callin_map
);
1033 cpu_clear(cpu
, smp_commenced_mask
);
1034 unmap_cpu_to_logical_apicid(cpu
);
1037 struct warm_boot_cpu_info
{
1038 struct completion
*complete
;
1043 static void __cpuinit
do_warm_boot_cpu(void *p
)
1045 struct warm_boot_cpu_info
*info
= p
;
1046 do_boot_cpu(info
->apicid
, info
->cpu
);
1047 complete(info
->complete
);
1050 static int __cpuinit
__smp_prepare_cpu(int cpu
)
1052 DECLARE_COMPLETION(done
);
1053 struct warm_boot_cpu_info info
;
1054 struct work_struct task
;
1057 apicid
= x86_cpu_to_apicid
[cpu
];
1058 if (apicid
== BAD_APICID
) {
1063 info
.complete
= &done
;
1064 info
.apicid
= apicid
;
1066 INIT_WORK(&task
, do_warm_boot_cpu
, &info
);
1068 tsc_sync_disabled
= 1;
1070 /* init low mem mapping */
1071 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ USER_PGD_PTRS
,
1074 schedule_work(&task
);
1075 wait_for_completion(&done
);
1077 tsc_sync_disabled
= 0;
1085 static void smp_tune_scheduling (void)
1087 unsigned long cachesize
; /* kB */
1088 unsigned long bandwidth
= 350; /* MB/s */
1090 * Rough estimation for SMP scheduling, this is the number of
1091 * cycles it takes for a fully memory-limited process to flush
1092 * the SMP-local cache.
1094 * (For a P5 this pretty much means we will choose another idle
1095 * CPU almost always at wakeup time (this is due to the small
1096 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1102 * this basically disables processor-affinity
1103 * scheduling on SMP without a TSC.
1107 cachesize
= boot_cpu_data
.x86_cache_size
;
1108 if (cachesize
== -1) {
1109 cachesize
= 16; /* Pentiums, 2x8kB cache */
1112 max_cache_size
= cachesize
* 1024;
1117 * Cycle through the processors sending APIC IPIs to boot each.
1120 static int boot_cpu_logical_apicid
;
1121 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1123 #ifdef CONFIG_X86_NUMAQ
1124 EXPORT_SYMBOL(xquad_portio
);
1127 static void __init
smp_boot_cpus(unsigned int max_cpus
)
1129 int apicid
, cpu
, bit
, kicked
;
1130 unsigned long bogosum
= 0;
1133 * Setup boot CPU information
1135 smp_store_cpu_info(0); /* Final full version of the data */
1136 printk("CPU%d: ", 0);
1137 print_cpu_info(&cpu_data
[0]);
1139 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1140 boot_cpu_logical_apicid
= logical_smp_processor_id();
1141 x86_cpu_to_apicid
[0] = boot_cpu_physical_apicid
;
1143 current_thread_info()->cpu
= 0;
1144 smp_tune_scheduling();
1146 set_cpu_sibling_map(0);
1149 * If we couldn't find an SMP configuration at boot time,
1150 * get out of here now!
1152 if (!smp_found_config
&& !acpi_lapic
) {
1153 printk(KERN_NOTICE
"SMP motherboard not detected.\n");
1154 smpboot_clear_io_apic_irqs();
1155 phys_cpu_present_map
= physid_mask_of_physid(0);
1156 if (APIC_init_uniprocessor())
1157 printk(KERN_NOTICE
"Local APIC not detected."
1158 " Using dummy APIC emulation.\n");
1159 map_cpu_to_logical_apicid();
1160 cpu_set(0, cpu_sibling_map
[0]);
1161 cpu_set(0, cpu_core_map
[0]);
1166 * Should not be necessary because the MP table should list the boot
1167 * CPU too, but we do it for the sake of robustness anyway.
1168 * Makes no sense to do this check in clustered apic mode, so skip it
1170 if (!check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1171 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1172 boot_cpu_physical_apicid
);
1173 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1177 * If we couldn't find a local APIC, then get out of here now!
1179 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) && !cpu_has_apic
) {
1180 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1181 boot_cpu_physical_apicid
);
1182 printk(KERN_ERR
"... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1183 smpboot_clear_io_apic_irqs();
1184 phys_cpu_present_map
= physid_mask_of_physid(0);
1185 cpu_set(0, cpu_sibling_map
[0]);
1186 cpu_set(0, cpu_core_map
[0]);
1190 verify_local_APIC();
1193 * If SMP should be disabled, then really disable it!
1196 smp_found_config
= 0;
1197 printk(KERN_INFO
"SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1198 smpboot_clear_io_apic_irqs();
1199 phys_cpu_present_map
= physid_mask_of_physid(0);
1200 cpu_set(0, cpu_sibling_map
[0]);
1201 cpu_set(0, cpu_core_map
[0]);
1207 map_cpu_to_logical_apicid();
1210 setup_portio_remap();
1213 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1215 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1216 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1217 * clustered apic ID.
1219 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map
));
1222 for (bit
= 0; kicked
< NR_CPUS
&& bit
< MAX_APICS
; bit
++) {
1223 apicid
= cpu_present_to_apicid(bit
);
1225 * Don't even attempt to start the boot CPU!
1227 if ((apicid
== boot_cpu_apicid
) || (apicid
== BAD_APICID
))
1230 if (!check_apicid_present(bit
))
1232 if (max_cpus
<= cpucount
+1)
1235 if (((cpu
= alloc_cpu_id()) <= 0) || do_boot_cpu(apicid
, cpu
))
1236 printk("CPU #%d not responding - cannot use it.\n",
1243 * Cleanup possible dangling ends...
1245 smpboot_restore_warm_reset_vector();
1248 * Allow the user to impress friends.
1250 Dprintk("Before bogomips.\n");
1251 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++)
1252 if (cpu_isset(cpu
, cpu_callout_map
))
1253 bogosum
+= cpu_data
[cpu
].loops_per_jiffy
;
1255 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1257 bogosum
/(500000/HZ
),
1258 (bogosum
/(5000/HZ
))%100);
1260 Dprintk("Before bogocount - setting activated=1.\n");
1263 printk(KERN_WARNING
"WARNING: SMP operation may be unreliable with B stepping processors.\n");
1266 * Don't taint if we are running SMP kernel on a single non-MP
1269 if (tainted
& TAINT_UNSAFE_SMP
) {
1271 printk (KERN_INFO
"WARNING: This combination of AMD processors is not suitable for SMP.\n");
1273 tainted
&= ~TAINT_UNSAFE_SMP
;
1276 Dprintk("Boot done.\n");
1279 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1282 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
1283 cpus_clear(cpu_sibling_map
[cpu
]);
1284 cpus_clear(cpu_core_map
[cpu
]);
1287 cpu_set(0, cpu_sibling_map
[0]);
1288 cpu_set(0, cpu_core_map
[0]);
1290 smpboot_setup_io_apic();
1292 setup_boot_APIC_clock();
1295 * Synchronize the TSC with the AP
1297 if (cpu_has_tsc
&& cpucount
&& cpu_khz
)
1298 synchronize_tsc_bp();
1301 /* These are wrappers to interface to the new boot process. Someone
1302 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1303 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1305 smp_commenced_mask
= cpumask_of_cpu(0);
1306 cpu_callin_map
= cpumask_of_cpu(0);
1308 smp_boot_cpus(max_cpus
);
1311 void __devinit
smp_prepare_boot_cpu(void)
1313 cpu_set(smp_processor_id(), cpu_online_map
);
1314 cpu_set(smp_processor_id(), cpu_callout_map
);
1315 cpu_set(smp_processor_id(), cpu_present_map
);
1316 cpu_set(smp_processor_id(), cpu_possible_map
);
1317 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
1320 #ifdef CONFIG_HOTPLUG_CPU
1322 remove_siblinginfo(int cpu
)
1325 struct cpuinfo_x86
*c
= cpu_data
;
1327 for_each_cpu_mask(sibling
, cpu_core_map
[cpu
]) {
1328 cpu_clear(cpu
, cpu_core_map
[sibling
]);
1330 * last thread sibling in this cpu core going down
1332 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1)
1333 c
[sibling
].booted_cores
--;
1336 for_each_cpu_mask(sibling
, cpu_sibling_map
[cpu
])
1337 cpu_clear(cpu
, cpu_sibling_map
[sibling
]);
1338 cpus_clear(cpu_sibling_map
[cpu
]);
1339 cpus_clear(cpu_core_map
[cpu
]);
1340 phys_proc_id
[cpu
] = BAD_APICID
;
1341 cpu_core_id
[cpu
] = BAD_APICID
;
1342 cpu_clear(cpu
, cpu_sibling_setup_map
);
1345 int __cpu_disable(void)
1347 cpumask_t map
= cpu_online_map
;
1348 int cpu
= smp_processor_id();
1351 * Perhaps use cpufreq to drop frequency, but that could go
1352 * into generic code.
1354 * We won't take down the boot processor on i386 due to some
1355 * interrupts only being able to be serviced by the BSP.
1356 * Especially so if we're not using an IOAPIC -zwane
1362 /* Allow any queued timer interrupts to get serviced */
1365 local_irq_disable();
1367 remove_siblinginfo(cpu
);
1369 cpu_clear(cpu
, map
);
1371 /* It's now safe to remove this processor from the online map */
1372 cpu_clear(cpu
, cpu_online_map
);
1376 void __cpu_die(unsigned int cpu
)
1378 /* We don't do anything here: idle task is faking death itself. */
1381 for (i
= 0; i
< 10; i
++) {
1382 /* They ack this in play_dead by setting CPU_DEAD */
1383 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1384 printk ("CPU %d is now offline\n", cpu
);
1385 if (1 == num_online_cpus())
1386 alternatives_smp_switch(0);
1391 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1393 #else /* ... !CONFIG_HOTPLUG_CPU */
1394 int __cpu_disable(void)
1399 void __cpu_die(unsigned int cpu
)
1401 /* We said "no" in __cpu_disable */
1404 #endif /* CONFIG_HOTPLUG_CPU */
1406 int __devinit
__cpu_up(unsigned int cpu
)
1408 #ifdef CONFIG_HOTPLUG_CPU
1412 * We do warm boot only on cpus that had booted earlier
1413 * Otherwise cold boot is all handled from smp_boot_cpus().
1414 * cpu_callin_map is set during AP kickstart process. Its reset
1415 * when a cpu is taken offline from cpu_exit_clear().
1417 if (!cpu_isset(cpu
, cpu_callin_map
))
1418 ret
= __smp_prepare_cpu(cpu
);
1424 /* In case one didn't come up */
1425 if (!cpu_isset(cpu
, cpu_callin_map
)) {
1426 printk(KERN_DEBUG
"skipping cpu%d, didn't come online\n", cpu
);
1432 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
1433 /* Unleash the CPU! */
1434 cpu_set(cpu
, smp_commenced_mask
);
1435 while (!cpu_isset(cpu
, cpu_online_map
))
1440 void __init
smp_cpus_done(unsigned int max_cpus
)
1442 #ifdef CONFIG_X86_IO_APIC
1443 setup_ioapic_dest();
1446 #ifndef CONFIG_HOTPLUG_CPU
1448 * Disable executability of the SMP trampoline:
1450 set_kernel_exec((unsigned long)trampoline_base
, trampoline_exec
);
1454 void __init
smp_intr_init(void)
1457 * IRQ0 must be given a fixed assignment and initialized,
1458 * because it's used before the IO-APIC is set up.
1460 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1463 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1464 * IPI, driven by wakeup.
1466 set_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1468 /* IPI for invalidation */
1469 set_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1471 /* IPI for generic function call */
1472 set_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);