drivers/staging/me4000/me4000.h

   1 /*
   2  * Copyright (C) 2003 Meilhaus Electronic GmbH (support@meilhaus.de)
   3  *
   4  * Source File : me4000.h
   5  * Author      : GG (Guenter Gebhardt)  <g.gebhardt@meilhaus.de>
   6  */
   7
   8 #ifndef _ME4000_H_
   9 #define _ME4000_H_
  10
  11 #ifdef __KERNEL__
  12
  13 /*=============================================================================
  14   The version of the driver release
  15   ===========================================================================*/
  16
  17 #define ME4000_DRIVER_VERSION  0x10009  // Version 1.00.09
  18
  19 /*=============================================================================
  20   Debug section
  21   ===========================================================================*/
  22
  23 #undef ME4000_CALL_DEBUG        // Debug function entry and exit
  24 #undef ME4000_ISR_DEBUG         // Debug the interrupt service routine
  25 #undef ME4000_PORT_DEBUG        // Debug port access
  26 #undef ME4000_DEBUG             // General purpose debug masseges
  27
  28 #ifdef ME4000_CALL_DEBUG
  29 #undef CALL_PDEBUG
  30 #define CALL_PDEBUG(fmt, args...) printk(KERN_DEBUG"ME4000:" fmt, ##args)
  31 #else
  32 # define CALL_PDEBUG(fmt, args...)      // no debugging, do nothing
  33 #endif
  34
  35 #ifdef ME4000_ISR_DEBUG
  36 #undef ISR_PDEBUG
  37 #define ISR_PDEBUG(fmt, args...) printk(KERN_DEBUG"ME4000:" fmt, ##args)
  38 #else
  39 #define ISR_PDEBUG(fmt, args...)        // no debugging, do nothing
  40 #endif
  41
  42 #ifdef ME4000_PORT_DEBUG
  43 #undef PORT_PDEBUG
  44 #define PORT_PDEBUG(fmt, args...) printk(KERN_DEBUG"ME4000:" fmt, ##args)
  45 #else
  46 #define PORT_PDEBUG(fmt, args...)       // no debugging, do nothing
  47 #endif
  48
  49 #ifdef ME4000_DEBUG
  50 #undef PDEBUG
  51 #define PDEBUG(fmt, args...) printk(KERN_DEBUG"ME4000:" fmt, ##args)
  52 #else
  53 #define PDEBUG(fmt, args...)    // no debugging, do nothing
  54 #endif
  55
  56 /*=============================================================================
  57   PCI vendor and device IDs
  58   ===========================================================================*/
  59
  60 #define PCI_VENDOR_ID_MEILHAUS 0x1402
  61
  62 #define PCI_DEVICE_ID_MEILHAUS_ME4650   0x4650  // Low Cost version
  63
  64 #define PCI_DEVICE_ID_MEILHAUS_ME4660   0x4660  // Standard version
  65 #define PCI_DEVICE_ID_MEILHAUS_ME4660I  0x4661  // Isolated version
  66 #define PCI_DEVICE_ID_MEILHAUS_ME4660S  0x4662  // Standard version with Sample and Hold
  67 #define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663  // Isolated version with Sample and Hold
  68
  69 #define PCI_DEVICE_ID_MEILHAUS_ME4670   0x4670  // Standard version
  70 #define PCI_DEVICE_ID_MEILHAUS_ME4670I  0x4671  // Isolated version
  71 #define PCI_DEVICE_ID_MEILHAUS_ME4670S  0x4672  // Standard version with Sample and Hold
  72 #define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673  // Isolated version with Sample and Hold
  73
  74 #define PCI_DEVICE_ID_MEILHAUS_ME4680   0x4680  // Standard version
  75 #define PCI_DEVICE_ID_MEILHAUS_ME4680I  0x4681  // Isolated version
  76 #define PCI_DEVICE_ID_MEILHAUS_ME4680S  0x4682  // Standard version with Sample and Hold
  77 #define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683  // Isolated version with Sample and Hold
  78
  79 /*=============================================================================
  80   Device names, for entries in /proc/..
  81   ===========================================================================*/
  82
  83 #define ME4000_NAME             "me4000"
  84 #define ME4000_AO_NAME          "me4000_ao"
  85 #define ME4000_AI_NAME          "me4000_ai"
  86 #define ME4000_DIO_NAME         "me4000_dio"
  87 #define ME4000_CNT_NAME         "me4000_cnt"
  88 #define ME4000_EXT_INT_NAME     "me4000_ext_int"
  89
  90 /*=============================================================================
  91   ME-4000 base register offsets
  92   ===========================================================================*/
  93
  94 #define ME4000_AO_00_CTRL_REG                   0x00    // R/W
  95 #define ME4000_AO_00_STATUS_REG                 0x04    // R/_
  96 #define ME4000_AO_00_FIFO_REG                   0x08    // _/W
  97 #define ME4000_AO_00_SINGLE_REG                 0x0C    // R/W
  98 #define ME4000_AO_00_TIMER_REG                  0x10    // _/W
  99
 100 #define ME4000_AO_01_CTRL_REG                   0x18    // R/W
 101 #define ME4000_AO_01_STATUS_REG                 0x1C    // R/_
 102 #define ME4000_AO_01_FIFO_REG                   0x20    // _/W
 103 #define ME4000_AO_01_SINGLE_REG                 0x24    // R/W
 104 #define ME4000_AO_01_TIMER_REG                  0x28    // _/W
 105
 106 #define ME4000_AO_02_CTRL_REG                   0x30    // R/W
 107 #define ME4000_AO_02_STATUS_REG                 0x34    // R/_
 108 #define ME4000_AO_02_FIFO_REG                   0x38    // _/W
 109 #define ME4000_AO_02_SINGLE_REG                 0x3C    // R/W
 110 #define ME4000_AO_02_TIMER_REG                  0x40    // _/W
 111
 112 #define ME4000_AO_03_CTRL_REG                   0x48    // R/W
 113 #define ME4000_AO_03_STATUS_REG                 0x4C    // R/_
 114 #define ME4000_AO_03_FIFO_REG                   0x50    // _/W
 115 #define ME4000_AO_03_SINGLE_REG                 0x54    // R/W
 116 #define ME4000_AO_03_TIMER_REG                  0x58    // _/W
 117
 118 #define ME4000_AI_CTRL_REG                      0x74    // _/W
 119 #define ME4000_AI_STATUS_REG                    0x74    // R/_
 120 #define ME4000_AI_CHANNEL_LIST_REG              0x78    // _/W
 121 #define ME4000_AI_DATA_REG                      0x7C    // R/_
 122 #define ME4000_AI_CHAN_TIMER_REG                0x80    // _/W
 123 #define ME4000_AI_CHAN_PRE_TIMER_REG            0x84    // _/W
 124 #define ME4000_AI_SCAN_TIMER_LOW_REG            0x88    // _/W
 125 #define ME4000_AI_SCAN_TIMER_HIGH_REG           0x8C    // _/W
 126 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG        0x90    // _/W
 127 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG       0x94    // _/W
 128 #define ME4000_AI_START_REG                     0x98    // R/_
 129
 130 #define ME4000_IRQ_STATUS_REG                   0x9C    // R/_
 131
 132 #define ME4000_DIO_PORT_0_REG                   0xA0    // R/W
 133 #define ME4000_DIO_PORT_1_REG                   0xA4    // R/W
 134 #define ME4000_DIO_PORT_2_REG                   0xA8    // R/W
 135 #define ME4000_DIO_PORT_3_REG                   0xAC    // R/W
 136 #define ME4000_DIO_DIR_REG                      0xB0    // R/W
 137
 138 #define ME4000_AO_LOADSETREG_XX                 0xB4    // R/W
 139
 140 #define ME4000_DIO_CTRL_REG                     0xB8    // R/W
 141
 142 #define ME4000_AO_DEMUX_ADJUST_REG              0xBC    // -/W
 143
 144 #define ME4000_AI_SAMPLE_COUNTER_REG            0xC0    // _/W
 145
 146 /*=============================================================================
 147   Value to adjust Demux
 148   ===========================================================================*/
 149
 150 #define ME4000_AO_DEMUX_ADJUST_VALUE            0x4C
 151
 152 /*=============================================================================
 153   Counter base register offsets
 154   ===========================================================================*/
 155
 156 #define ME4000_CNT_COUNTER_0_REG                0x00
 157 #define ME4000_CNT_COUNTER_1_REG                0x01
 158 #define ME4000_CNT_COUNTER_2_REG                0x02
 159 #define ME4000_CNT_CTRL_REG                     0x03
 160
 161 /*=============================================================================
 162   PLX base register offsets
 163   ===========================================================================*/
 164
 165 #define PLX_INTCSR      0x4C    // Interrupt control and status register
 166 #define PLX_ICR         0x50    // Initialization control register
 167
 168 /*=============================================================================
 169   Bits for the PLX_ICSR register
 170   ===========================================================================*/
 171
 172 #define PLX_INTCSR_LOCAL_INT1_EN             0x01       // If set, local interrupt 1 is enabled (r/w)
 173 #define PLX_INTCSR_LOCAL_INT1_POL            0x02       // If set, local interrupt 1 polarity is active high (r/w)
 174 #define PLX_INTCSR_LOCAL_INT1_STATE          0x04       // If set, local interrupt 1 is active (r/_)
 175 #define PLX_INTCSR_LOCAL_INT2_EN             0x08       // If set, local interrupt 2 is enabled (r/w)
 176 #define PLX_INTCSR_LOCAL_INT2_POL            0x10       // If set, local interrupt 2 polarity is active high (r/w)
 177 #define PLX_INTCSR_LOCAL_INT2_STATE          0x20       // If set, local interrupt 2 is active  (r/_)
 178 #define PLX_INTCSR_PCI_INT_EN                0x40       // If set, PCI interrupt is enabled (r/w)
 179 #define PLX_INTCSR_SOFT_INT                  0x80       // If set, a software interrupt is generated (r/w)
 180
 181 /*=============================================================================
 182   Bits for the PLX_ICR register
 183   ===========================================================================*/
 184
 185 #define PLX_ICR_BIT_EEPROM_CLOCK_SET            0x01000000
 186 #define PLX_ICR_BIT_EEPROM_CHIP_SELECT          0x02000000
 187 #define PLX_ICR_BIT_EEPROM_WRITE                0x04000000
 188 #define PLX_ICR_BIT_EEPROM_READ                 0x08000000
 189 #define PLX_ICR_BIT_EEPROM_VALID                0x10000000
 190
 191 #define PLX_ICR_MASK_EEPROM                     0x1F000000
 192
 193 #define EEPROM_DELAY                            1
 194
 195 /*=============================================================================
 196   Bits for the ME4000_AO_CTRL_REG register
 197   ===========================================================================*/
 198
 199 #define ME4000_AO_CTRL_BIT_MODE_0               0x001
 200 #define ME4000_AO_CTRL_BIT_MODE_1               0x002
 201 #define ME4000_AO_CTRL_MASK_MODE                0x003
 202 #define ME4000_AO_CTRL_BIT_STOP                 0x004
 203 #define ME4000_AO_CTRL_BIT_ENABLE_FIFO          0x008
 204 #define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG       0x010
 205 #define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE         0x020
 206 #define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP       0x080
 207 #define ME4000_AO_CTRL_BIT_ENABLE_DO            0x100
 208 #define ME4000_AO_CTRL_BIT_ENABLE_IRQ           0x200
 209 #define ME4000_AO_CTRL_BIT_RESET_IRQ            0x400
 210 #define ME4000_AO_CTRL_BIT_EX_TRIG_BOTH         0x800
 211
 212 /*=============================================================================
 213   Bits for the ME4000_AO_STATUS_REG register
 214   ===========================================================================*/
 215
 216 #define ME4000_AO_STATUS_BIT_FSM                0x01
 217 #define ME4000_AO_STATUS_BIT_FF                 0x02
 218 #define ME4000_AO_STATUS_BIT_HF                 0x04
 219 #define ME4000_AO_STATUS_BIT_EF                 0x08
 220
 221 /*=============================================================================
 222   Bits for the ME4000_AI_CTRL_REG register
 223   ===========================================================================*/
 224
 225 #define ME4000_AI_CTRL_BIT_MODE_0               0x00000001
 226 #define ME4000_AI_CTRL_BIT_MODE_1               0x00000002
 227 #define ME4000_AI_CTRL_BIT_MODE_2               0x00000004
 228 #define ME4000_AI_CTRL_BIT_SAMPLE_HOLD          0x00000008
 229 #define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP       0x00000010
 230 #define ME4000_AI_CTRL_BIT_STOP                 0x00000020
 231 #define ME4000_AI_CTRL_BIT_CHANNEL_FIFO         0x00000040
 232 #define ME4000_AI_CTRL_BIT_DATA_FIFO            0x00000080
 233 #define ME4000_AI_CTRL_BIT_FULLSCALE            0x00000100
 234 #define ME4000_AI_CTRL_BIT_OFFSET               0x00000200
 235 #define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG       0x00000400
 236 #define ME4000_AI_CTRL_BIT_EX_TRIG              0x00000800
 237 #define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING      0x00001000
 238 #define ME4000_AI_CTRL_BIT_EX_IRQ               0x00002000
 239 #define ME4000_AI_CTRL_BIT_EX_IRQ_RESET         0x00004000
 240 #define ME4000_AI_CTRL_BIT_LE_IRQ               0x00008000
 241 #define ME4000_AI_CTRL_BIT_LE_IRQ_RESET         0x00010000
 242 #define ME4000_AI_CTRL_BIT_HF_IRQ               0x00020000
 243 #define ME4000_AI_CTRL_BIT_HF_IRQ_RESET         0x00040000
 244 #define ME4000_AI_CTRL_BIT_SC_IRQ               0x00080000
 245 #define ME4000_AI_CTRL_BIT_SC_IRQ_RESET         0x00100000
 246 #define ME4000_AI_CTRL_BIT_SC_RELOAD            0x00200000
 247 #define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH         0x80000000
 248
 249 /*=============================================================================
 250   Bits for the ME4000_AI_STATUS_REG register
 251   ===========================================================================*/
 252
 253 #define ME4000_AI_STATUS_BIT_EF_CHANNEL         0x00400000
 254 #define ME4000_AI_STATUS_BIT_HF_CHANNEL         0x00800000
 255 #define ME4000_AI_STATUS_BIT_FF_CHANNEL         0x01000000
 256 #define ME4000_AI_STATUS_BIT_EF_DATA            0x02000000
 257 #define ME4000_AI_STATUS_BIT_HF_DATA            0x04000000
 258 #define ME4000_AI_STATUS_BIT_FF_DATA            0x08000000
 259 #define ME4000_AI_STATUS_BIT_LE                 0x10000000
 260 #define ME4000_AI_STATUS_BIT_FSM                0x20000000
 261
 262 /*=============================================================================
 263   Bits for the ME4000_IRQ_STATUS_REG register
 264   ===========================================================================*/
 265
 266 #define ME4000_IRQ_STATUS_BIT_EX                0x01
 267 #define ME4000_IRQ_STATUS_BIT_LE                0x02
 268 #define ME4000_IRQ_STATUS_BIT_AI_HF             0x04
 269 #define ME4000_IRQ_STATUS_BIT_AO_0_HF           0x08
 270 #define ME4000_IRQ_STATUS_BIT_AO_1_HF           0x10
 271 #define ME4000_IRQ_STATUS_BIT_AO_2_HF           0x20
 272 #define ME4000_IRQ_STATUS_BIT_AO_3_HF           0x40
 273 #define ME4000_IRQ_STATUS_BIT_SC                0x80
 274
 275 /*=============================================================================
 276   Bits for the ME4000_DIO_CTRL_REG register
 277   ===========================================================================*/
 278
 279 #define ME4000_DIO_CTRL_BIT_MODE_0              0X0001
 280 #define ME4000_DIO_CTRL_BIT_MODE_1              0X0002
 281 #define ME4000_DIO_CTRL_BIT_MODE_2              0X0004
 282 #define ME4000_DIO_CTRL_BIT_MODE_3              0X0008
 283 #define ME4000_DIO_CTRL_BIT_MODE_4              0X0010
 284 #define ME4000_DIO_CTRL_BIT_MODE_5              0X0020
 285 #define ME4000_DIO_CTRL_BIT_MODE_6              0X0040
 286 #define ME4000_DIO_CTRL_BIT_MODE_7              0X0080
 287
 288 #define ME4000_DIO_CTRL_BIT_FUNCTION_0          0X0100
 289 #define ME4000_DIO_CTRL_BIT_FUNCTION_1          0X0200
 290
 291 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0         0X0400
 292 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1         0X0800
 293 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2         0X1000
 294 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3         0X2000
 295
 296 /*=============================================================================
 297   Bits for the ME4000_CNT_CTRL_REG register
 298   ===========================================================================*/
 299
 300 #define ME4000_CNT_CTRL_BIT_COUNTER_0  0x00
 301 #define ME4000_CNT_CTRL_BIT_COUNTER_1  0x40
 302 #define ME4000_CNT_CTRL_BIT_COUNTER_2  0x80
 303
 304 #define ME4000_CNT_CTRL_BIT_MODE_0     0x00     // Change state if zero crossing
 305 #define ME4000_CNT_CTRL_BIT_MODE_1     0x02     // Retriggerable One-Shot
 306 #define ME4000_CNT_CTRL_BIT_MODE_2     0x04     // Asymmetrical divider
 307 #define ME4000_CNT_CTRL_BIT_MODE_3     0x06     // Symmetrical divider
 308 #define ME4000_CNT_CTRL_BIT_MODE_4     0x08     // Counter start by software trigger
 309 #define ME4000_CNT_CTRL_BIT_MODE_5     0x0A     // Counter start by hardware trigger
 310
 311 /*=============================================================================
 312   Extract information from minor device number
 313   ===========================================================================*/
 314
 315 #define AO_BOARD(dev) ((MINOR(dev) >> 6) & 0x3)
 316 #define AO_PORT(dev)  ((MINOR(dev) >> 2) & 0xF)
 317 #define AO_MODE(dev)  (MINOR(dev) & 0x3)
 318
 319 #define AI_BOARD(dev) ((MINOR(dev) >> 3) & 0x1F)
 320 #define AI_MODE(dev)  (MINOR(dev) & 0x7)
 321
 322 #define DIO_BOARD(dev) (MINOR(dev))
 323
 324 #define CNT_BOARD(dev) (MINOR(dev))
 325
 326 #define EXT_INT_BOARD(dev) (MINOR(dev))
 327
 328 /*=============================================================================
 329   Circular buffer used for analog input/output reads/writes.
 330   ===========================================================================*/
 331
 332 struct me4000_circ_buf {
 333         s16 *buf;
 334         int volatile head;
 335         int volatile tail;
 336 };
 337
 338 /*=============================================================================
 339   Information about the hardware capabilities
 340   ===========================================================================*/
 341
 342 struct me4000_ao_info {
 343         int count;
 344         int fifo_count;
 345 };
 346
 347 struct me4000_ai_info {
 348         int count;
 349         int sh_count;
 350         int diff_count;
 351         int ex_trig_analog;
 352 };
 353
 354 struct me4000_dio_info {
 355         int count;
 356 };
 357
 358 struct me4000_cnt_info {
 359         int count;
 360 };
 361
 362 struct me4000_board {
 363         u16 vendor_id;
 364         u16 device_id;
 365         struct me4000_ao_info ao;
 366         struct me4000_ai_info ai;
 367         struct me4000_dio_info dio;
 368         struct me4000_cnt_info cnt;
 369 };
 370
 371 static struct me4000_board me4000_boards[] = {
 372         {PCI_VENDOR_ID_MEILHAUS, 0x4610, {0, 0}, {16, 0, 0, 0}, {4}, {3}},
 373
 374         {PCI_VENDOR_ID_MEILHAUS, 0x4650, {0, 0}, {16, 0, 0, 0}, {4}, {0}},
 375
 376         {PCI_VENDOR_ID_MEILHAUS, 0x4660, {2, 0}, {16, 0, 0, 0}, {4}, {3}},
 377         {PCI_VENDOR_ID_MEILHAUS, 0x4661, {2, 0}, {16, 0, 0, 0}, {4}, {3}},
 378         {PCI_VENDOR_ID_MEILHAUS, 0x4662, {2, 0}, {16, 8, 0, 0}, {4}, {3}},
 379         {PCI_VENDOR_ID_MEILHAUS, 0x4663, {2, 0}, {16, 8, 0, 0}, {4}, {3}},
 380
 381         {PCI_VENDOR_ID_MEILHAUS, 0x4670, {4, 0}, {32, 0, 16, 1}, {4}, {3}},
 382         {PCI_VENDOR_ID_MEILHAUS, 0x4671, {4, 0}, {32, 0, 16, 1}, {4}, {3}},
 383         {PCI_VENDOR_ID_MEILHAUS, 0x4672, {4, 0}, {32, 8, 16, 1}, {4}, {3}},
 384         {PCI_VENDOR_ID_MEILHAUS, 0x4673, {4, 0}, {32, 8, 16, 1}, {4}, {3}},
 385
 386         {PCI_VENDOR_ID_MEILHAUS, 0x4680, {4, 4}, {32, 0, 16, 1}, {4}, {3}},
 387         {PCI_VENDOR_ID_MEILHAUS, 0x4681, {4, 4}, {32, 0, 16, 1}, {4}, {3}},
 388         {PCI_VENDOR_ID_MEILHAUS, 0x4682, {4, 4}, {32, 8, 16, 1}, {4}, {3}},
 389         {PCI_VENDOR_ID_MEILHAUS, 0x4683, {4, 4}, {32, 8, 16, 1}, {4}, {3}},
 390
 391         {0},
 392 };
 393
 394 /*=============================================================================
 395   PCI device table.
 396   This is used by modprobe to translate PCI IDs to drivers.
 397   ===========================================================================*/
 398
 399 static struct pci_device_id me4000_pci_table[] __devinitdata = {
 400         {PCI_VENDOR_ID_MEILHAUS, 0x4610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 401
 402         {PCI_VENDOR_ID_MEILHAUS, 0x4650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 403
 404         {PCI_VENDOR_ID_MEILHAUS, 0x4660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 405         {PCI_VENDOR_ID_MEILHAUS, 0x4661, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 406         {PCI_VENDOR_ID_MEILHAUS, 0x4662, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 407         {PCI_VENDOR_ID_MEILHAUS, 0x4663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 408
 409         {PCI_VENDOR_ID_MEILHAUS, 0x4670, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 410         {PCI_VENDOR_ID_MEILHAUS, 0x4671, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 411         {PCI_VENDOR_ID_MEILHAUS, 0x4672, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 412         {PCI_VENDOR_ID_MEILHAUS, 0x4673, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 413
 414         {PCI_VENDOR_ID_MEILHAUS, 0x4680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 415         {PCI_VENDOR_ID_MEILHAUS, 0x4681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 416         {PCI_VENDOR_ID_MEILHAUS, 0x4682, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 417         {PCI_VENDOR_ID_MEILHAUS, 0x4683, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 418
 419         {0}
 420 };
 421
 422 MODULE_DEVICE_TABLE(pci, me4000_pci_table);
 423
 424 /*=============================================================================
 425   Global board and subdevice information structures
 426   ===========================================================================*/
 427
 428 struct me4000_info {
 429         struct list_head list;  // List of all detected boards
 430         int board_count;        // Index of the board after detection
 431
 432         unsigned long plx_regbase;      // PLX configuration space base address
 433         resource_size_t me4000_regbase; // Base address of the ME4000
 434         resource_size_t timer_regbase;  // Base address of the timer circuit
 435         resource_size_t program_regbase;        // Base address to set the program pin for the xilinx
 436
 437         unsigned long plx_regbase_size; // PLX register set space
 438         resource_size_t me4000_regbase_size;    // ME4000 register set space
 439         resource_size_t timer_regbase_size;     // Timer circuit register set space
 440         resource_size_t program_regbase_size;   // Size of program base address of the ME4000
 441
 442         unsigned int serial_no; // Serial number of the board
 443         unsigned char hw_revision;      // Hardware revision of the board
 444         unsigned short vendor_id;       // Meilhaus vendor id (0x1402)
 445         unsigned short device_id;       // Device ID
 446
 447         int pci_bus_no;         // PCI bus number
 448         int pci_dev_no;         // PCI device number
 449         int pci_func_no;        // PCI function number
 450         struct pci_dev *pci_dev_p;      // General PCI information
 451
 452         struct me4000_board *board_p;   // Holds the board capabilities
 453
 454         unsigned int irq;       // IRQ assigned from the PCI BIOS
 455         unsigned int irq_count; // Count of external interrupts
 456
 457         spinlock_t preload_lock;        // Guards the analog output preload register
 458         spinlock_t ai_ctrl_lock;        // Guards the analog input control register
 459
 460         struct list_head ao_context_list;       // List with analog output specific context
 461         struct me4000_ai_context *ai_context;   // Analog input  specific context
 462         struct me4000_dio_context *dio_context; // Digital I/O specific context
 463         struct me4000_cnt_context *cnt_context; // Counter specific context
 464         struct me4000_ext_int_context *ext_int_context; // External interrupt specific context
 465 };
 466
 467 struct me4000_ao_context {
 468         struct list_head list;  // linked list of me4000_ao_context_t
 469         int index;              // Index in the list
 470         int mode;               // Indicates mode (0 = single, 1 = wraparound, 2 = continous)
 471         int dac_in_use;         // Indicates if already opend
 472         spinlock_t use_lock;    // Guards in_use
 473         spinlock_t int_lock;    // Used when locking out interrupts
 474         struct me4000_circ_buf circ_buf;        // Circular buffer
 475         wait_queue_head_t wait_queue;   // Wait queue to sleep while blocking write
 476         struct me4000_info *board_info;
 477         unsigned int irq;       // The irq associated with this ADC
 478         int volatile pipe_flag; // Indicates broken pipe set from me4000_ao_isr()
 479         unsigned long ctrl_reg;
 480         unsigned long status_reg;
 481         unsigned long fifo_reg;
 482         unsigned long single_reg;
 483         unsigned long timer_reg;
 484         unsigned long irq_status_reg;
 485         unsigned long preload_reg;
 486         struct fasync_struct *fasync_p; // Queue for asynchronous notification
 487 };
 488
 489 struct me4000_ai_context {
 490         struct list_head list;  // linked list of me4000_ai_info_t
 491         int mode;               // Indicates mode
 492         int in_use;             // Indicates if already opend
 493         spinlock_t use_lock;    // Guards in_use
 494         spinlock_t int_lock;    // Used when locking out interrupts
 495         int number;             // Number of the DAC
 496         unsigned int irq;       // The irq associated with this ADC
 497         struct me4000_circ_buf circ_buf;        // Circular buffer
 498         wait_queue_head_t wait_queue;   // Wait queue to sleep while blocking read
 499         struct me4000_info *board_info;
 500
 501         struct fasync_struct *fasync_p; // Queue for asynchronous notification
 502
 503         unsigned long ctrl_reg;
 504         unsigned long status_reg;
 505         unsigned long channel_list_reg;
 506         unsigned long data_reg;
 507         unsigned long chan_timer_reg;
 508         unsigned long chan_pre_timer_reg;
 509         unsigned long scan_timer_low_reg;
 510         unsigned long scan_timer_high_reg;
 511         unsigned long scan_pre_timer_low_reg;
 512         unsigned long scan_pre_timer_high_reg;
 513         unsigned long start_reg;
 514         unsigned long irq_status_reg;
 515         unsigned long sample_counter_reg;
 516
 517         unsigned long chan_timer;
 518         unsigned long chan_pre_timer;
 519         unsigned long scan_timer_low;
 520         unsigned long scan_timer_high;
 521         unsigned long channel_list_count;
 522         unsigned long sample_counter;
 523         int sample_counter_reload;
 524 };
 525
 526 struct me4000_dio_context {
 527         struct list_head list;  // linked list of me4000_dio_context_t
 528         int in_use;             // Indicates if already opend
 529         spinlock_t use_lock;    // Guards in_use
 530         int number;
 531         int dio_count;
 532         struct me4000_info *board_info;
 533         unsigned long dir_reg;
 534         unsigned long ctrl_reg;
 535         unsigned long port_0_reg;
 536         unsigned long port_1_reg;
 537         unsigned long port_2_reg;
 538         unsigned long port_3_reg;
 539 };
 540
 541 struct me4000_cnt_context {
 542         struct list_head list;  // linked list of me4000_dio_context_t
 543         int in_use;             // Indicates if already opend
 544         spinlock_t use_lock;    // Guards in_use
 545         int number;
 546         int cnt_count;
 547         struct me4000_info *board_info;
 548         unsigned long ctrl_reg;
 549         unsigned long counter_0_reg;
 550         unsigned long counter_1_reg;
 551         unsigned long counter_2_reg;
 552 };
 553
 554 struct me4000_ext_int_context {
 555         struct list_head list;  // linked list of me4000_dio_context_t
 556         int in_use;             // Indicates if already opend
 557         spinlock_t use_lock;    // Guards in_use
 558         int number;
 559         struct me4000_info *board_info;
 560         unsigned int irq;
 561         unsigned long int_count;
 562         struct fasync_struct *fasync_ptr;
 563         unsigned long ctrl_reg;
 564         unsigned long irq_status_reg;
 565 };
 566
 567 #endif
 568
 569 /*=============================================================================
 570   Application include section starts here
 571   ===========================================================================*/
 572
 573 /*-----------------------------------------------------------------------------
 574   Defines for analog input
 575   ----------------------------------------------------------------------------*/
 576
 577 /* General stuff */
 578 #define ME4000_AI_FIFO_COUNT            2048
 579
 580 #define ME4000_AI_MIN_TICKS             66
 581 #define ME4000_AI_MAX_SCAN_TICKS        0xFFFFFFFFFFLL
 582
 583 #define ME4000_AI_BUFFER_SIZE           (32 * 1024)     // Size in bytes
 584
 585 #define ME4000_AI_BUFFER_COUNT          ((ME4000_AI_BUFFER_SIZE) / 2)   // Size in values
 586
 587 /* Channel list defines and masks */
 588 #define ME4000_AI_CHANNEL_LIST_COUNT            1024
 589
 590 #define ME4000_AI_LIST_INPUT_SINGLE_ENDED       0x000
 591 #define ME4000_AI_LIST_INPUT_DIFFERENTIAL       0x020
 592
 593 #define ME4000_AI_LIST_RANGE_BIPOLAR_10         0x000
 594 #define ME4000_AI_LIST_RANGE_BIPOLAR_2_5        0x040
 595 #define ME4000_AI_LIST_RANGE_UNIPOLAR_10        0x080
 596 #define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5       0x0C0
 597
 598 #define ME4000_AI_LIST_LAST_ENTRY               0x100
 599
 600 /* External trigger defines */
 601 #define ME4000_AI_TRIGGER_SOFTWARE              0x0     // Use only with API
 602 #define ME4000_AI_TRIGGER_EXT_DIGITAL           0x1
 603 #define ME4000_AI_TRIGGER_EXT_ANALOG            0x2
 604
 605 #define ME4000_AI_TRIGGER_EXT_EDGE_RISING       0x0
 606 #define ME4000_AI_TRIGGER_EXT_EDGE_FALLING      0x1
 607 #define ME4000_AI_TRIGGER_EXT_EDGE_BOTH         0x2
 608
 609 /* Sample and Hold */
 610 #define ME4000_AI_SIMULTANEOUS_DISABLE          0x0
 611 #define ME4000_AI_SIMULTANEOUS_ENABLE           0x1
 612
 613 /* Defines for the Sample Counter */
 614 #define ME4000_AI_SC_RELOAD                     0x0
 615 #define ME4000_AI_SC_ONCE                       0x1
 616
 617 /* Modes for analog input */
 618 #define ME4000_AI_ACQ_MODE_SINGLE               0x00    // Catch one single value
 619 #define ME4000_AI_ACQ_MODE_SOFTWARE             0x01    // Continous sampling with software start
 620 #define ME4000_AI_ACQ_MODE_EXT                  0x02    // Continous sampling with external trigger start
 621 #define ME4000_AI_ACQ_MODE_EXT_SINGLE_VALUE     0x03    // Sample one value by external trigger
 622 #define ME4000_AI_ACQ_MODE_EXT_SINGLE_CHANLIST  0x04    // Sample one channel list by external trigger
 623
 624 /* Staus of AI FSM */
 625 #define ME4000_AI_STATUS_IDLE                   0x0
 626 #define ME4000_AI_STATUS_BUSY                   0x1
 627
 628 /* Voltages for calibration */
 629 #define ME4000_AI_GAIN_1_UNI_OFFSET             10.0E-3
 630 #define ME4000_AI_GAIN_1_UNI_FULLSCALE          9950.0E-3
 631 #define ME4000_AI_GAIN_1_BI_OFFSET              0.0
 632 #define ME4000_AI_GAIN_1_BI_FULLSCALE           9950.0E-3
 633 #define ME4000_AI_GAIN_4_UNI_OFFSET             10.0E-3
 634 #define ME4000_AI_GAIN_4_UNI_FULLSCALE          2450.0E-3
 635 #define ME4000_AI_GAIN_4_BI_OFFSET              0.0
 636 #define ME4000_AI_GAIN_4_BI_FULLSCALE           2450.0E-3
 637
 638 /* Ideal digits for calibration */
 639 #define ME4000_AI_GAIN_1_UNI_OFFSET_DIGITS      (-32702)
 640 #define ME4000_AI_GAIN_1_UNI_FULLSCALE_DIGITS   32440
 641 #define ME4000_AI_GAIN_1_BI_OFFSET_DIGITS       0
 642 #define ME4000_AI_GAIN_1_BI_FULLSCALE_DIGITS    32604
 643 #define ME4000_AI_GAIN_4_UNI_OFFSET_DIGITS      (-32505)
 644 #define ME4000_AI_GAIN_4_UNI_FULLSCALE_DIGITS   31457
 645 #define ME4000_AI_GAIN_4_BI_OFFSET_DIGITS       0
 646 #define ME4000_AI_GAIN_4_BI_FULLSCALE_DIGITS    32113
 647
 648 /*-----------------------------------------------------------------------------
 649   Defines for analog output
 650   ----------------------------------------------------------------------------*/
 651
 652 /* General stuff */
 653 #define ME4000_AO_FIFO_COUNT                    (4 * 1024)
 654
 655 #define ME4000_AO_MIN_TICKS                     66
 656
 657 #define ME4000_AO_BUFFER_SIZE                   (32 * 1024)     // Size in bytes
 658
 659 #define ME4000_AO_BUFFER_COUNT                  ((ME4000_AO_BUFFER_SIZE) / 2)   // Size in values
 660
 661 /* Conversion modes for analog output */
 662 #define ME4000_AO_CONV_MODE_SINGLE              0x0
 663 #define ME4000_AO_CONV_MODE_WRAPAROUND          0x1
 664 #define ME4000_AO_CONV_MODE_CONTINUOUS          0x2
 665
 666 /* Trigger setup */
 667 #define ME4000_AO_TRIGGER_EXT_EDGE_RISING       0x0
 668 #define ME4000_AO_TRIGGER_EXT_EDGE_FALLING      0x1
 669 #define ME4000_AO_TRIGGER_EXT_EDGE_BOTH         0x2
 670
 671 /* Status of AO FSM */
 672 #define ME4000_AO_STATUS_IDLE                   0x0
 673 #define ME4000_AO_STATUS_BUSY                   0x1
 674
 675 /*-----------------------------------------------------------------------------
 676   Defines for eeprom
 677   ----------------------------------------------------------------------------*/
 678
 679 #define ME4000_EEPROM_CMD_READ                  0x180
 680 #define ME4000_EEPROM_CMD_WRITE_ENABLE          0x130
 681 #define ME4000_EEPROM_CMD_WRITE_DISABLE         0x100
 682 #define ME4000_EEPROM_CMD_WRITE                 0x1400000
 683
 684 #define ME4000_EEPROM_CMD_LENGTH_READ           9
 685 #define ME4000_EEPROM_CMD_LENGTH_WRITE_ENABLE   9
 686 #define ME4000_EEPROM_CMD_LENGTH_WRITE_DISABLE  9
 687 #define ME4000_EEPROM_CMD_LENGTH_WRITE          25
 688
 689 #define ME4000_EEPROM_ADR_DATE_HIGH             0x32
 690 #define ME4000_EEPROM_ADR_DATE_LOW              0x33
 691
 692 #define ME4000_EEPROM_ADR_GAIN_1_UNI_OFFSET     0x34
 693 #define ME4000_EEPROM_ADR_GAIN_1_UNI_FULLSCALE  0x35
 694 #define ME4000_EEPROM_ADR_GAIN_1_BI_OFFSET      0x36
 695 #define ME4000_EEPROM_ADR_GAIN_1_BI_FULLSCALE   0x37
 696 #define ME4000_EEPROM_ADR_GAIN_1_DIFF_OFFSET    0x38
 697 #define ME4000_EEPROM_ADR_GAIN_1_DIFF_FULLSCALE 0x39
 698
 699 #define ME4000_EEPROM_ADR_GAIN_4_UNI_OFFSET     0x3A
 700 #define ME4000_EEPROM_ADR_GAIN_4_UNI_FULLSCALE  0x3B
 701 #define ME4000_EEPROM_ADR_GAIN_4_BI_OFFSET      0x3C
 702 #define ME4000_EEPROM_ADR_GAIN_4_BI_FULLSCALE   0x3D
 703 #define ME4000_EEPROM_ADR_GAIN_4_DIFF_OFFSET    0x3E
 704 #define ME4000_EEPROM_ADR_GAIN_4_DIFF_FULLSCALE 0x3F
 705
 706 #define ME4000_EEPROM_ADR_LENGTH                6
 707 #define ME4000_EEPROM_DATA_LENGTH               16
 708
 709 /*-----------------------------------------------------------------------------
 710   Defines for digital I/O
 711   ----------------------------------------------------------------------------*/
 712
 713 #define ME4000_DIO_PORT_A               0x0
 714 #define ME4000_DIO_PORT_B               0x1
 715 #define ME4000_DIO_PORT_C               0x2
 716 #define ME4000_DIO_PORT_D               0x3
 717
 718 #define ME4000_DIO_PORT_INPUT           0x0
 719 #define ME4000_DIO_PORT_OUTPUT          0x1
 720 #define ME4000_DIO_FIFO_LOW             0x2
 721 #define ME4000_DIO_FIFO_HIGH            0x3
 722
 723 #define ME4000_DIO_FUNCTION_PATTERN     0x0
 724 #define ME4000_DIO_FUNCTION_DEMUX       0x1
 725 #define ME4000_DIO_FUNCTION_MUX         0x2
 726
 727 /*-----------------------------------------------------------------------------
 728   Defines for counters
 729   ----------------------------------------------------------------------------*/
 730
 731 #define ME4000_CNT_COUNTER_0  0
 732 #define ME4000_CNT_COUNTER_1  1
 733 #define ME4000_CNT_COUNTER_2  2
 734
 735 #define ME4000_CNT_MODE_0     0 // Change state if zero crossing
 736 #define ME4000_CNT_MODE_1     1 // Retriggerable One-Shot
 737 #define ME4000_CNT_MODE_2     2 // Asymmetrical divider
 738 #define ME4000_CNT_MODE_3     3 // Symmetrical divider
 739 #define ME4000_CNT_MODE_4     4 // Counter start by software trigger
 740 #define ME4000_CNT_MODE_5     5 // Counter start by hardware trigger
 741
 742 /*-----------------------------------------------------------------------------
 743   General type definitions
 744   ----------------------------------------------------------------------------*/
 745
 746 struct me4000_user_info {
 747         int board_count;        // Index of the board after detection
 748         unsigned long plx_regbase;      // PLX configuration space base address
 749         resource_size_t me4000_regbase; // Base address of the ME4000
 750         unsigned long plx_regbase_size; // PLX register set space
 751         resource_size_t me4000_regbase_size;    // ME4000 register set space
 752         unsigned long serial_no;        // Serial number of the board
 753         unsigned char hw_revision;      // Hardware revision of the board
 754         unsigned short vendor_id;       // Meilhaus vendor id (0x1402)
 755         unsigned short device_id;       // Device ID
 756         int pci_bus_no;         // PCI bus number
 757         int pci_dev_no;         // PCI device number
 758         int pci_func_no;        // PCI function number
 759         char irq;               // IRQ assigned from the PCI BIOS
 760         int irq_count;          // Count of external interrupts
 761
 762         int driver_version;     // Version of the driver release
 763
 764         int ao_count;           // Count of analog output channels
 765         int ao_fifo_count;      // Count fo analog output fifos
 766
 767         int ai_count;           // Count of analog input channels
 768         int ai_sh_count;        // Count of sample and hold devices
 769         int ai_ex_trig_analog;  // Flag to indicate if analogous external trigger is available
 770
 771         int dio_count;          // Count of digital I/O ports
 772
 773         int cnt_count;          // Count of counters
 774 };
 775
 776 /*-----------------------------------------------------------------------------
 777   Type definitions for analog output
 778   ----------------------------------------------------------------------------*/
 779
 780 struct me4000_ao_channel_list {
 781         unsigned long count;
 782         unsigned long *list;
 783 };
 784
 785 /*-----------------------------------------------------------------------------
 786   Type definitions for analog input
 787   ----------------------------------------------------------------------------*/
 788
 789 struct me4000_ai_channel_list {
 790         unsigned long count;
 791         unsigned long *list;
 792 };
 793
 794 struct me4000_ai_timer {
 795         unsigned long pre_chan;
 796         unsigned long chan;
 797         unsigned long scan_low;
 798         unsigned long scan_high;
 799 };
 800
 801 struct me4000_ai_config {
 802         struct me4000_ai_timer timer;
 803         struct me4000_ai_channel_list channel_list;
 804         int sh;
 805 };
 806
 807 struct me4000_ai_single {
 808         int channel;
 809         int range;
 810         int mode;
 811         short value;
 812         unsigned long timeout;
 813 };
 814
 815 struct me4000_ai_trigger {
 816         int mode;
 817         int edge;
 818 };
 819
 820 struct me4000_ai_sc {
 821         unsigned long value;
 822         int reload;
 823 };
 824
 825 /*-----------------------------------------------------------------------------
 826   Type definitions for eeprom
 827   ----------------------------------------------------------------------------*/
 828
 829 struct me4000_eeprom {
 830         unsigned long date;
 831         short uni_10_offset;
 832         short uni_10_fullscale;
 833         short uni_2_5_offset;
 834         short uni_2_5_fullscale;
 835         short bi_10_offset;
 836         short bi_10_fullscale;
 837         short bi_2_5_offset;
 838         short bi_2_5_fullscale;
 839         short diff_10_offset;
 840         short diff_10_fullscale;
 841         short diff_2_5_offset;
 842         short diff_2_5_fullscale;
 843 };
 844
 845 /*-----------------------------------------------------------------------------
 846   Type definitions for digital I/O
 847   ----------------------------------------------------------------------------*/
 848
 849 struct me4000_dio_config {
 850         int port;
 851         int mode;
 852         int function;
 853 };
 854
 855 struct me4000_dio_byte {
 856         int port;
 857         unsigned char byte;
 858 };
 859
 860 /*-----------------------------------------------------------------------------
 861   Type definitions for counters
 862   ----------------------------------------------------------------------------*/
 863
 864 struct me4000_cnt {
 865         int counter;
 866         unsigned short value;
 867 };
 868
 869 struct me4000_cnt_config {
 870         int counter;
 871         int mode;
 872 };
 873
 874 /*-----------------------------------------------------------------------------
 875   Type definitions for external interrupt
 876   ----------------------------------------------------------------------------*/
 877
 878 struct me4000_int {
 879         int int1_count;
 880         int int2_count;
 881 };
 882
 883 /*-----------------------------------------------------------------------------
 884   The ioctls of the board
 885   ----------------------------------------------------------------------------*/
 886
 887 #define ME4000_IOCTL_MAXNR 50
 888 #define ME4000_MAGIC 'y'
 889 #define ME4000_GET_USER_INFO          _IOR (ME4000_MAGIC, 0, \
 890                                             struct me4000_user_info)
 891
 892 #define ME4000_AO_START               _IOW (ME4000_MAGIC, 1, unsigned long)
 893 #define ME4000_AO_STOP                _IO  (ME4000_MAGIC, 2)
 894 #define ME4000_AO_IMMEDIATE_STOP      _IO  (ME4000_MAGIC, 3)
 895 #define ME4000_AO_RESET               _IO  (ME4000_MAGIC, 4)
 896 #define ME4000_AO_PRELOAD             _IO  (ME4000_MAGIC, 5)
 897 #define ME4000_AO_PRELOAD_UPDATE      _IO  (ME4000_MAGIC, 6)
 898 #define ME4000_AO_EX_TRIG_ENABLE      _IO  (ME4000_MAGIC, 7)
 899 #define ME4000_AO_EX_TRIG_DISABLE     _IO  (ME4000_MAGIC, 8)
 900 #define ME4000_AO_EX_TRIG_SETUP       _IOW (ME4000_MAGIC, 9, int)
 901 #define ME4000_AO_TIMER_SET_DIVISOR   _IOW (ME4000_MAGIC, 10, unsigned long)
 902 #define ME4000_AO_ENABLE_DO           _IO  (ME4000_MAGIC, 11)
 903 #define ME4000_AO_DISABLE_DO          _IO  (ME4000_MAGIC, 12)
 904 #define ME4000_AO_FSM_STATE           _IOR (ME4000_MAGIC, 13, int)
 905
 906 #define ME4000_AI_SINGLE              _IOR (ME4000_MAGIC, 14, \
 907                                             struct me4000_ai_single)
 908 #define ME4000_AI_START               _IOW (ME4000_MAGIC, 15, unsigned long)
 909 #define ME4000_AI_STOP                _IO  (ME4000_MAGIC, 16)
 910 #define ME4000_AI_IMMEDIATE_STOP      _IO  (ME4000_MAGIC, 17)
 911 #define ME4000_AI_EX_TRIG_ENABLE      _IO  (ME4000_MAGIC, 18)
 912 #define ME4000_AI_EX_TRIG_DISABLE     _IO  (ME4000_MAGIC, 19)
 913 #define ME4000_AI_EX_TRIG_SETUP       _IOW (ME4000_MAGIC, 20, \
 914                                             struct me4000_ai_trigger)
 915 #define ME4000_AI_CONFIG              _IOW (ME4000_MAGIC, 21, \
 916                                             struct me4000_ai_config)
 917 #define ME4000_AI_SC_SETUP            _IOW (ME4000_MAGIC, 22, \
 918                                             struct me4000_ai_sc)
 919 #define ME4000_AI_FSM_STATE           _IOR (ME4000_MAGIC, 23, int)
 920
 921 #define ME4000_DIO_CONFIG             _IOW (ME4000_MAGIC, 24, \
 922                                             struct me4000_dio_config)
 923 #define ME4000_DIO_GET_BYTE           _IOR (ME4000_MAGIC, 25, \
 924                                             struct me4000_dio_byte)
 925 #define ME4000_DIO_SET_BYTE           _IOW (ME4000_MAGIC, 26, \
 926                                             struct me4000_dio_byte)
 927 #define ME4000_DIO_RESET              _IO  (ME4000_MAGIC, 27)
 928
 929 #define ME4000_CNT_READ               _IOR (ME4000_MAGIC, 28, \
 930                                             struct me4000_cnt)
 931 #define ME4000_CNT_WRITE              _IOW (ME4000_MAGIC, 29, \
 932                                             struct me4000_cnt)
 933 #define ME4000_CNT_CONFIG             _IOW (ME4000_MAGIC, 30, \
 934                                             struct me4000_cnt_config)
 935 #define ME4000_CNT_RESET              _IO  (ME4000_MAGIC, 31)
 936
 937 #define ME4000_EXT_INT_DISABLE        _IO  (ME4000_MAGIC, 32)
 938 #define ME4000_EXT_INT_ENABLE         _IO  (ME4000_MAGIC, 33)
 939 #define ME4000_EXT_INT_COUNT          _IOR (ME4000_MAGIC, 34, int)
 940
 941 #define ME4000_AI_OFFSET_ENABLE       _IO  (ME4000_MAGIC, 35)
 942 #define ME4000_AI_OFFSET_DISABLE      _IO  (ME4000_MAGIC, 36)
 943 #define ME4000_AI_FULLSCALE_ENABLE    _IO  (ME4000_MAGIC, 37)
 944 #define ME4000_AI_FULLSCALE_DISABLE   _IO  (ME4000_MAGIC, 38)
 945
 946 #define ME4000_AI_EEPROM_READ         _IOR (ME4000_MAGIC, 39, \
 947                                             struct me4000_eeprom)
 948 #define ME4000_AI_EEPROM_WRITE        _IOW (ME4000_MAGIC, 40, \
 949                                             struct me4000_eeprom)
 950
 951 #define ME4000_AO_SIMULTANEOUS_EX_TRIG _IO  (ME4000_MAGIC, 41)
 952 #define ME4000_AO_SIMULTANEOUS_SW      _IO  (ME4000_MAGIC, 42)
 953 #define ME4000_AO_SIMULTANEOUS_DISABLE _IO  (ME4000_MAGIC, 43)
 954 #define ME4000_AO_SIMULTANEOUS_UPDATE  _IOW (ME4000_MAGIC, 44, \
 955                                              struct me4000_ao_channel_list)
 956
 957 #define ME4000_AO_SYNCHRONOUS_EX_TRIG  _IO  (ME4000_MAGIC, 45)
 958 #define ME4000_AO_SYNCHRONOUS_SW       _IO  (ME4000_MAGIC, 46)
 959 #define ME4000_AO_SYNCHRONOUS_DISABLE  _IO  (ME4000_MAGIC, 47)
 960
 961 #define ME4000_AO_EX_TRIG_TIMEOUT      _IOW (ME4000_MAGIC, 48, unsigned long)
 962 #define ME4000_AO_GET_FREE_BUFFER      _IOR (ME4000_MAGIC, 49, unsigned long)
 963
 964 #define ME4000_AI_GET_COUNT_BUFFER     _IOR (ME4000_MAGIC, 50, unsigned long)
 965
 966 #endif