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kbuild: modules_install for external modules must not remove existing modules
[linux-2.6/mini2440.git] / sound / oss / es1371.c
blob4400c85386862a8f101f9c0742d89a5d0e99fe91
1 /*****************************************************************************/
2
3 /*
4 * es1371.c -- Creative Ensoniq ES1371.
5 *
6 * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Special thanks to Ensoniq
23 *
24 * Supported devices:
25 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
26 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
27 * /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
28 * /dev/midi simple MIDI UART interface, no ioctl
29 *
30 * NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
31 * to be done in software. That is what /dev/dac is for. By now (Q2 1998)
32 * there are several MIDI to PCM (WAV) packages, one of them is timidity.
33 *
34 * Revision history
35 * 04.06.1998 0.1 Initial release
36 * Mixer stuff should be overhauled; especially optional AC97 mixer bits
37 * should be detected. This results in strange behaviour of some mixer
38 * settings, like master volume and mic.
39 * 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice
40 * 03.08.1998 0.3 Do not include modversions.h
41 * Now mixer behaviour can basically be selected between
42 * "OSS documented" and "OSS actual" behaviour
43 * 31.08.1998 0.4 Fix realplayer problems - dac.count issues
44 * 27.10.1998 0.5 Fix joystick support
45 * -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
46 * 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA
47 * 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs
48 * Don't wake up app until there are fragsize bytes to read/write
49 * 06.01.1999 0.8 remove the silly SA_INTERRUPT flag.
50 * hopefully killed the egcs section type conflict
51 * 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl.
52 * reported by Johan Maes <joma@telindus.be>
53 * 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK
54 * read/write cannot be executed
55 * 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE,
56 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
57 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
58 * Another Alpha fix (wait_src_ready in init routine)
59 * reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
60 * Note: joystick address handling might still be wrong on archs
61 * other than i386
62 * 15.06.1999 0.12 Fix bad allocation bug.
63 * Thanks to Deti Fliegl <fliegl@in.tum.de>
64 * 28.06.1999 0.13 Add pci_set_master
65 * 03.08.1999 0.14 adapt to Linus' new __setup/__initcall
66 * added kernel command line option "es1371=joystickaddr"
67 * removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
68 * 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4.
69 * Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
70 * module_init/__setup fixes
71 * 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com>
72 * Added detection for ES1371 revision ID so that we can
73 * detect the ES1373 and later parts.
74 * added AC97 #defines for readability
75 * added a /proc file system for dumping hardware state
76 * updated SRC and CODEC w/r functions to accommodate bugs
77 * in some versions of the ES137x chips.
78 * 31.08.1999 0.17 add spin_lock_init
79 * replaced current->state = x with set_current_state(x)
80 * 03.09.1999 0.18 change read semantics for MIDI to match
81 * OSS more closely; remove possible wakeup race
82 * 21.10.1999 0.19 Round sampling rates, requested by
83 * Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
84 * 27.10.1999 0.20 Added SigmaTel 3D enhancement string
85 * Codec ID printing changes
86 * 28.10.1999 0.21 More waitqueue races fixed
87 * Joe Cotellese <joec@ensoniq.com>
88 * Changed PCI detection routine so we can more easily
89 * detect ES137x chip and derivatives.
90 * 05.01.2000 0.22 Should now work with rev7 boards; patch by
91 * Eric Lemar, elemar@cs.washington.edu
92 * 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun;
93 * Tim Janik's BSE (Bedevilled Sound Engine) found this
94 * 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver
95 * 07.02.2000 0.25 Use ac97_codec
96 * 01.03.2000 0.26 SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com>
97 * Use pci_module_init
98 * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
99 * 12.12.2000 0.28 More dma buffer initializations, patch from
100 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
101 * 05.01.2001 0.29 Hopefully updates will not be required anymore when Creative bumps
102 * the CT5880 revision.
103 * suggested by Stephan Müller <smueller@chronox.de>
104 * 31.01.2001 0.30 Register/Unregister gameport
105 * Fix SETTRIGGER non OSS API conformity
106 * 14.07.2001 0.31 Add list of laptops needing amplifier control
107 * 03.01.2003 0.32 open_mode fixes from Georg Acher <acher@in.tum.de>
108 */
109
110 /*****************************************************************************/
111
112 #include <linux/interrupt.h>
113 #include <linux/module.h>
114 #include <linux/string.h>
115 #include <linux/ioport.h>
116 #include <linux/sched.h>
117 #include <linux/delay.h>
118 #include <linux/sound.h>
119 #include <linux/slab.h>
120 #include <linux/soundcard.h>
121 #include <linux/pci.h>
122 #include <linux/init.h>
123 #include <linux/poll.h>
124 #include <linux/bitops.h>
125 #include <linux/proc_fs.h>
126 #include <linux/spinlock.h>
127 #include <linux/smp_lock.h>
128 #include <linux/ac97_codec.h>
129 #include <linux/gameport.h>
130 #include <linux/wait.h>
131 #include <linux/dma-mapping.h>
132 #include <linux/mutex.h>
133
134 #include <asm/io.h>
135 #include <asm/page.h>
136 #include <asm/uaccess.h>
137
138 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
139 #define SUPPORT_JOYSTICK
140 #endif
141
142 /* --------------------------------------------------------------------- */
143
144 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
145 #define ES1371_DEBUG
146 #define DBG(x) {}
147 /*#define DBG(x) {x}*/
148
149 /* --------------------------------------------------------------------- */
150
151 #ifndef PCI_VENDOR_ID_ENSONIQ
152 #define PCI_VENDOR_ID_ENSONIQ 0x1274
153 #endif
154
155 #ifndef PCI_VENDOR_ID_ECTIVA
156 #define PCI_VENDOR_ID_ECTIVA 0x1102
157 #endif
158
159 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
160 #define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
161 #endif
162
163 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
164 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
165 #endif
166
167 #ifndef PCI_DEVICE_ID_ECTIVA_EV1938
168 #define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
169 #endif
170
171 /* ES1371 chip ID */
172 /* This is a little confusing because all ES1371 compatible chips have the
173 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
174 This is only significant if you want to enable features on the later parts.
175 Yes, I know it's stupid and why didn't we use the sub IDs?
176 */
177 #define ES1371REV_ES1373_A 0x04
178 #define ES1371REV_ES1373_B 0x06
179 #define ES1371REV_CT5880_A 0x07
180 #define CT5880REV_CT5880_C 0x02
181 #define CT5880REV_CT5880_D 0x03
182 #define ES1371REV_ES1371_B 0x09
183 #define EV1938REV_EV1938_A 0x00
184 #define ES1371REV_ES1373_8 0x08
185
186 #define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
187
188 #define ES1371_EXTENT 0x40
189 #define JOY_EXTENT 8
190
191 #define ES1371_REG_CONTROL 0x00
192 #define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */
193 #define ES1371_REG_UART_DATA 0x08
194 #define ES1371_REG_UART_STATUS 0x09
195 #define ES1371_REG_UART_CONTROL 0x09
196 #define ES1371_REG_UART_TEST 0x0a
197 #define ES1371_REG_MEMPAGE 0x0c
198 #define ES1371_REG_SRCONV 0x10
199 #define ES1371_REG_CODEC 0x14
200 #define ES1371_REG_LEGACY 0x18
201 #define ES1371_REG_SERIAL_CONTROL 0x20
202 #define ES1371_REG_DAC1_SCOUNT 0x24
203 #define ES1371_REG_DAC2_SCOUNT 0x28
204 #define ES1371_REG_ADC_SCOUNT 0x2c
205
206 #define ES1371_REG_DAC1_FRAMEADR 0xc30
207 #define ES1371_REG_DAC1_FRAMECNT 0xc34
208 #define ES1371_REG_DAC2_FRAMEADR 0xc38
209 #define ES1371_REG_DAC2_FRAMECNT 0xc3c
210 #define ES1371_REG_ADC_FRAMEADR 0xd30
211 #define ES1371_REG_ADC_FRAMECNT 0xd34
212
213 #define ES1371_FMT_U8_MONO 0
214 #define ES1371_FMT_U8_STEREO 1
215 #define ES1371_FMT_S16_MONO 2
216 #define ES1371_FMT_S16_STEREO 3
217 #define ES1371_FMT_STEREO 1
218 #define ES1371_FMT_S16 2
219 #define ES1371_FMT_MASK 3
220
221 static const unsigned sample_size[] = { 1, 2, 2, 4 };
222 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
223
224 #define CTRL_RECEN_B 0x08000000 /* 1 = don't mix analog in to digital out */
225 #define CTRL_SPDIFEN_B 0x04000000
226 #define CTRL_JOY_SHIFT 24
227 #define CTRL_JOY_MASK 3
228 #define CTRL_JOY_200 0x00000000 /* joystick base address */
229 #define CTRL_JOY_208 0x01000000
230 #define CTRL_JOY_210 0x02000000
231 #define CTRL_JOY_218 0x03000000
232 #define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */
233 #define CTRL_GPIO_IN1 0x00200000
234 #define CTRL_GPIO_IN2 0x00400000
235 #define CTRL_GPIO_IN3 0x00800000
236 #define CTRL_GPIO_OUT0 0x00010000
237 #define CTRL_GPIO_OUT1 0x00020000
238 #define CTRL_GPIO_OUT2 0x00040000
239 #define CTRL_GPIO_OUT3 0x00080000
240 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
241 #define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */
242 #define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */
243 #define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */
244 #define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */
245 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
246 #define CTRL_PDLEV0 0x00000000 /* power down level */
247 #define CTRL_PDLEV1 0x00000100
248 #define CTRL_PDLEV2 0x00000200
249 #define CTRL_PDLEV3 0x00000300
250 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
251 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
252 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
253 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
254 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
255 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */
256 #define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */
257 #define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */
258
259
260 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
261 #define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
262 #define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */
263 #define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */
264 #define STAT_TESTMODE 0x00010000 /* test ASIC */
265 #define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */
266 #define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
267 #define STAT_SH_VC 6
268 #define STAT_MPWR 0x00000020 /* power level interrupt */
269 #define STAT_MCCB 0x00000010 /* CCB int pending */
270 #define STAT_UART 0x00000008 /* UART int pending */
271 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
272 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
273 #define STAT_ADC 0x00000001 /* ADC int pending */
274
275 #define USTAT_RXINT 0x80 /* UART rx int pending */
276 #define USTAT_TXINT 0x04 /* UART tx int pending */
277 #define USTAT_TXRDY 0x02 /* UART tx ready */
278 #define USTAT_RXRDY 0x01 /* UART rx ready */
279
280 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
281 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
282 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
283 #define UCTRL_CNTRL 0x03 /* control field */
284 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
285
286 /* sample rate converter */
287 #define SRC_OKSTATE 1
288
289 #define SRC_RAMADDR_MASK 0xfe000000
290 #define SRC_RAMADDR_SHIFT 25
291 #define SRC_DAC1FREEZE (1UL << 21)
292 #define SRC_DAC2FREEZE (1UL << 20)
293 #define SRC_ADCFREEZE (1UL << 19)
294
295
296 #define SRC_WE 0x01000000 /* read/write control for SRC RAM */
297 #define SRC_BUSY 0x00800000 /* SRC busy */
298 #define SRC_DIS 0x00400000 /* 1 = disable SRC */
299 #define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */
300 #define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */
301 #define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */
302 #define SRC_CTLMASK 0x00780000
303 #define SRC_RAMDATA_MASK 0x0000ffff
304 #define SRC_RAMDATA_SHIFT 0
305
306 #define SRCREG_ADC 0x78
307 #define SRCREG_DAC1 0x70
308 #define SRCREG_DAC2 0x74
309 #define SRCREG_VOL_ADC 0x6c
310 #define SRCREG_VOL_DAC1 0x7c
311 #define SRCREG_VOL_DAC2 0x7e
312
313 #define SRCREG_TRUNC_N 0x00
314 #define SRCREG_INT_REGS 0x01
315 #define SRCREG_ACCUM_FRAC 0x02
316 #define SRCREG_VFREQ_FRAC 0x03
317
318 #define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
319 #define CODEC_PIADD_MASK 0x007f0000
320 #define CODEC_PIADD_SHIFT 16
321 #define CODEC_PIDAT_MASK 0x0000ffff
322 #define CODEC_PIDAT_SHIFT 0
323
324 #define CODEC_RDY 0x80000000 /* AC97 read data valid */
325 #define CODEC_WIP 0x40000000 /* AC97 write in progress */
326 #define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
327 #define CODEC_POADD_MASK 0x007f0000
328 #define CODEC_POADD_SHIFT 16
329 #define CODEC_PODAT_MASK 0x0000ffff
330 #define CODEC_PODAT_SHIFT 0
331
332
333 #define LEGACY_JFAST 0x80000000 /* fast joystick timing */
334 #define LEGACY_FIRQ 0x01000000 /* force IRQ */
335
336 #define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */
337 #define SCTRL_P2ENDINC 0x00380000 /* */
338 #define SCTRL_SH_P2ENDINC 19
339 #define SCTRL_P2STINC 0x00070000 /* */
340 #define SCTRL_SH_P2STINC 16
341 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
342 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
343 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
344 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
345 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
346 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
347 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
348 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
349 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
350 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
351 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
352 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
353 #define SCTRL_R1FMT 0x00000030 /* format mask */
354 #define SCTRL_SH_R1FMT 4
355 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
356 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
357 #define SCTRL_P2FMT 0x0000000c /* format mask */
358 #define SCTRL_SH_P2FMT 2
359 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
360 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
361 #define SCTRL_P1FMT 0x00000003 /* format mask */
362 #define SCTRL_SH_P1FMT 0
363
364
365 /* misc stuff */
366 #define POLL_COUNT 0x1000
367 #define FMODE_DAC 4 /* slight misuse of mode_t */
368
369 /* MIDI buffer sizes */
370
371 #define MIDIINBUF 256
372 #define MIDIOUTBUF 256
373
374 #define FMODE_MIDI_SHIFT 3
375 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
376 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
377
378 #define ES1371_MODULE_NAME "es1371"
379 #define PFX ES1371_MODULE_NAME ": "
380
381 /* --------------------------------------------------------------------- */
382
383 struct es1371_state {
384 /* magic */
385 unsigned int magic;
386
387 /* list of es1371 devices */
388 struct list_head devs;
389
390 /* the corresponding pci_dev structure */
391 struct pci_dev *dev;
392
393 /* soundcore stuff */
394 int dev_audio;
395 int dev_dac;
396 int dev_midi;
397
398 /* hardware resources */
399 unsigned long io; /* long for SPARC */
400 unsigned int irq;
401
402 /* PCI ID's */
403 u16 vendor;
404 u16 device;
405 u8 rev; /* the chip revision */
406
407 /* options */
408 int spdif_volume; /* S/PDIF output is enabled if != -1 */
409
410 #ifdef ES1371_DEBUG
411 /* debug /proc entry */
412 struct proc_dir_entry *ps;
413 #endif /* ES1371_DEBUG */
414
415 struct ac97_codec *codec;
416
417 /* wave stuff */
418 unsigned ctrl;
419 unsigned sctrl;
420 unsigned dac1rate, dac2rate, adcrate;
421
422 spinlock_t lock;
423 struct mutex open_mutex;
424 mode_t open_mode;
425 wait_queue_head_t open_wait;
426
427 struct dmabuf {
428 void *rawbuf;
429 dma_addr_t dmaaddr;
430 unsigned buforder;
431 unsigned numfrag;
432 unsigned fragshift;
433 unsigned hwptr, swptr;
434 unsigned total_bytes;
435 int count;
436 unsigned error; /* over/underrun */
437 wait_queue_head_t wait;
438 /* redundant, but makes calculations easier */
439 unsigned fragsize;
440 unsigned dmasize;
441 unsigned fragsamples;
442 /* OSS stuff */
443 unsigned mapped:1;
444 unsigned ready:1;
445 unsigned endcleared:1;
446 unsigned enabled:1;
447 unsigned ossfragshift;
448 int ossmaxfrags;
449 unsigned subdivision;
450 } dma_dac1, dma_dac2, dma_adc;
451
452 /* midi stuff */
453 struct {
454 unsigned ird, iwr, icnt;
455 unsigned ord, owr, ocnt;
456 wait_queue_head_t iwait;
457 wait_queue_head_t owait;
458 unsigned char ibuf[MIDIINBUF];
459 unsigned char obuf[MIDIOUTBUF];
460 } midi;
461
462 #ifdef SUPPORT_JOYSTICK
463 struct gameport *gameport;
464 #endif
465
466 struct mutex sem;
467 };
468
469 /* --------------------------------------------------------------------- */
470
471 static LIST_HEAD(devs);
472
473 /* --------------------------------------------------------------------- */
474
475 static inline unsigned ld2(unsigned int x)
476 {
477 unsigned r = 0;
478
479 if (x >= 0x10000) {
480 x >>= 16;
481 r += 16;
482 }
483 if (x >= 0x100) {
484 x >>= 8;
485 r += 8;
486 }
487 if (x >= 0x10) {
488 x >>= 4;
489 r += 4;
490 }
491 if (x >= 4) {
492 x >>= 2;
493 r += 2;
494 }
495 if (x >= 2)
496 r++;
497 return r;
498 }
499
500 /* --------------------------------------------------------------------- */
501
502 static unsigned wait_src_ready(struct es1371_state *s)
503 {
504 unsigned int t, r;
505
506 for (t = 0; t < POLL_COUNT; t++) {
507 if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
508 return r;
509 udelay(1);
510 }
511 printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
512 return r;
513 }
514
515 static unsigned src_read(struct es1371_state *s, unsigned reg)
516 {
517 unsigned int temp,i,orig;
518
519 /* wait for ready */
520 temp = wait_src_ready (s);
521
522 /* we can only access the SRC at certain times, make sure
523 we're allowed to before we read */
524
525 orig = temp;
526 /* expose the SRC state bits */
527 outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
528 s->io + ES1371_REG_SRCONV);
529
530 /* now, wait for busy and the correct time to read */
531 temp = wait_src_ready (s);
532
533 if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
534 /* wait for the right state */
535 for (i=0; i<POLL_COUNT; i++){
536 temp = inl (s->io + ES1371_REG_SRCONV);
537 if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
538 break;
539 }
540 }
541
542 /* hide the state bits */
543 outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
544 return temp;
545
546
547 }
548
549 static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
550 {
551
552 unsigned int r;
553
554 r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
555 r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
556 r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
557 outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
558
559 }
560
561 /* --------------------------------------------------------------------- */
562
563 /* most of the following here is black magic */
564 static void set_adc_rate(struct es1371_state *s, unsigned rate)
565 {
566 unsigned long flags;
567 unsigned int n, truncm, freq;
568
569 if (rate > 48000)
570 rate = 48000;
571 if (rate < 4000)
572 rate = 4000;
573 n = rate / 3000;
574 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
575 n--;
576 truncm = (21 * n - 1) | 1;
577 freq = ((48000UL << 15) / rate) * n;
578 s->adcrate = (48000UL << 15) / (freq / n);
579 spin_lock_irqsave(&s->lock, flags);
580 if (rate >= 24000) {
581 if (truncm > 239)
582 truncm = 239;
583 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
584 (((239 - truncm) >> 1) << 9) | (n << 4));
585 } else {
586 if (truncm > 119)
587 truncm = 119;
588 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
589 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
590 }
591 src_write(s, SRCREG_ADC+SRCREG_INT_REGS,
592 (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
593 ((freq >> 5) & 0xfc00));
594 src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
595 src_write(s, SRCREG_VOL_ADC, n << 8);
596 src_write(s, SRCREG_VOL_ADC+1, n << 8);
597 spin_unlock_irqrestore(&s->lock, flags);
598 }
599
600
601 static void set_dac1_rate(struct es1371_state *s, unsigned rate)
602 {
603 unsigned long flags;
604 unsigned int freq, r;
605
606 if (rate > 48000)
607 rate = 48000;
608 if (rate < 4000)
609 rate = 4000;
610 freq = ((rate << 15) + 1500) / 3000;
611 s->dac1rate = (freq * 3000 + 16384) >> 15;
612 spin_lock_irqsave(&s->lock, flags);
613 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
614 outl(r, s->io + ES1371_REG_SRCONV);
615 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS,
616 (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
617 ((freq >> 5) & 0xfc00));
618 src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
619 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
620 outl(r, s->io + ES1371_REG_SRCONV);
621 spin_unlock_irqrestore(&s->lock, flags);
622 }
623
624 static void set_dac2_rate(struct es1371_state *s, unsigned rate)
625 {
626 unsigned long flags;
627 unsigned int freq, r;
628
629 if (rate > 48000)
630 rate = 48000;
631 if (rate < 4000)
632 rate = 4000;
633 freq = ((rate << 15) + 1500) / 3000;
634 s->dac2rate = (freq * 3000 + 16384) >> 15;
635 spin_lock_irqsave(&s->lock, flags);
636 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
637 outl(r, s->io + ES1371_REG_SRCONV);
638 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS,
639 (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
640 ((freq >> 5) & 0xfc00));
641 src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
642 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
643 outl(r, s->io + ES1371_REG_SRCONV);
644 spin_unlock_irqrestore(&s->lock, flags);
645 }
646
647 /* --------------------------------------------------------------------- */
648
649 static void __devinit src_init(struct es1371_state *s)
650 {
651 unsigned int i;
652
653 /* before we enable or disable the SRC we need
654 to wait for it to become ready */
655 wait_src_ready(s);
656
657 outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
658
659 for (i = 0; i < 0x80; i++)
660 src_write(s, i, 0);
661
662 src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
663 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
664 src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
665 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
666 src_write(s, SRCREG_VOL_ADC, 1 << 12);
667 src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
668 src_write(s, SRCREG_VOL_DAC1, 1 << 12);
669 src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
670 src_write(s, SRCREG_VOL_DAC2, 1 << 12);
671 src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
672 set_adc_rate(s, 22050);
673 set_dac1_rate(s, 22050);
674 set_dac2_rate(s, 22050);
675
676 /* WARNING:
677 * enabling the sample rate converter without properly programming
678 * its parameters causes the chip to lock up (the SRC busy bit will
679 * be stuck high, and I've found no way to rectify this other than
680 * power cycle)
681 */
682 wait_src_ready(s);
683 outl(0, s->io+ES1371_REG_SRCONV);
684 }
685
686 /* --------------------------------------------------------------------- */
687
688 static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
689 {
690 struct es1371_state *s = (struct es1371_state *)codec->private_data;
691 unsigned long flags;
692 unsigned t, x;
693
694 spin_lock_irqsave(&s->lock, flags);
695 for (t = 0; t < POLL_COUNT; t++)
696 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
697 break;
698
699 /* save the current state for later */
700 x = wait_src_ready(s);
701
702 /* enable SRC state data in SRC mux */
703 outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
704 s->io+ES1371_REG_SRCONV);
705
706 /* wait for not busy (state 0) first to avoid
707 transition states */
708 for (t=0; t<POLL_COUNT; t++){
709 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
710 break;
711 udelay(1);
712 }
713
714 /* wait for a SAFE time to write addr/data and then do it, dammit */
715 for (t=0; t<POLL_COUNT; t++){
716 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
717 break;
718 udelay(1);
719 }
720
721 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
722 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
723
724 /* restore SRC reg */
725 wait_src_ready(s);
726 outl(x, s->io+ES1371_REG_SRCONV);
727 spin_unlock_irqrestore(&s->lock, flags);
728 }
729
730 static u16 rdcodec(struct ac97_codec *codec, u8 addr)
731 {
732 struct es1371_state *s = (struct es1371_state *)codec->private_data;
733 unsigned long flags;
734 unsigned t, x;
735
736 spin_lock_irqsave(&s->lock, flags);
737
738 /* wait for WIP to go away */
739 for (t = 0; t < 0x1000; t++)
740 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
741 break;
742
743 /* save the current state for later */
744 x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
745
746 /* enable SRC state data in SRC mux */
747 outl( x | 0x00010000,
748 s->io+ES1371_REG_SRCONV);
749
750 /* wait for not busy (state 0) first to avoid
751 transition states */
752 for (t=0; t<POLL_COUNT; t++){
753 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
754 break;
755 udelay(1);
756 }
757
758 /* wait for a SAFE time to write addr/data and then do it, dammit */
759 for (t=0; t<POLL_COUNT; t++){
760 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
761 break;
762 udelay(1);
763 }
764
765 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
766 /* restore SRC reg */
767 wait_src_ready(s);
768 outl(x, s->io+ES1371_REG_SRCONV);
769
770 /* wait for WIP again */
771 for (t = 0; t < 0x1000; t++)
772 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
773 break;
774
775 /* now wait for the stinkin' data (RDY) */
776 for (t = 0; t < POLL_COUNT; t++)
777 if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
778 break;
779
780 spin_unlock_irqrestore(&s->lock, flags);
781 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
782 }
783
784 /* --------------------------------------------------------------------- */
785
786 static inline void stop_adc(struct es1371_state *s)
787 {
788 unsigned long flags;
789
790 spin_lock_irqsave(&s->lock, flags);
791 s->ctrl &= ~CTRL_ADC_EN;
792 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
793 spin_unlock_irqrestore(&s->lock, flags);
794 }
795
796 static inline void stop_dac1(struct es1371_state *s)
797 {
798 unsigned long flags;
799
800 spin_lock_irqsave(&s->lock, flags);
801 s->ctrl &= ~CTRL_DAC1_EN;
802 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
803 spin_unlock_irqrestore(&s->lock, flags);
804 }
805
806 static inline void stop_dac2(struct es1371_state *s)
807 {
808 unsigned long flags;
809
810 spin_lock_irqsave(&s->lock, flags);
811 s->ctrl &= ~CTRL_DAC2_EN;
812 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
813 spin_unlock_irqrestore(&s->lock, flags);
814 }
815
816 static void start_dac1(struct es1371_state *s)
817 {
818 unsigned long flags;
819 unsigned fragremain, fshift;
820
821 spin_lock_irqsave(&s->lock, flags);
822 if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
823 && s->dma_dac1.ready) {
824 s->ctrl |= CTRL_DAC1_EN;
825 s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
826 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
827 fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
828 fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
829 if (fragremain < 2*fshift)
830 fragremain = s->dma_dac1.fragsize;
831 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
832 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
833 outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
834 }
835 spin_unlock_irqrestore(&s->lock, flags);
836 }
837
838 static void start_dac2(struct es1371_state *s)
839 {
840 unsigned long flags;
841 unsigned fragremain, fshift;
842
843 spin_lock_irqsave(&s->lock, flags);
844 if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
845 && s->dma_dac2.ready) {
846 s->ctrl |= CTRL_DAC2_EN;
847 s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN |
848 SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
849 (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) |
850 (0 << SCTRL_SH_P2STINC);
851 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
852 fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
853 fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
854 if (fragremain < 2*fshift)
855 fragremain = s->dma_dac2.fragsize;
856 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
857 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
858 outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
859 }
860 spin_unlock_irqrestore(&s->lock, flags);
861 }
862
863 static void start_adc(struct es1371_state *s)
864 {
865 unsigned long flags;
866 unsigned fragremain, fshift;
867
868 spin_lock_irqsave(&s->lock, flags);
869 if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
870 && s->dma_adc.ready) {
871 s->ctrl |= CTRL_ADC_EN;
872 s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
873 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
874 fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
875 fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
876 if (fragremain < 2*fshift)
877 fragremain = s->dma_adc.fragsize;
878 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
879 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
880 outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
881 }
882 spin_unlock_irqrestore(&s->lock, flags);
883 }
884
885 /* --------------------------------------------------------------------- */
886
887 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
888 #define DMABUF_MINORDER 1
889
890
891 static inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
892 {
893 struct page *page, *pend;
894
895 if (db->rawbuf) {
896 /* undo marking the pages as reserved */
897 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
898 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
899 ClearPageReserved(page);
900 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
901 }
902 db->rawbuf = NULL;
903 db->mapped = db->ready = 0;
904 }
905
906 static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
907 {
908 int order;
909 unsigned bytepersec;
910 unsigned bufs;
911 struct page *page, *pend;
912
913 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
914 if (!db->rawbuf) {
915 db->ready = db->mapped = 0;
916 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
917 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
918 break;
919 if (!db->rawbuf)
920 return -ENOMEM;
921 db->buforder = order;
922 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
923 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
924 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
925 SetPageReserved(page);
926 }
927 fmt &= ES1371_FMT_MASK;
928 bytepersec = rate << sample_shift[fmt];
929 bufs = PAGE_SIZE << db->buforder;
930 if (db->ossfragshift) {
931 if ((1000 << db->ossfragshift) < bytepersec)
932 db->fragshift = ld2(bytepersec/1000);
933 else
934 db->fragshift = db->ossfragshift;
935 } else {
936 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
937 if (db->fragshift < 3)
938 db->fragshift = 3;
939 }
940 db->numfrag = bufs >> db->fragshift;
941 while (db->numfrag < 4 && db->fragshift > 3) {
942 db->fragshift--;
943 db->numfrag = bufs >> db->fragshift;
944 }
945 db->fragsize = 1 << db->fragshift;
946 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
947 db->numfrag = db->ossmaxfrags;
948 db->fragsamples = db->fragsize >> sample_shift[fmt];
949 db->dmasize = db->numfrag << db->fragshift;
950 memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
951 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
952 outl(db->dmaaddr, s->io+(reg & 0xff));
953 outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
954 db->enabled = 1;
955 db->ready = 1;
956 return 0;
957 }
958
959 static inline int prog_dmabuf_adc(struct es1371_state *s)
960 {
961 stop_adc(s);
962 return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK,
963 ES1371_REG_ADC_FRAMEADR);
964 }
965
966 static inline int prog_dmabuf_dac2(struct es1371_state *s)
967 {
968 stop_dac2(s);
969 return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK,
970 ES1371_REG_DAC2_FRAMEADR);
971 }
972
973 static inline int prog_dmabuf_dac1(struct es1371_state *s)
974 {
975 stop_dac1(s);
976 return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
977 ES1371_REG_DAC1_FRAMEADR);
978 }
979
980 static inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
981 {
982 unsigned hwptr, diff;
983
984 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
985 hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
986 diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
987 db->hwptr = hwptr;
988 return diff;
989 }
990
991 static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
992 {
993 if (bptr + len > bsize) {
994 unsigned x = bsize - bptr;
995 memset(((char *)buf) + bptr, c, x);
996 bptr = 0;
997 len -= x;
998 }
999 memset(((char *)buf) + bptr, c, len);
1000 }
1001
1002 /* call with spinlock held! */
1003 static void es1371_update_ptr(struct es1371_state *s)
1004 {
1005 int diff;
1006
1007 /* update ADC pointer */
1008 if (s->ctrl & CTRL_ADC_EN) {
1009 diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);
1010 s->dma_adc.total_bytes += diff;
1011 s->dma_adc.count += diff;
1012 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1013 wake_up(&s->dma_adc.wait);
1014 if (!s->dma_adc.mapped) {
1015 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1016 s->ctrl &= ~CTRL_ADC_EN;
1017 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1018 s->dma_adc.error++;
1019 }
1020 }
1021 }
1022 /* update DAC1 pointer */
1023 if (s->ctrl & CTRL_DAC1_EN) {
1024 diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT);
1025 s->dma_dac1.total_bytes += diff;
1026 if (s->dma_dac1.mapped) {
1027 s->dma_dac1.count += diff;
1028 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
1029 wake_up(&s->dma_dac1.wait);
1030 } else {
1031 s->dma_dac1.count -= diff;
1032 if (s->dma_dac1.count <= 0) {
1033 s->ctrl &= ~CTRL_DAC1_EN;
1034 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1035 s->dma_dac1.error++;
1036 } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) {
1037 clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr,
1038 s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80);
1039 s->dma_dac1.endcleared = 1;
1040 }
1041 if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize)
1042 wake_up(&s->dma_dac1.wait);
1043 }
1044 }
1045 /* update DAC2 pointer */
1046 if (s->ctrl & CTRL_DAC2_EN) {
1047 diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT);
1048 s->dma_dac2.total_bytes += diff;
1049 if (s->dma_dac2.mapped) {
1050 s->dma_dac2.count += diff;
1051 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1052 wake_up(&s->dma_dac2.wait);
1053 } else {
1054 s->dma_dac2.count -= diff;
1055 if (s->dma_dac2.count <= 0) {
1056 s->ctrl &= ~CTRL_DAC2_EN;
1057 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1058 s->dma_dac2.error++;
1059 } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) {
1060 clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr,
1061 s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80);
1062 s->dma_dac2.endcleared = 1;
1063 }
1064 if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize)
1065 wake_up(&s->dma_dac2.wait);
1066 }
1067 }
1068 }
1069
1070 /* hold spinlock for the following! */
1071 static void es1371_handle_midi(struct es1371_state *s)
1072 {
1073 unsigned char ch;
1074 int wake;
1075
1076 if (!(s->ctrl & CTRL_UART_EN))
1077 return;
1078 wake = 0;
1079 while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) {
1080 ch = inb(s->io+ES1371_REG_UART_DATA);
1081 if (s->midi.icnt < MIDIINBUF) {
1082 s->midi.ibuf[s->midi.iwr] = ch;
1083 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1084 s->midi.icnt++;
1085 }
1086 wake = 1;
1087 }
1088 if (wake)
1089 wake_up(&s->midi.iwait);
1090 wake = 0;
1091 while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) {
1092 outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA);
1093 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1094 s->midi.ocnt--;
1095 if (s->midi.ocnt < MIDIOUTBUF-16)
1096 wake = 1;
1097 }
1098 if (wake)
1099 wake_up(&s->midi.owait);
1100 outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL);
1101 }
1102
1103 static irqreturn_t es1371_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1104 {
1105 struct es1371_state *s = (struct es1371_state *)dev_id;
1106 unsigned int intsrc, sctl;
1107
1108 /* fastpath out, to ease interrupt sharing */
1109 intsrc = inl(s->io+ES1371_REG_STATUS);
1110 if (!(intsrc & 0x80000000))
1111 return IRQ_NONE;
1112 spin_lock(&s->lock);
1113 /* clear audio interrupts first */
1114 sctl = s->sctrl;
1115 if (intsrc & STAT_ADC)
1116 sctl &= ~SCTRL_R1INTEN;
1117 if (intsrc & STAT_DAC1)
1118 sctl &= ~SCTRL_P1INTEN;
1119 if (intsrc & STAT_DAC2)
1120 sctl &= ~SCTRL_P2INTEN;
1121 outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL);
1122 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1123 es1371_update_ptr(s);
1124 es1371_handle_midi(s);
1125 spin_unlock(&s->lock);
1126 return IRQ_HANDLED;
1127 }
1128
1129 /* --------------------------------------------------------------------- */
1130
1131 static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
1132
1133 #define VALIDATE_STATE(s) \
1134 ({ \
1135 if (!(s) || (s)->magic != ES1371_MAGIC) { \
1136 printk(invalid_magic); \
1137 return -ENXIO; \
1138 } \
1139 })
1140
1141 /* --------------------------------------------------------------------- */
1142
1143 /* Conversion table for S/PDIF PCM volume emulation through the SRC */
1144 /* dB-linear table of DAC vol values; -0dB to -46.5dB with mute */
1145 static const unsigned short DACVolTable[101] =
1146 {
1147 0x1000, 0x0f2a, 0x0e60, 0x0da0, 0x0cea, 0x0c3e, 0x0b9a, 0x0aff,
1148 0x0a6d, 0x09e1, 0x095e, 0x08e1, 0x086a, 0x07fa, 0x078f, 0x072a,
1149 0x06cb, 0x0670, 0x061a, 0x05c9, 0x057b, 0x0532, 0x04ed, 0x04ab,
1150 0x046d, 0x0432, 0x03fa, 0x03c5, 0x0392, 0x0363, 0x0335, 0x030b,
1151 0x02e2, 0x02bc, 0x0297, 0x0275, 0x0254, 0x0235, 0x0217, 0x01fb,
1152 0x01e1, 0x01c8, 0x01b0, 0x0199, 0x0184, 0x0170, 0x015d, 0x014b,
1153 0x0139, 0x0129, 0x0119, 0x010b, 0x00fd, 0x00f0, 0x00e3, 0x00d7,
1154 0x00cc, 0x00c1, 0x00b7, 0x00ae, 0x00a5, 0x009c, 0x0094, 0x008c,
1155 0x0085, 0x007e, 0x0077, 0x0071, 0x006b, 0x0066, 0x0060, 0x005b,
1156 0x0057, 0x0052, 0x004e, 0x004a, 0x0046, 0x0042, 0x003f, 0x003c,
1157 0x0038, 0x0036, 0x0033, 0x0030, 0x002e, 0x002b, 0x0029, 0x0027,
1158 0x0025, 0x0023, 0x0021, 0x001f, 0x001e, 0x001c, 0x001b, 0x0019,
1159 0x0018, 0x0017, 0x0016, 0x0014, 0x0000
1160 };
1161
1162 /*
1163 * when we are in S/PDIF mode, we want to disable any analog output so
1164 * we filter the mixer ioctls
1165 */
1166 static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, unsigned long arg)
1167 {
1168 struct es1371_state *s = (struct es1371_state *)codec->private_data;
1169 int val;
1170 unsigned long flags;
1171 unsigned int left, right;
1172
1173 VALIDATE_STATE(s);
1174 /* filter mixer ioctls to catch PCM and MASTER volume when in S/PDIF mode */
1175 if (s->spdif_volume == -1)
1176 return codec->mixer_ioctl(codec, cmd, arg);
1177 switch (cmd) {
1178 case SOUND_MIXER_WRITE_VOLUME:
1179 return 0;
1180
1181 case SOUND_MIXER_WRITE_PCM: /* use SRC for PCM volume */
1182 if (get_user(val, (int __user *)arg))
1183 return -EFAULT;
1184 right = ((val >> 8) & 0xff);
1185 left = (val & 0xff);
1186 if (right > 100)
1187 right = 100;
1188 if (left > 100)
1189 left = 100;
1190 s->spdif_volume = (right << 8) | left;
1191 spin_lock_irqsave(&s->lock, flags);
1192 src_write(s, SRCREG_VOL_DAC2, DACVolTable[100 - left]);
1193 src_write(s, SRCREG_VOL_DAC2+1, DACVolTable[100 - right]);
1194 spin_unlock_irqrestore(&s->lock, flags);
1195 return 0;
1196
1197 case SOUND_MIXER_READ_PCM:
1198 return put_user(s->spdif_volume, (int __user *)arg);
1199 }
1200 return codec->mixer_ioctl(codec, cmd, arg);
1201 }
1202
1203 /* --------------------------------------------------------------------- */
1204
1205 /*
1206 * AC97 Mixer Register to Connections mapping of the Concert 97 board
1207 *
1208 * AC97_MASTER_VOL_STEREO Line Out
1209 * AC97_MASTER_VOL_MONO TAD Output
1210 * AC97_PCBEEP_VOL none
1211 * AC97_PHONE_VOL TAD Input (mono)
1212 * AC97_MIC_VOL MIC Input (mono)
1213 * AC97_LINEIN_VOL Line Input (stereo)
1214 * AC97_CD_VOL CD Input (stereo)
1215 * AC97_VIDEO_VOL none
1216 * AC97_AUX_VOL Aux Input (stereo)
1217 * AC97_PCMOUT_VOL Wave Output (stereo)
1218 */
1219
1220 static int es1371_open_mixdev(struct inode *inode, struct file *file)
1221 {
1222 int minor = iminor(inode);
1223 struct list_head *list;
1224 struct es1371_state *s;
1225
1226 for (list = devs.next; ; list = list->next) {
1227 if (list == &devs)
1228 return -ENODEV;
1229 s = list_entry(list, struct es1371_state, devs);
1230 if (s->codec->dev_mixer == minor)
1231 break;
1232 }
1233 VALIDATE_STATE(s);
1234 file->private_data = s;
1235 return nonseekable_open(inode, file);
1236 }
1237
1238 static int es1371_release_mixdev(struct inode *inode, struct file *file)
1239 {
1240 struct es1371_state *s = (struct es1371_state *)file->private_data;
1241
1242 VALIDATE_STATE(s);
1243 return 0;
1244 }
1245
1246 static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1247 {
1248 struct es1371_state *s = (struct es1371_state *)file->private_data;
1249 struct ac97_codec *codec = s->codec;
1250
1251 return mixdev_ioctl(codec, cmd, arg);
1252 }
1253
1254 static /*const*/ struct file_operations es1371_mixer_fops = {
1255 .owner = THIS_MODULE,
1256 .llseek = no_llseek,
1257 .ioctl = es1371_ioctl_mixdev,
1258 .open = es1371_open_mixdev,
1259 .release = es1371_release_mixdev,
1260 };
1261
1262 /* --------------------------------------------------------------------- */
1263
1264 static int drain_dac1(struct es1371_state *s, int nonblock)
1265 {
1266 DECLARE_WAITQUEUE(wait, current);
1267 unsigned long flags;
1268 int count, tmo;
1269
1270 if (s->dma_dac1.mapped || !s->dma_dac1.ready)
1271 return 0;
1272 add_wait_queue(&s->dma_dac1.wait, &wait);
1273 for (;;) {
1274 __set_current_state(TASK_INTERRUPTIBLE);
1275 spin_lock_irqsave(&s->lock, flags);
1276 count = s->dma_dac1.count;
1277 spin_unlock_irqrestore(&s->lock, flags);
1278 if (count <= 0)
1279 break;
1280 if (signal_pending(current))
1281 break;
1282 if (nonblock) {
1283 remove_wait_queue(&s->dma_dac1.wait, &wait);
1284 set_current_state(TASK_RUNNING);
1285 return -EBUSY;
1286 }
1287 tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate;
1288 tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
1289 if (!schedule_timeout(tmo + 1))
1290 DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");)
1291 }
1292 remove_wait_queue(&s->dma_dac1.wait, &wait);
1293 set_current_state(TASK_RUNNING);
1294 if (signal_pending(current))
1295 return -ERESTARTSYS;
1296 return 0;
1297 }
1298
1299 static int drain_dac2(struct es1371_state *s, int nonblock)
1300 {
1301 DECLARE_WAITQUEUE(wait, current);
1302 unsigned long flags;
1303 int count, tmo;
1304
1305 if (s->dma_dac2.mapped || !s->dma_dac2.ready)
1306 return 0;
1307 add_wait_queue(&s->dma_dac2.wait, &wait);
1308 for (;;) {
1309 __set_current_state(TASK_UNINTERRUPTIBLE);
1310 spin_lock_irqsave(&s->lock, flags);
1311 count = s->dma_dac2.count;
1312 spin_unlock_irqrestore(&s->lock, flags);
1313 if (count <= 0)
1314 break;
1315 if (signal_pending(current))
1316 break;
1317 if (nonblock) {
1318 remove_wait_queue(&s->dma_dac2.wait, &wait);
1319 set_current_state(TASK_RUNNING);
1320 return -EBUSY;
1321 }
1322 tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate;
1323 tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
1324 if (!schedule_timeout(tmo + 1))
1325 DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");)
1326 }
1327 remove_wait_queue(&s->dma_dac2.wait, &wait);
1328 set_current_state(TASK_RUNNING);
1329 if (signal_pending(current))
1330 return -ERESTARTSYS;
1331 return 0;
1332 }
1333
1334 /* --------------------------------------------------------------------- */
1335
1336 static ssize_t es1371_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1337 {
1338 struct es1371_state *s = (struct es1371_state *)file->private_data;
1339 DECLARE_WAITQUEUE(wait, current);
1340 ssize_t ret = 0;
1341 unsigned long flags;
1342 unsigned swptr;
1343 int cnt;
1344
1345 VALIDATE_STATE(s);
1346 if (s->dma_adc.mapped)
1347 return -ENXIO;
1348 if (!access_ok(VERIFY_WRITE, buffer, count))
1349 return -EFAULT;
1350 mutex_lock(&s->sem);
1351 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1352 goto out2;
1353
1354 add_wait_queue(&s->dma_adc.wait, &wait);
1355 while (count > 0) {
1356 spin_lock_irqsave(&s->lock, flags);
1357 swptr = s->dma_adc.swptr;
1358 cnt = s->dma_adc.dmasize-swptr;
1359 if (s->dma_adc.count < cnt)
1360 cnt = s->dma_adc.count;
1361 if (cnt <= 0)
1362 __set_current_state(TASK_INTERRUPTIBLE);
1363 spin_unlock_irqrestore(&s->lock, flags);
1364 if (cnt > count)
1365 cnt = count;
1366 if (cnt <= 0) {
1367 if (s->dma_adc.enabled)
1368 start_adc(s);
1369 if (file->f_flags & O_NONBLOCK) {
1370 if (!ret)
1371 ret = -EAGAIN;
1372 goto out;
1373 }
1374 mutex_unlock(&s->sem);
1375 schedule();
1376 if (signal_pending(current)) {
1377 if (!ret)
1378 ret = -ERESTARTSYS;
1379 goto out2;
1380 }
1381 mutex_lock(&s->sem);
1382 if (s->dma_adc.mapped)
1383 {
1384 ret = -ENXIO;
1385 goto out;
1386 }
1387 continue;
1388 }
1389 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1390 if (!ret)
1391 ret = -EFAULT;
1392 goto out;
1393 }
1394 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1395 spin_lock_irqsave(&s->lock, flags);
1396 s->dma_adc.swptr = swptr;
1397 s->dma_adc.count -= cnt;
1398 spin_unlock_irqrestore(&s->lock, flags);
1399 count -= cnt;
1400 buffer += cnt;
1401 ret += cnt;
1402 if (s->dma_adc.enabled)
1403 start_adc(s);
1404 }
1405 out:
1406 mutex_unlock(&s->sem);
1407 out2:
1408 remove_wait_queue(&s->dma_adc.wait, &wait);
1409 set_current_state(TASK_RUNNING);
1410 return ret;
1411 }
1412
1413 static ssize_t es1371_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1414 {
1415 struct es1371_state *s = (struct es1371_state *)file->private_data;
1416 DECLARE_WAITQUEUE(wait, current);
1417 ssize_t ret;
1418 unsigned long flags;
1419 unsigned swptr;
1420 int cnt;
1421
1422 VALIDATE_STATE(s);
1423 if (s->dma_dac2.mapped)
1424 return -ENXIO;
1425 if (!access_ok(VERIFY_READ, buffer, count))
1426 return -EFAULT;
1427 mutex_lock(&s->sem);
1428 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1429 goto out3;
1430 ret = 0;
1431 add_wait_queue(&s->dma_dac2.wait, &wait);
1432 while (count > 0) {
1433 spin_lock_irqsave(&s->lock, flags);
1434 if (s->dma_dac2.count < 0) {
1435 s->dma_dac2.count = 0;
1436 s->dma_dac2.swptr = s->dma_dac2.hwptr;
1437 }
1438 swptr = s->dma_dac2.swptr;
1439 cnt = s->dma_dac2.dmasize-swptr;
1440 if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize)
1441 cnt = s->dma_dac2.dmasize - s->dma_dac2.count;
1442 if (cnt <= 0)
1443 __set_current_state(TASK_INTERRUPTIBLE);
1444 spin_unlock_irqrestore(&s->lock, flags);
1445 if (cnt > count)
1446 cnt = count;
1447 if (cnt <= 0) {
1448 if (s->dma_dac2.enabled)
1449 start_dac2(s);
1450 if (file->f_flags & O_NONBLOCK) {
1451 if (!ret)
1452 ret = -EAGAIN;
1453 goto out;
1454 }
1455 mutex_unlock(&s->sem);
1456 schedule();
1457 if (signal_pending(current)) {
1458 if (!ret)
1459 ret = -ERESTARTSYS;
1460 goto out2;
1461 }
1462 mutex_lock(&s->sem);
1463 if (s->dma_dac2.mapped)
1464 {
1465 ret = -ENXIO;
1466 goto out;
1467 }
1468 continue;
1469 }
1470 if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) {
1471 if (!ret)
1472 ret = -EFAULT;
1473 goto out;
1474 }
1475 swptr = (swptr + cnt) % s->dma_dac2.dmasize;
1476 spin_lock_irqsave(&s->lock, flags);
1477 s->dma_dac2.swptr = swptr;
1478 s->dma_dac2.count += cnt;
1479 s->dma_dac2.endcleared = 0;
1480 spin_unlock_irqrestore(&s->lock, flags);
1481 count -= cnt;
1482 buffer += cnt;
1483 ret += cnt;
1484 if (s->dma_dac2.enabled)
1485 start_dac2(s);
1486 }
1487 out:
1488 mutex_unlock(&s->sem);
1489 out2:
1490 remove_wait_queue(&s->dma_dac2.wait, &wait);
1491 out3:
1492 set_current_state(TASK_RUNNING);
1493 return ret;
1494 }
1495
1496 /* No kernel lock - we have our own spinlock */
1497 static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait)
1498 {
1499 struct es1371_state *s = (struct es1371_state *)file->private_data;
1500 unsigned long flags;
1501 unsigned int mask = 0;
1502
1503 VALIDATE_STATE(s);
1504 if (file->f_mode & FMODE_WRITE) {
1505 if (!s->dma_dac2.ready && prog_dmabuf_dac2(s))
1506 return 0;
1507 poll_wait(file, &s->dma_dac2.wait, wait);
1508 }
1509 if (file->f_mode & FMODE_READ) {
1510 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1511 return 0;
1512 poll_wait(file, &s->dma_adc.wait, wait);
1513 }
1514 spin_lock_irqsave(&s->lock, flags);
1515 es1371_update_ptr(s);
1516 if (file->f_mode & FMODE_READ) {
1517 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1518 mask |= POLLIN | POLLRDNORM;
1519 }
1520 if (file->f_mode & FMODE_WRITE) {
1521 if (s->dma_dac2.mapped) {
1522 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1523 mask |= POLLOUT | POLLWRNORM;
1524 } else {
1525 if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize)
1526 mask |= POLLOUT | POLLWRNORM;
1527 }
1528 }
1529 spin_unlock_irqrestore(&s->lock, flags);
1530 return mask;
1531 }
1532
1533 static int es1371_mmap(struct file *file, struct vm_area_struct *vma)
1534 {
1535 struct es1371_state *s = (struct es1371_state *)file->private_data;
1536 struct dmabuf *db;
1537 int ret = 0;
1538 unsigned long size;
1539
1540 VALIDATE_STATE(s);
1541 lock_kernel();
1542 mutex_lock(&s->sem);
1543
1544 if (vma->vm_flags & VM_WRITE) {
1545 if ((ret = prog_dmabuf_dac2(s)) != 0) {
1546 goto out;
1547 }
1548 db = &s->dma_dac2;
1549 } else if (vma->vm_flags & VM_READ) {
1550 if ((ret = prog_dmabuf_adc(s)) != 0) {
1551 goto out;
1552 }
1553 db = &s->dma_adc;
1554 } else {
1555 ret = -EINVAL;
1556 goto out;
1557 }
1558 if (vma->vm_pgoff != 0) {
1559 ret = -EINVAL;
1560 goto out;
1561 }
1562 size = vma->vm_end - vma->vm_start;
1563 if (size > (PAGE_SIZE << db->buforder)) {
1564 ret = -EINVAL;
1565 goto out;
1566 }
1567 if (remap_pfn_range(vma, vma->vm_start,
1568 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1569 size, vma->vm_page_prot)) {
1570 ret = -EAGAIN;
1571 goto out;
1572 }
1573 db->mapped = 1;
1574 out:
1575 mutex_unlock(&s->sem);
1576 unlock_kernel();
1577 return ret;
1578 }
1579
1580 static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1581 {
1582 struct es1371_state *s = (struct es1371_state *)file->private_data;
1583 unsigned long flags;
1584 audio_buf_info abinfo;
1585 count_info cinfo;
1586 int count;
1587 int val, mapped, ret;
1588 void __user *argp = (void __user *)arg;
1589 int __user *p = argp;
1590
1591 VALIDATE_STATE(s);
1592 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) ||
1593 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1594 switch (cmd) {
1595 case OSS_GETVERSION:
1596 return put_user(SOUND_VERSION, p);
1597
1598 case SNDCTL_DSP_SYNC:
1599 if (file->f_mode & FMODE_WRITE)
1600 return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/);
1601 return 0;
1602
1603 case SNDCTL_DSP_SETDUPLEX:
1604 return 0;
1605
1606 case SNDCTL_DSP_GETCAPS:
1607 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1608
1609 case SNDCTL_DSP_RESET:
1610 if (file->f_mode & FMODE_WRITE) {
1611 stop_dac2(s);
1612 synchronize_irq(s->irq);
1613 s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0;
1614 }
1615 if (file->f_mode & FMODE_READ) {
1616 stop_adc(s);
1617 synchronize_irq(s->irq);
1618 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1619 }
1620 return 0;
1621
1622 case SNDCTL_DSP_SPEED:
1623 if (get_user(val, p))
1624 return -EFAULT;
1625 if (val >= 0) {
1626 if (file->f_mode & FMODE_READ) {
1627 stop_adc(s);
1628 s->dma_adc.ready = 0;
1629 set_adc_rate(s, val);
1630 }
1631 if (file->f_mode & FMODE_WRITE) {
1632 stop_dac2(s);
1633 s->dma_dac2.ready = 0;
1634 set_dac2_rate(s, val);
1635 }
1636 }
1637 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
1638
1639 case SNDCTL_DSP_STEREO:
1640 if (get_user(val, p))
1641 return -EFAULT;
1642 if (file->f_mode & FMODE_READ) {
1643 stop_adc(s);
1644 s->dma_adc.ready = 0;
1645 spin_lock_irqsave(&s->lock, flags);
1646 if (val)
1647 s->sctrl |= SCTRL_R1SMB;
1648 else
1649 s->sctrl &= ~SCTRL_R1SMB;
1650 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1651 spin_unlock_irqrestore(&s->lock, flags);
1652 }
1653 if (file->f_mode & FMODE_WRITE) {
1654 stop_dac2(s);
1655 s->dma_dac2.ready = 0;
1656 spin_lock_irqsave(&s->lock, flags);
1657 if (val)
1658 s->sctrl |= SCTRL_P2SMB;
1659 else
1660 s->sctrl &= ~SCTRL_P2SMB;
1661 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1662 spin_unlock_irqrestore(&s->lock, flags);
1663 }
1664 return 0;
1665
1666 case SNDCTL_DSP_CHANNELS:
1667 if (get_user(val, p))
1668 return -EFAULT;
1669 if (val != 0) {
1670 if (file->f_mode & FMODE_READ) {
1671 stop_adc(s);
1672 s->dma_adc.ready = 0;
1673 spin_lock_irqsave(&s->lock, flags);
1674 if (val >= 2)
1675 s->sctrl |= SCTRL_R1SMB;
1676 else
1677 s->sctrl &= ~SCTRL_R1SMB;
1678 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1679 spin_unlock_irqrestore(&s->lock, flags);
1680 }
1681 if (file->f_mode & FMODE_WRITE) {
1682 stop_dac2(s);
1683 s->dma_dac2.ready = 0;
1684 spin_lock_irqsave(&s->lock, flags);
1685 if (val >= 2)
1686 s->sctrl |= SCTRL_P2SMB;
1687 else
1688 s->sctrl &= ~SCTRL_P2SMB;
1689 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1690 spin_unlock_irqrestore(&s->lock, flags);
1691 }
1692 }
1693 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
1694
1695 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1696 return put_user(AFMT_S16_LE|AFMT_U8, p);
1697
1698 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1699 if (get_user(val, p))
1700 return -EFAULT;
1701 if (val != AFMT_QUERY) {
1702 if (file->f_mode & FMODE_READ) {
1703 stop_adc(s);
1704 s->dma_adc.ready = 0;
1705 spin_lock_irqsave(&s->lock, flags);
1706 if (val == AFMT_S16_LE)
1707 s->sctrl |= SCTRL_R1SEB;
1708 else
1709 s->sctrl &= ~SCTRL_R1SEB;
1710 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1711 spin_unlock_irqrestore(&s->lock, flags);
1712 }
1713 if (file->f_mode & FMODE_WRITE) {
1714 stop_dac2(s);
1715 s->dma_dac2.ready = 0;
1716 spin_lock_irqsave(&s->lock, flags);
1717 if (val == AFMT_S16_LE)
1718 s->sctrl |= SCTRL_P2SEB;
1719 else
1720 s->sctrl &= ~SCTRL_P2SEB;
1721 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1722 spin_unlock_irqrestore(&s->lock, flags);
1723 }
1724 }
1725 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ?
1726 AFMT_S16_LE : AFMT_U8, p);
1727
1728 case SNDCTL_DSP_POST:
1729 return 0;
1730
1731 case SNDCTL_DSP_GETTRIGGER:
1732 val = 0;
1733 if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN)
1734 val |= PCM_ENABLE_INPUT;
1735 if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN)
1736 val |= PCM_ENABLE_OUTPUT;
1737 return put_user(val, p);
1738
1739 case SNDCTL_DSP_SETTRIGGER:
1740 if (get_user(val, p))
1741 return -EFAULT;
1742 if (file->f_mode & FMODE_READ) {
1743 if (val & PCM_ENABLE_INPUT) {
1744 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1745 return ret;
1746 s->dma_adc.enabled = 1;
1747 start_adc(s);
1748 } else {
1749 s->dma_adc.enabled = 0;
1750 stop_adc(s);
1751 }
1752 }
1753 if (file->f_mode & FMODE_WRITE) {
1754 if (val & PCM_ENABLE_OUTPUT) {
1755 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1756 return ret;
1757 s->dma_dac2.enabled = 1;
1758 start_dac2(s);
1759 } else {
1760 s->dma_dac2.enabled = 0;
1761 stop_dac2(s);
1762 }
1763 }
1764 return 0;
1765
1766 case SNDCTL_DSP_GETOSPACE:
1767 if (!(file->f_mode & FMODE_WRITE))
1768 return -EINVAL;
1769 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1770 return val;
1771 spin_lock_irqsave(&s->lock, flags);
1772 es1371_update_ptr(s);
1773 abinfo.fragsize = s->dma_dac2.fragsize;
1774 count = s->dma_dac2.count;
1775 if (count < 0)
1776 count = 0;
1777 abinfo.bytes = s->dma_dac2.dmasize - count;
1778 abinfo.fragstotal = s->dma_dac2.numfrag;
1779 abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift;
1780 spin_unlock_irqrestore(&s->lock, flags);
1781 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1782
1783 case SNDCTL_DSP_GETISPACE:
1784 if (!(file->f_mode & FMODE_READ))
1785 return -EINVAL;
1786 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1787 return val;
1788 spin_lock_irqsave(&s->lock, flags);
1789 es1371_update_ptr(s);
1790 abinfo.fragsize = s->dma_adc.fragsize;
1791 count = s->dma_adc.count;
1792 if (count < 0)
1793 count = 0;
1794 abinfo.bytes = count;
1795 abinfo.fragstotal = s->dma_adc.numfrag;
1796 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1797 spin_unlock_irqrestore(&s->lock, flags);
1798 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1799
1800 case SNDCTL_DSP_NONBLOCK:
1801 file->f_flags |= O_NONBLOCK;
1802 return 0;
1803
1804 case SNDCTL_DSP_GETODELAY:
1805 if (!(file->f_mode & FMODE_WRITE))
1806 return -EINVAL;
1807 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1808 return val;
1809 spin_lock_irqsave(&s->lock, flags);
1810 es1371_update_ptr(s);
1811 count = s->dma_dac2.count;
1812 spin_unlock_irqrestore(&s->lock, flags);
1813 if (count < 0)
1814 count = 0;
1815 return put_user(count, p);
1816
1817 case SNDCTL_DSP_GETIPTR:
1818 if (!(file->f_mode & FMODE_READ))
1819 return -EINVAL;
1820 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1821 return val;
1822 spin_lock_irqsave(&s->lock, flags);
1823 es1371_update_ptr(s);
1824 cinfo.bytes = s->dma_adc.total_bytes;
1825 count = s->dma_adc.count;
1826 if (count < 0)
1827 count = 0;
1828 cinfo.blocks = count >> s->dma_adc.fragshift;
1829 cinfo.ptr = s->dma_adc.hwptr;
1830 if (s->dma_adc.mapped)
1831 s->dma_adc.count &= s->dma_adc.fragsize-1;
1832 spin_unlock_irqrestore(&s->lock, flags);
1833 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1834 return -EFAULT;
1835 return 0;
1836
1837 case SNDCTL_DSP_GETOPTR:
1838 if (!(file->f_mode & FMODE_WRITE))
1839 return -EINVAL;
1840 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1841 return val;
1842 spin_lock_irqsave(&s->lock, flags);
1843 es1371_update_ptr(s);
1844 cinfo.bytes = s->dma_dac2.total_bytes;
1845 count = s->dma_dac2.count;
1846 if (count < 0)
1847 count = 0;
1848 cinfo.blocks = count >> s->dma_dac2.fragshift;
1849 cinfo.ptr = s->dma_dac2.hwptr;
1850 if (s->dma_dac2.mapped)
1851 s->dma_dac2.count &= s->dma_dac2.fragsize-1;
1852 spin_unlock_irqrestore(&s->lock, flags);
1853 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1854 return -EFAULT;
1855 return 0;
1856
1857 case SNDCTL_DSP_GETBLKSIZE:
1858 if (file->f_mode & FMODE_WRITE) {
1859 if ((val = prog_dmabuf_dac2(s)))
1860 return val;
1861 return put_user(s->dma_dac2.fragsize, p);
1862 }
1863 if ((val = prog_dmabuf_adc(s)))
1864 return val;
1865 return put_user(s->dma_adc.fragsize, p);
1866
1867 case SNDCTL_DSP_SETFRAGMENT:
1868 if (get_user(val, p))
1869 return -EFAULT;
1870 if (file->f_mode & FMODE_READ) {
1871 s->dma_adc.ossfragshift = val & 0xffff;
1872 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1873 if (s->dma_adc.ossfragshift < 4)
1874 s->dma_adc.ossfragshift = 4;
1875 if (s->dma_adc.ossfragshift > 15)
1876 s->dma_adc.ossfragshift = 15;
1877 if (s->dma_adc.ossmaxfrags < 4)
1878 s->dma_adc.ossmaxfrags = 4;
1879 }
1880 if (file->f_mode & FMODE_WRITE) {
1881 s->dma_dac2.ossfragshift = val & 0xffff;
1882 s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff;
1883 if (s->dma_dac2.ossfragshift < 4)
1884 s->dma_dac2.ossfragshift = 4;
1885 if (s->dma_dac2.ossfragshift > 15)
1886 s->dma_dac2.ossfragshift = 15;
1887 if (s->dma_dac2.ossmaxfrags < 4)
1888 s->dma_dac2.ossmaxfrags = 4;
1889 }
1890 return 0;
1891
1892 case SNDCTL_DSP_SUBDIVIDE:
1893 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1894 (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision))
1895 return -EINVAL;
1896 if (get_user(val, p))
1897 return -EFAULT;
1898 if (val != 1 && val != 2 && val != 4)
1899 return -EINVAL;
1900 if (file->f_mode & FMODE_READ)
1901 s->dma_adc.subdivision = val;
1902 if (file->f_mode & FMODE_WRITE)
1903 s->dma_dac2.subdivision = val;
1904 return 0;
1905
1906 case SOUND_PCM_READ_RATE:
1907 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
1908
1909 case SOUND_PCM_READ_CHANNELS:
1910 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
1911
1912 case SOUND_PCM_READ_BITS:
1913 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, p);
1914
1915 case SOUND_PCM_WRITE_FILTER:
1916 case SNDCTL_DSP_SETSYNCRO:
1917 case SOUND_PCM_READ_FILTER:
1918 return -EINVAL;
1919
1920 }
1921 return mixdev_ioctl(s->codec, cmd, arg);
1922 }
1923
1924 static int es1371_open(struct inode *inode, struct file *file)
1925 {
1926 int minor = iminor(inode);
1927 DECLARE_WAITQUEUE(wait, current);
1928 unsigned long flags;
1929 struct list_head *list;
1930 struct es1371_state *s;
1931
1932 for (list = devs.next; ; list = list->next) {
1933 if (list == &devs)
1934 return -ENODEV;
1935 s = list_entry(list, struct es1371_state, devs);
1936 if (!((s->dev_audio ^ minor) & ~0xf))
1937 break;
1938 }
1939 VALIDATE_STATE(s);
1940 file->private_data = s;
1941 /* wait for device to become free */
1942 mutex_lock(&s->open_mutex);
1943 while (s->open_mode & file->f_mode) {
1944 if (file->f_flags & O_NONBLOCK) {
1945 mutex_unlock(&s->open_mutex);
1946 return -EBUSY;
1947 }
1948 add_wait_queue(&s->open_wait, &wait);
1949 __set_current_state(TASK_INTERRUPTIBLE);
1950 mutex_unlock(&s->open_mutex);
1951 schedule();
1952 remove_wait_queue(&s->open_wait, &wait);
1953 set_current_state(TASK_RUNNING);
1954 if (signal_pending(current))
1955 return -ERESTARTSYS;
1956 mutex_lock(&s->open_mutex);
1957 }
1958 if (file->f_mode & FMODE_READ) {
1959 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1960 s->dma_adc.enabled = 1;
1961 set_adc_rate(s, 8000);
1962 }
1963 if (file->f_mode & FMODE_WRITE) {
1964 s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0;
1965 s->dma_dac2.enabled = 1;
1966 set_dac2_rate(s, 8000);
1967 }
1968 spin_lock_irqsave(&s->lock, flags);
1969 if (file->f_mode & FMODE_READ) {
1970 s->sctrl &= ~SCTRL_R1FMT;
1971 if ((minor & 0xf) == SND_DEV_DSP16)
1972 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT;
1973 else
1974 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT;
1975 }
1976 if (file->f_mode & FMODE_WRITE) {
1977 s->sctrl &= ~SCTRL_P2FMT;
1978 if ((minor & 0xf) == SND_DEV_DSP16)
1979 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT;
1980 else
1981 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT;
1982 }
1983 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1984 spin_unlock_irqrestore(&s->lock, flags);
1985 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1986 mutex_unlock(&s->open_mutex);
1987 mutex_init(&s->sem);
1988 return nonseekable_open(inode, file);
1989 }
1990
1991 static int es1371_release(struct inode *inode, struct file *file)
1992 {
1993 struct es1371_state *s = (struct es1371_state *)file->private_data;
1994
1995 VALIDATE_STATE(s);
1996 lock_kernel();
1997 if (file->f_mode & FMODE_WRITE)
1998 drain_dac2(s, file->f_flags & O_NONBLOCK);
1999 mutex_lock(&s->open_mutex);
2000 if (file->f_mode & FMODE_WRITE) {
2001 stop_dac2(s);
2002 dealloc_dmabuf(s, &s->dma_dac2);
2003 }
2004 if (file->f_mode & FMODE_READ) {
2005 stop_adc(s);
2006 dealloc_dmabuf(s, &s->dma_adc);
2007 }
2008 s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
2009 mutex_unlock(&s->open_mutex);
2010 wake_up(&s->open_wait);
2011 unlock_kernel();
2012 return 0;
2013 }
2014
2015 static /*const*/ struct file_operations es1371_audio_fops = {
2016 .owner = THIS_MODULE,
2017 .llseek = no_llseek,
2018 .read = es1371_read,
2019 .write = es1371_write,
2020 .poll = es1371_poll,
2021 .ioctl = es1371_ioctl,
2022 .mmap = es1371_mmap,
2023 .open = es1371_open,
2024 .release = es1371_release,
2025 };
2026
2027 /* --------------------------------------------------------------------- */
2028
2029 static ssize_t es1371_write_dac(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2030 {
2031 struct es1371_state *s = (struct es1371_state *)file->private_data;
2032 DECLARE_WAITQUEUE(wait, current);
2033 ssize_t ret = 0;
2034 unsigned long flags;
2035 unsigned swptr;
2036 int cnt;
2037
2038 VALIDATE_STATE(s);
2039 if (s->dma_dac1.mapped)
2040 return -ENXIO;
2041 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2042 return ret;
2043 if (!access_ok(VERIFY_READ, buffer, count))
2044 return -EFAULT;
2045 add_wait_queue(&s->dma_dac1.wait, &wait);
2046 while (count > 0) {
2047 spin_lock_irqsave(&s->lock, flags);
2048 if (s->dma_dac1.count < 0) {
2049 s->dma_dac1.count = 0;
2050 s->dma_dac1.swptr = s->dma_dac1.hwptr;
2051 }
2052 swptr = s->dma_dac1.swptr;
2053 cnt = s->dma_dac1.dmasize-swptr;
2054 if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize)
2055 cnt = s->dma_dac1.dmasize - s->dma_dac1.count;
2056 if (cnt <= 0)
2057 __set_current_state(TASK_INTERRUPTIBLE);
2058 spin_unlock_irqrestore(&s->lock, flags);
2059 if (cnt > count)
2060 cnt = count;
2061 if (cnt <= 0) {
2062 if (s->dma_dac1.enabled)
2063 start_dac1(s);
2064 if (file->f_flags & O_NONBLOCK) {
2065 if (!ret)
2066 ret = -EAGAIN;
2067 break;
2068 }
2069 schedule();
2070 if (signal_pending(current)) {
2071 if (!ret)
2072 ret = -ERESTARTSYS;
2073 break;
2074 }
2075 continue;
2076 }
2077 if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) {
2078 if (!ret)
2079 ret = -EFAULT;
2080 break;
2081 }
2082 swptr = (swptr + cnt) % s->dma_dac1.dmasize;
2083 spin_lock_irqsave(&s->lock, flags);
2084 s->dma_dac1.swptr = swptr;
2085 s->dma_dac1.count += cnt;
2086 s->dma_dac1.endcleared = 0;
2087 spin_unlock_irqrestore(&s->lock, flags);
2088 count -= cnt;
2089 buffer += cnt;
2090 ret += cnt;
2091 if (s->dma_dac1.enabled)
2092 start_dac1(s);
2093 }
2094 remove_wait_queue(&s->dma_dac1.wait, &wait);
2095 set_current_state(TASK_RUNNING);
2096 return ret;
2097 }
2098
2099 /* No kernel lock - we have our own spinlock */
2100 static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait)
2101 {
2102 struct es1371_state *s = (struct es1371_state *)file->private_data;
2103 unsigned long flags;
2104 unsigned int mask = 0;
2105
2106 VALIDATE_STATE(s);
2107 if (!s->dma_dac1.ready && prog_dmabuf_dac1(s))
2108 return 0;
2109 poll_wait(file, &s->dma_dac1.wait, wait);
2110 spin_lock_irqsave(&s->lock, flags);
2111 es1371_update_ptr(s);
2112 if (s->dma_dac1.mapped) {
2113 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
2114 mask |= POLLOUT | POLLWRNORM;
2115 } else {
2116 if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize)
2117 mask |= POLLOUT | POLLWRNORM;
2118 }
2119 spin_unlock_irqrestore(&s->lock, flags);
2120 return mask;
2121 }
2122
2123 static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma)
2124 {
2125 struct es1371_state *s = (struct es1371_state *)file->private_data;
2126 int ret;
2127 unsigned long size;
2128
2129 VALIDATE_STATE(s);
2130 if (!(vma->vm_flags & VM_WRITE))
2131 return -EINVAL;
2132 lock_kernel();
2133 if ((ret = prog_dmabuf_dac1(s)) != 0)
2134 goto out;
2135 ret = -EINVAL;
2136 if (vma->vm_pgoff != 0)
2137 goto out;
2138 size = vma->vm_end - vma->vm_start;
2139 if (size > (PAGE_SIZE << s->dma_dac1.buforder))
2140 goto out;
2141 ret = -EAGAIN;
2142 if (remap_pfn_range(vma, vma->vm_start,
2143 virt_to_phys(s->dma_dac1.rawbuf) >> PAGE_SHIFT,
2144 size, vma->vm_page_prot))
2145 goto out;
2146 s->dma_dac1.mapped = 1;
2147 ret = 0;
2148 out:
2149 unlock_kernel();
2150 return ret;
2151 }
2152
2153 static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2154 {
2155 struct es1371_state *s = (struct es1371_state *)file->private_data;
2156 unsigned long flags;
2157 audio_buf_info abinfo;
2158 count_info cinfo;
2159 int count;
2160 int val, ret;
2161 int __user *p = (int __user *)arg;
2162
2163 VALIDATE_STATE(s);
2164 switch (cmd) {
2165 case OSS_GETVERSION:
2166 return put_user(SOUND_VERSION, p);
2167
2168 case SNDCTL_DSP_SYNC:
2169 return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/);
2170
2171 case SNDCTL_DSP_SETDUPLEX:
2172 return -EINVAL;
2173
2174 case SNDCTL_DSP_GETCAPS:
2175 return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
2176
2177 case SNDCTL_DSP_RESET:
2178 stop_dac1(s);
2179 synchronize_irq(s->irq);
2180 s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0;
2181 return 0;
2182
2183 case SNDCTL_DSP_SPEED:
2184 if (get_user(val, p))
2185 return -EFAULT;
2186 if (val >= 0) {
2187 stop_dac1(s);
2188 s->dma_dac1.ready = 0;
2189 set_dac1_rate(s, val);
2190 }
2191 return put_user(s->dac1rate, p);
2192
2193 case SNDCTL_DSP_STEREO:
2194 if (get_user(val, p))
2195 return -EFAULT;
2196 stop_dac1(s);
2197 s->dma_dac1.ready = 0;
2198 spin_lock_irqsave(&s->lock, flags);
2199 if (val)
2200 s->sctrl |= SCTRL_P1SMB;
2201 else
2202 s->sctrl &= ~SCTRL_P1SMB;
2203 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2204 spin_unlock_irqrestore(&s->lock, flags);
2205 return 0;
2206
2207 case SNDCTL_DSP_CHANNELS:
2208 if (get_user(val, p))
2209 return -EFAULT;
2210 if (val != 0) {
2211 stop_dac1(s);
2212 s->dma_dac1.ready = 0;
2213 spin_lock_irqsave(&s->lock, flags);
2214 if (val >= 2)
2215 s->sctrl |= SCTRL_P1SMB;
2216 else
2217 s->sctrl &= ~SCTRL_P1SMB;
2218 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2219 spin_unlock_irqrestore(&s->lock, flags);
2220 }
2221 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
2222
2223 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2224 return put_user(AFMT_S16_LE|AFMT_U8, p);
2225
2226 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2227 if (get_user(val, p))
2228 return -EFAULT;
2229 if (val != AFMT_QUERY) {
2230 stop_dac1(s);
2231 s->dma_dac1.ready = 0;
2232 spin_lock_irqsave(&s->lock, flags);
2233 if (val == AFMT_S16_LE)
2234 s->sctrl |= SCTRL_P1SEB;
2235 else
2236 s->sctrl &= ~SCTRL_P1SEB;
2237 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2238 spin_unlock_irqrestore(&s->lock, flags);
2239 }
2240 return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, p);
2241
2242 case SNDCTL_DSP_POST:
2243 return 0;
2244
2245 case SNDCTL_DSP_GETTRIGGER:
2246 return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, p);
2247
2248 case SNDCTL_DSP_SETTRIGGER:
2249 if (get_user(val, p))
2250 return -EFAULT;
2251 if (val & PCM_ENABLE_OUTPUT) {
2252 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2253 return ret;
2254 s->dma_dac1.enabled = 1;
2255 start_dac1(s);
2256 } else {
2257 s->dma_dac1.enabled = 0;
2258 stop_dac1(s);
2259 }
2260 return 0;
2261
2262 case SNDCTL_DSP_GETOSPACE:
2263 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2264 return val;
2265 spin_lock_irqsave(&s->lock, flags);
2266 es1371_update_ptr(s);
2267 abinfo.fragsize = s->dma_dac1.fragsize;
2268 count = s->dma_dac1.count;
2269 if (count < 0)
2270 count = 0;
2271 abinfo.bytes = s->dma_dac1.dmasize - count;
2272 abinfo.fragstotal = s->dma_dac1.numfrag;
2273 abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift;
2274 spin_unlock_irqrestore(&s->lock, flags);
2275 return copy_to_user((void __user *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2276
2277 case SNDCTL_DSP_NONBLOCK:
2278 file->f_flags |= O_NONBLOCK;
2279 return 0;
2280
2281 case SNDCTL_DSP_GETODELAY:
2282 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2283 return val;
2284 spin_lock_irqsave(&s->lock, flags);
2285 es1371_update_ptr(s);
2286 count = s->dma_dac1.count;
2287 spin_unlock_irqrestore(&s->lock, flags);
2288 if (count < 0)
2289 count = 0;
2290 return put_user(count, p);
2291
2292 case SNDCTL_DSP_GETOPTR:
2293 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2294 return val;
2295 spin_lock_irqsave(&s->lock, flags);
2296 es1371_update_ptr(s);
2297 cinfo.bytes = s->dma_dac1.total_bytes;
2298 count = s->dma_dac1.count;
2299 if (count < 0)
2300 count = 0;
2301 cinfo.blocks = count >> s->dma_dac1.fragshift;
2302 cinfo.ptr = s->dma_dac1.hwptr;
2303 if (s->dma_dac1.mapped)
2304 s->dma_dac1.count &= s->dma_dac1.fragsize-1;
2305 spin_unlock_irqrestore(&s->lock, flags);
2306 if (copy_to_user((void __user *)arg, &cinfo, sizeof(cinfo)))
2307 return -EFAULT;
2308 return 0;
2309
2310 case SNDCTL_DSP_GETBLKSIZE:
2311 if ((val = prog_dmabuf_dac1(s)))
2312 return val;
2313 return put_user(s->dma_dac1.fragsize, p);
2314
2315 case SNDCTL_DSP_SETFRAGMENT:
2316 if (get_user(val, p))
2317 return -EFAULT;
2318 s->dma_dac1.ossfragshift = val & 0xffff;
2319 s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff;
2320 if (s->dma_dac1.ossfragshift < 4)
2321 s->dma_dac1.ossfragshift = 4;
2322 if (s->dma_dac1.ossfragshift > 15)
2323 s->dma_dac1.ossfragshift = 15;
2324 if (s->dma_dac1.ossmaxfrags < 4)
2325 s->dma_dac1.ossmaxfrags = 4;
2326 return 0;
2327
2328 case SNDCTL_DSP_SUBDIVIDE:
2329 if (s->dma_dac1.subdivision)
2330 return -EINVAL;
2331 if (get_user(val, p))
2332 return -EFAULT;
2333 if (val != 1 && val != 2 && val != 4)
2334 return -EINVAL;
2335 s->dma_dac1.subdivision = val;
2336 return 0;
2337
2338 case SOUND_PCM_READ_RATE:
2339 return put_user(s->dac1rate, p);
2340
2341 case SOUND_PCM_READ_CHANNELS:
2342 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
2343
2344 case SOUND_PCM_READ_BITS:
2345 return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, p);
2346
2347 case SOUND_PCM_WRITE_FILTER:
2348 case SNDCTL_DSP_SETSYNCRO:
2349 case SOUND_PCM_READ_FILTER:
2350 return -EINVAL;
2351
2352 }
2353 return mixdev_ioctl(s->codec, cmd, arg);
2354 }
2355
2356 static int es1371_open_dac(struct inode *inode, struct file *file)
2357 {
2358 int minor = iminor(inode);
2359 DECLARE_WAITQUEUE(wait, current);
2360 unsigned long flags;
2361 struct list_head *list;
2362 struct es1371_state *s;
2363
2364 for (list = devs.next; ; list = list->next) {
2365 if (list == &devs)
2366 return -ENODEV;
2367 s = list_entry(list, struct es1371_state, devs);
2368 if (!((s->dev_dac ^ minor) & ~0xf))
2369 break;
2370 }
2371 VALIDATE_STATE(s);
2372 /* we allow opening with O_RDWR, most programs do it although they will only write */
2373 #if 0
2374 if (file->f_mode & FMODE_READ)
2375 return -EPERM;
2376 #endif
2377 if (!(file->f_mode & FMODE_WRITE))
2378 return -EINVAL;
2379 file->private_data = s;
2380 /* wait for device to become free */
2381 mutex_lock(&s->open_mutex);
2382 while (s->open_mode & FMODE_DAC) {
2383 if (file->f_flags & O_NONBLOCK) {
2384 mutex_unlock(&s->open_mutex);
2385 return -EBUSY;
2386 }
2387 add_wait_queue(&s->open_wait, &wait);
2388 __set_current_state(TASK_INTERRUPTIBLE);
2389 mutex_unlock(&s->open_mutex);
2390 schedule();
2391 remove_wait_queue(&s->open_wait, &wait);
2392 set_current_state(TASK_RUNNING);
2393 if (signal_pending(current))
2394 return -ERESTARTSYS;
2395 mutex_lock(&s->open_mutex);
2396 }
2397 s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0;
2398 s->dma_dac1.enabled = 1;
2399 set_dac1_rate(s, 8000);
2400 spin_lock_irqsave(&s->lock, flags);
2401 s->sctrl &= ~SCTRL_P1FMT;
2402 if ((minor & 0xf) == SND_DEV_DSP16)
2403 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT;
2404 else
2405 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT;
2406 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2407 spin_unlock_irqrestore(&s->lock, flags);
2408 s->open_mode |= FMODE_DAC;
2409 mutex_unlock(&s->open_mutex);
2410 return nonseekable_open(inode, file);
2411 }
2412
2413 static int es1371_release_dac(struct inode *inode, struct file *file)
2414 {
2415 struct es1371_state *s = (struct es1371_state *)file->private_data;
2416
2417 VALIDATE_STATE(s);
2418 lock_kernel();
2419 drain_dac1(s, file->f_flags & O_NONBLOCK);
2420 mutex_lock(&s->open_mutex);
2421 stop_dac1(s);
2422 dealloc_dmabuf(s, &s->dma_dac1);
2423 s->open_mode &= ~FMODE_DAC;
2424 mutex_unlock(&s->open_mutex);
2425 wake_up(&s->open_wait);
2426 unlock_kernel();
2427 return 0;
2428 }
2429
2430 static /*const*/ struct file_operations es1371_dac_fops = {
2431 .owner = THIS_MODULE,
2432 .llseek = no_llseek,
2433 .write = es1371_write_dac,
2434 .poll = es1371_poll_dac,
2435 .ioctl = es1371_ioctl_dac,
2436 .mmap = es1371_mmap_dac,
2437 .open = es1371_open_dac,
2438 .release = es1371_release_dac,
2439 };
2440
2441 /* --------------------------------------------------------------------- */
2442
2443 static ssize_t es1371_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
2444 {
2445 struct es1371_state *s = (struct es1371_state *)file->private_data;
2446 DECLARE_WAITQUEUE(wait, current);
2447 ssize_t ret;
2448 unsigned long flags;
2449 unsigned ptr;
2450 int cnt;
2451
2452 VALIDATE_STATE(s);
2453 if (!access_ok(VERIFY_WRITE, buffer, count))
2454 return -EFAULT;
2455 if (count == 0)
2456 return 0;
2457 ret = 0;
2458 add_wait_queue(&s->midi.iwait, &wait);
2459 while (count > 0) {
2460 spin_lock_irqsave(&s->lock, flags);
2461 ptr = s->midi.ird;
2462 cnt = MIDIINBUF - ptr;
2463 if (s->midi.icnt < cnt)
2464 cnt = s->midi.icnt;
2465 if (cnt <= 0)
2466 __set_current_state(TASK_INTERRUPTIBLE);
2467 spin_unlock_irqrestore(&s->lock, flags);
2468 if (cnt > count)
2469 cnt = count;
2470 if (cnt <= 0) {
2471 if (file->f_flags & O_NONBLOCK) {
2472 if (!ret)
2473 ret = -EAGAIN;
2474 break;
2475 }
2476 schedule();
2477 if (signal_pending(current)) {
2478 if (!ret)
2479 ret = -ERESTARTSYS;
2480 break;
2481 }
2482 continue;
2483 }
2484 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2485 if (!ret)
2486 ret = -EFAULT;
2487 break;
2488 }
2489 ptr = (ptr + cnt) % MIDIINBUF;
2490 spin_lock_irqsave(&s->lock, flags);
2491 s->midi.ird = ptr;
2492 s->midi.icnt -= cnt;
2493 spin_unlock_irqrestore(&s->lock, flags);
2494 count -= cnt;
2495 buffer += cnt;
2496 ret += cnt;
2497 break;
2498 }
2499 __set_current_state(TASK_RUNNING);
2500 remove_wait_queue(&s->midi.iwait, &wait);
2501 return ret;
2502 }
2503
2504 static ssize_t es1371_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2505 {
2506 struct es1371_state *s = (struct es1371_state *)file->private_data;
2507 DECLARE_WAITQUEUE(wait, current);
2508 ssize_t ret;
2509 unsigned long flags;
2510 unsigned ptr;
2511 int cnt;
2512
2513 VALIDATE_STATE(s);
2514 if (!access_ok(VERIFY_READ, buffer, count))
2515 return -EFAULT;
2516 if (count == 0)
2517 return 0;
2518 ret = 0;
2519 add_wait_queue(&s->midi.owait, &wait);
2520 while (count > 0) {
2521 spin_lock_irqsave(&s->lock, flags);
2522 ptr = s->midi.owr;
2523 cnt = MIDIOUTBUF - ptr;
2524 if (s->midi.ocnt + cnt > MIDIOUTBUF)
2525 cnt = MIDIOUTBUF - s->midi.ocnt;
2526 if (cnt <= 0) {
2527 __set_current_state(TASK_INTERRUPTIBLE);
2528 es1371_handle_midi(s);
2529 }
2530 spin_unlock_irqrestore(&s->lock, flags);
2531 if (cnt > count)
2532 cnt = count;
2533 if (cnt <= 0) {
2534 if (file->f_flags & O_NONBLOCK) {
2535 if (!ret)
2536 ret = -EAGAIN;
2537 break;
2538 }
2539 schedule();
2540 if (signal_pending(current)) {
2541 if (!ret)
2542 ret = -ERESTARTSYS;
2543 break;
2544 }
2545 continue;
2546 }
2547 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2548 if (!ret)
2549 ret = -EFAULT;
2550 break;
2551 }
2552 ptr = (ptr + cnt) % MIDIOUTBUF;
2553 spin_lock_irqsave(&s->lock, flags);
2554 s->midi.owr = ptr;
2555 s->midi.ocnt += cnt;
2556 spin_unlock_irqrestore(&s->lock, flags);
2557 count -= cnt;
2558 buffer += cnt;
2559 ret += cnt;
2560 spin_lock_irqsave(&s->lock, flags);
2561 es1371_handle_midi(s);
2562 spin_unlock_irqrestore(&s->lock, flags);
2563 }
2564 __set_current_state(TASK_RUNNING);
2565 remove_wait_queue(&s->midi.owait, &wait);
2566 return ret;
2567 }
2568
2569 /* No kernel lock - we have our own spinlock */
2570 static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait)
2571 {
2572 struct es1371_state *s = (struct es1371_state *)file->private_data;
2573 unsigned long flags;
2574 unsigned int mask = 0;
2575
2576 VALIDATE_STATE(s);
2577 if (file->f_mode & FMODE_WRITE)
2578 poll_wait(file, &s->midi.owait, wait);
2579 if (file->f_mode & FMODE_READ)
2580 poll_wait(file, &s->midi.iwait, wait);
2581 spin_lock_irqsave(&s->lock, flags);
2582 if (file->f_mode & FMODE_READ) {
2583 if (s->midi.icnt > 0)
2584 mask |= POLLIN | POLLRDNORM;
2585 }
2586 if (file->f_mode & FMODE_WRITE) {
2587 if (s->midi.ocnt < MIDIOUTBUF)
2588 mask |= POLLOUT | POLLWRNORM;
2589 }
2590 spin_unlock_irqrestore(&s->lock, flags);
2591 return mask;
2592 }
2593
2594 static int es1371_midi_open(struct inode *inode, struct file *file)
2595 {
2596 int minor = iminor(inode);
2597 DECLARE_WAITQUEUE(wait, current);
2598 unsigned long flags;
2599 struct list_head *list;
2600 struct es1371_state *s;
2601
2602 for (list = devs.next; ; list = list->next) {
2603 if (list == &devs)
2604 return -ENODEV;
2605 s = list_entry(list, struct es1371_state, devs);
2606 if (s->dev_midi == minor)
2607 break;
2608 }
2609 VALIDATE_STATE(s);
2610 file->private_data = s;
2611 /* wait for device to become free */
2612 mutex_lock(&s->open_mutex);
2613 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2614 if (file->f_flags & O_NONBLOCK) {
2615 mutex_unlock(&s->open_mutex);
2616 return -EBUSY;
2617 }
2618 add_wait_queue(&s->open_wait, &wait);
2619 __set_current_state(TASK_INTERRUPTIBLE);
2620 mutex_unlock(&s->open_mutex);
2621 schedule();
2622 remove_wait_queue(&s->open_wait, &wait);
2623 set_current_state(TASK_RUNNING);
2624 if (signal_pending(current))
2625 return -ERESTARTSYS;
2626 mutex_lock(&s->open_mutex);
2627 }
2628 spin_lock_irqsave(&s->lock, flags);
2629 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2630 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2631 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2632 outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL);
2633 outb(0, s->io+ES1371_REG_UART_CONTROL);
2634 outb(0, s->io+ES1371_REG_UART_TEST);
2635 }
2636 if (file->f_mode & FMODE_READ) {
2637 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2638 }
2639 if (file->f_mode & FMODE_WRITE) {
2640 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2641 }
2642 s->ctrl |= CTRL_UART_EN;
2643 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2644 es1371_handle_midi(s);
2645 spin_unlock_irqrestore(&s->lock, flags);
2646 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
2647 mutex_unlock(&s->open_mutex);
2648 return nonseekable_open(inode, file);
2649 }
2650
2651 static int es1371_midi_release(struct inode *inode, struct file *file)
2652 {
2653 struct es1371_state *s = (struct es1371_state *)file->private_data;
2654 DECLARE_WAITQUEUE(wait, current);
2655 unsigned long flags;
2656 unsigned count, tmo;
2657
2658 VALIDATE_STATE(s);
2659 lock_kernel();
2660 if (file->f_mode & FMODE_WRITE) {
2661 add_wait_queue(&s->midi.owait, &wait);
2662 for (;;) {
2663 __set_current_state(TASK_INTERRUPTIBLE);
2664 spin_lock_irqsave(&s->lock, flags);
2665 count = s->midi.ocnt;
2666 spin_unlock_irqrestore(&s->lock, flags);
2667 if (count <= 0)
2668 break;
2669 if (signal_pending(current))
2670 break;
2671 if (file->f_flags & O_NONBLOCK)
2672 break;
2673 tmo = (count * HZ) / 3100;
2674 if (!schedule_timeout(tmo ? : 1) && tmo)
2675 printk(KERN_DEBUG PFX "midi timed out??\n");
2676 }
2677 remove_wait_queue(&s->midi.owait, &wait);
2678 set_current_state(TASK_RUNNING);
2679 }
2680 mutex_lock(&s->open_mutex);
2681 s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
2682 spin_lock_irqsave(&s->lock, flags);
2683 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2684 s->ctrl &= ~CTRL_UART_EN;
2685 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2686 }
2687 spin_unlock_irqrestore(&s->lock, flags);
2688 mutex_unlock(&s->open_mutex);
2689 wake_up(&s->open_wait);
2690 unlock_kernel();
2691 return 0;
2692 }
2693
2694 static /*const*/ struct file_operations es1371_midi_fops = {
2695 .owner = THIS_MODULE,
2696 .llseek = no_llseek,
2697 .read = es1371_midi_read,
2698 .write = es1371_midi_write,
2699 .poll = es1371_midi_poll,
2700 .open = es1371_midi_open,
2701 .release = es1371_midi_release,
2702 };
2703
2704 /* --------------------------------------------------------------------- */
2705
2706 /*
2707 * for debugging purposes, we'll create a proc device that dumps the
2708 * CODEC chipstate
2709 */
2710
2711 #ifdef ES1371_DEBUG
2712 static int proc_es1371_dump (char *buf, char **start, off_t fpos, int length, int *eof, void *data)
2713 {
2714 struct es1371_state *s;
2715 int cnt, len = 0;
2716
2717 if (list_empty(&devs))
2718 return 0;
2719 s = list_entry(devs.next, struct es1371_state, devs);
2720 /* print out header */
2721 len += sprintf(buf + len, "\t\tCreative ES137x Debug Dump-o-matic\n");
2722
2723 /* print out CODEC state */
2724 len += sprintf (buf + len, "AC97 CODEC state\n");
2725 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
2726 len+= sprintf (buf + len, "reg:0x%02x val:0x%04x\n", cnt, rdcodec(s->codec, cnt));
2727
2728 if (fpos >=len){
2729 *start = buf;
2730 *eof =1;
2731 return 0;
2732 }
2733 *start = buf + fpos;
2734 if ((len -= fpos) > length)
2735 return length;
2736 *eof =1;
2737 return len;
2738
2739 }
2740 #endif /* ES1371_DEBUG */
2741
2742 /* --------------------------------------------------------------------- */
2743
2744 /* maximum number of devices; only used for command line params */
2745 #define NR_DEVICE 5
2746
2747 static int spdif[NR_DEVICE];
2748 static int nomix[NR_DEVICE];
2749 static int amplifier[NR_DEVICE];
2750
2751 static unsigned int devindex;
2752
2753 module_param_array(spdif, bool, NULL, 0);
2754 MODULE_PARM_DESC(spdif, "if 1 the output is in S/PDIF digital mode");
2755 module_param_array(nomix, bool, NULL, 0);
2756 MODULE_PARM_DESC(nomix, "if 1 no analog audio is mixed to the digital output");
2757 module_param_array(amplifier, bool, NULL, 0);
2758 MODULE_PARM_DESC(amplifier, "Set to 1 if the machine needs the amp control enabling (many laptops)");
2759
2760 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2761 MODULE_DESCRIPTION("ES1371 AudioPCI97 Driver");
2762 MODULE_LICENSE("GPL");
2763
2764
2765 /* --------------------------------------------------------------------- */
2766
2767 static struct initvol {
2768 int mixch;
2769 int vol;
2770 } initvol[] __devinitdata = {
2771 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2772 { SOUND_MIXER_WRITE_CD, 0x4040 },
2773 { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 },
2774 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2775 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2776 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2777 { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 },
2778 { SOUND_MIXER_WRITE_OGAIN, 0x4040 },
2779 { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 },
2780 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2781 { SOUND_MIXER_WRITE_MIC, 0x4040 },
2782 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2783 { SOUND_MIXER_WRITE_IGAIN, 0x4040 }
2784 };
2785
2786 static struct
2787 {
2788 short svid, sdid;
2789 } amplifier_needed[] =
2790 {
2791 { 0x107B, 0x2150 }, /* Gateway Solo 2150 */
2792 { 0x13BD, 0x100C }, /* Mebius PC-MJ100V */
2793 { 0x1102, 0x5938 }, /* Targa Xtender 300 */
2794 { 0x1102, 0x8938 }, /* IPC notebook */
2795 { PCI_ANY_ID, PCI_ANY_ID }
2796 };
2797
2798 #ifdef SUPPORT_JOYSTICK
2799
2800 static int __devinit es1371_register_gameport(struct es1371_state *s)
2801 {
2802 struct gameport *gp;
2803 int gpio;
2804
2805 for (gpio = 0x218; gpio >= 0x200; gpio -= 0x08)
2806 if (request_region(gpio, JOY_EXTENT, "es1371"))
2807 break;
2808
2809 if (gpio < 0x200) {
2810 printk(KERN_ERR PFX "no free joystick address found\n");
2811 return -EBUSY;
2812 }
2813
2814 s->gameport = gp = gameport_allocate_port();
2815 if (!gp) {
2816 printk(KERN_ERR PFX "can not allocate memory for gameport\n");
2817 release_region(gpio, JOY_EXTENT);
2818 return -ENOMEM;
2819 }
2820
2821 gameport_set_name(gp, "ESS1371 Gameport");
2822 gameport_set_phys(gp, "isa%04x/gameport0", gpio);
2823 gp->dev.parent = &s->dev->dev;
2824 gp->io = gpio;
2825
2826 s->ctrl |= CTRL_JYSTK_EN | (((gpio >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT);
2827 outl(s->ctrl, s->io + ES1371_REG_CONTROL);
2828
2829 gameport_register_port(gp);
2830
2831 return 0;
2832 }
2833
2834 static inline void es1371_unregister_gameport(struct es1371_state *s)
2835 {
2836 if (s->gameport) {
2837 int gpio = s->gameport->io;
2838 gameport_unregister_port(s->gameport);
2839 release_region(gpio, JOY_EXTENT);
2840
2841 }
2842 }
2843
2844 #else
2845 static inline int es1371_register_gameport(struct es1371_state *s) { return -ENOSYS; }
2846 static inline void es1371_unregister_gameport(struct es1371_state *s) { }
2847 #endif /* SUPPORT_JOYSTICK */
2848
2849
2850 static int __devinit es1371_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2851 {
2852 struct es1371_state *s;
2853 mm_segment_t fs;
2854 int i, val, res = -1;
2855 int idx;
2856 unsigned long tmo;
2857 signed long tmo2;
2858 unsigned int cssr;
2859
2860 if ((res=pci_enable_device(pcidev)))
2861 return res;
2862
2863 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO))
2864 return -ENODEV;
2865 if (pcidev->irq == 0)
2866 return -ENODEV;
2867 i = pci_set_dma_mask(pcidev, DMA_32BIT_MASK);
2868 if (i) {
2869 printk(KERN_WARNING "es1371: architecture does not support 32bit PCI busmaster DMA\n");
2870 return i;
2871 }
2872 if (!(s = kmalloc(sizeof(struct es1371_state), GFP_KERNEL))) {
2873 printk(KERN_WARNING PFX "out of memory\n");
2874 return -ENOMEM;
2875 }
2876 memset(s, 0, sizeof(struct es1371_state));
2877
2878 s->codec = ac97_alloc_codec();
2879 if(s->codec == NULL)
2880 goto err_codec;
2881
2882 init_waitqueue_head(&s->dma_adc.wait);
2883 init_waitqueue_head(&s->dma_dac1.wait);
2884 init_waitqueue_head(&s->dma_dac2.wait);
2885 init_waitqueue_head(&s->open_wait);
2886 init_waitqueue_head(&s->midi.iwait);
2887 init_waitqueue_head(&s->midi.owait);
2888 mutex_init(&s->open_mutex);
2889 spin_lock_init(&s->lock);
2890 s->magic = ES1371_MAGIC;
2891 s->dev = pcidev;
2892 s->io = pci_resource_start(pcidev, 0);
2893 s->irq = pcidev->irq;
2894 s->vendor = pcidev->vendor;
2895 s->device = pcidev->device;
2896 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
2897 s->codec->private_data = s;
2898 s->codec->id = 0;
2899 s->codec->codec_read = rdcodec;
2900 s->codec->codec_write = wrcodec;
2901 printk(KERN_INFO PFX "found chip, vendor id 0x%04x device id 0x%04x revision 0x%02x\n",
2902 s->vendor, s->device, s->rev);
2903 if (!request_region(s->io, ES1371_EXTENT, "es1371")) {
2904 printk(KERN_ERR PFX "io ports %#lx-%#lx in use\n", s->io, s->io+ES1371_EXTENT-1);
2905 res = -EBUSY;
2906 goto err_region;
2907 }
2908 if ((res=request_irq(s->irq, es1371_interrupt, SA_SHIRQ, "es1371",s))) {
2909 printk(KERN_ERR PFX "irq %u in use\n", s->irq);
2910 goto err_irq;
2911 }
2912 printk(KERN_INFO PFX "found es1371 rev %d at io %#lx irq %u\n",
2913 s->rev, s->io, s->irq);
2914 /* register devices */
2915 if ((res=(s->dev_audio = register_sound_dsp(&es1371_audio_fops,-1)))<0)
2916 goto err_dev1;
2917 if ((res=(s->codec->dev_mixer = register_sound_mixer(&es1371_mixer_fops, -1))) < 0)
2918 goto err_dev2;
2919 if ((res=(s->dev_dac = register_sound_dsp(&es1371_dac_fops, -1))) < 0)
2920 goto err_dev3;
2921 if ((res=(s->dev_midi = register_sound_midi(&es1371_midi_fops, -1)))<0 )
2922 goto err_dev4;
2923 #ifdef ES1371_DEBUG
2924 /* initialize the debug proc device */
2925 s->ps = create_proc_read_entry("es1371",0,NULL,proc_es1371_dump,NULL);
2926 #endif /* ES1371_DEBUG */
2927
2928 /* initialize codec registers */
2929 s->ctrl = 0;
2930
2931 /* Check amplifier requirements */
2932
2933 if (amplifier[devindex])
2934 s->ctrl |= CTRL_GPIO_OUT0;
2935 else for(idx = 0; amplifier_needed[idx].svid != PCI_ANY_ID; idx++)
2936 {
2937 if(pcidev->subsystem_vendor == amplifier_needed[idx].svid &&
2938 pcidev->subsystem_device == amplifier_needed[idx].sdid)
2939 {
2940 s->ctrl |= CTRL_GPIO_OUT0; /* turn internal amplifier on */
2941 printk(KERN_INFO PFX "Enabling internal amplifier.\n");
2942 }
2943 }
2944
2945 s->sctrl = 0;
2946 cssr = 0;
2947 s->spdif_volume = -1;
2948 /* check to see if s/pdif mode is being requested */
2949 if (spdif[devindex]) {
2950 if (s->rev >= 4) {
2951 printk(KERN_INFO PFX "enabling S/PDIF output\n");
2952 s->spdif_volume = 0;
2953 cssr |= STAT_EN_SPDIF;
2954 s->ctrl |= CTRL_SPDIFEN_B;
2955 if (nomix[devindex]) /* don't mix analog inputs to s/pdif output */
2956 s->ctrl |= CTRL_RECEN_B;
2957 } else {
2958 printk(KERN_ERR PFX "revision %d does not support S/PDIF\n", s->rev);
2959 }
2960 }
2961 /* initialize the chips */
2962 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2963 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2964 outl(LEGACY_JFAST, s->io+ES1371_REG_LEGACY);
2965 pci_set_master(pcidev); /* enable bus mastering */
2966 /* if we are a 5880 turn on the AC97 */
2967 if (s->vendor == PCI_VENDOR_ID_ENSONIQ &&
2968 ((s->device == PCI_DEVICE_ID_ENSONIQ_CT5880 && s->rev >= CT5880REV_CT5880_C) ||
2969 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_CT5880_A) ||
2970 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_ES1373_8))) {
2971 cssr |= CSTAT_5880_AC97_RST;
2972 outl(cssr, s->io+ES1371_REG_STATUS);
2973 /* need to delay around 20ms(bleech) to give
2974 some CODECs enough time to wakeup */
2975 tmo = jiffies + (HZ / 50) + 1;
2976 for (;;) {
2977 tmo2 = tmo - jiffies;
2978 if (tmo2 <= 0)
2979 break;
2980 schedule_timeout(tmo2);
2981 }
2982 }
2983 /* AC97 warm reset to start the bitclk */
2984 outl(s->ctrl | CTRL_SYNCRES, s->io+ES1371_REG_CONTROL);
2985 udelay(2);
2986 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2987 /* init the sample rate converter */
2988 src_init(s);
2989 /* codec init */
2990 if (!ac97_probe_codec(s->codec)) {
2991 res = -ENODEV;
2992 goto err_gp;
2993 }
2994 /* set default values */
2995
2996 fs = get_fs();
2997 set_fs(KERNEL_DS);
2998 val = SOUND_MASK_LINE;
2999 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
3000 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
3001 val = initvol[i].vol;
3002 mixdev_ioctl(s->codec, initvol[i].mixch, (unsigned long)&val);
3003 }
3004 /* mute master and PCM when in S/PDIF mode */
3005 if (s->spdif_volume != -1) {
3006 val = 0x0000;
3007 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_VOLUME, (unsigned long)&val);
3008 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_PCM, (unsigned long)&val);
3009 }
3010 set_fs(fs);
3011 /* turn on S/PDIF output driver if requested */
3012 outl(cssr, s->io+ES1371_REG_STATUS);
3013
3014 es1371_register_gameport(s);
3015
3016 /* store it in the driver field */
3017 pci_set_drvdata(pcidev, s);
3018 /* put it into driver list */
3019 list_add_tail(&s->devs, &devs);
3020 /* increment devindex */
3021 if (devindex < NR_DEVICE-1)
3022 devindex++;
3023 return 0;
3024
3025 err_gp:
3026 #ifdef ES1371_DEBUG
3027 if (s->ps)
3028 remove_proc_entry("es1371", NULL);
3029 #endif
3030 unregister_sound_midi(s->dev_midi);
3031 err_dev4:
3032 unregister_sound_dsp(s->dev_dac);
3033 err_dev3:
3034 unregister_sound_mixer(s->codec->dev_mixer);
3035 err_dev2:
3036 unregister_sound_dsp(s->dev_audio);
3037 err_dev1:
3038 printk(KERN_ERR PFX "cannot register misc device\n");
3039 free_irq(s->irq, s);
3040 err_irq:
3041 release_region(s->io, ES1371_EXTENT);
3042 err_region:
3043 err_codec:
3044 ac97_release_codec(s->codec);
3045 kfree(s);
3046 return res;
3047 }
3048
3049 static void __devexit es1371_remove(struct pci_dev *dev)
3050 {
3051 struct es1371_state *s = pci_get_drvdata(dev);
3052
3053 if (!s)
3054 return;
3055 list_del(&s->devs);
3056 #ifdef ES1371_DEBUG
3057 if (s->ps)
3058 remove_proc_entry("es1371", NULL);
3059 #endif /* ES1371_DEBUG */
3060 outl(0, s->io+ES1371_REG_CONTROL); /* switch everything off */
3061 outl(0, s->io+ES1371_REG_SERIAL_CONTROL); /* clear serial interrupts */
3062 synchronize_irq(s->irq);
3063 free_irq(s->irq, s);
3064 es1371_unregister_gameport(s);
3065 release_region(s->io, ES1371_EXTENT);
3066 unregister_sound_dsp(s->dev_audio);
3067 unregister_sound_mixer(s->codec->dev_mixer);
3068 unregister_sound_dsp(s->dev_dac);
3069 unregister_sound_midi(s->dev_midi);
3070 ac97_release_codec(s->codec);
3071 kfree(s);
3072 pci_set_drvdata(dev, NULL);
3073 }
3074
3075 static struct pci_device_id id_table[] = {
3076 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3077 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3078 { PCI_VENDOR_ID_ECTIVA, PCI_DEVICE_ID_ECTIVA_EV1938, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3079 { 0, }
3080 };
3081
3082 MODULE_DEVICE_TABLE(pci, id_table);
3083
3084 static struct pci_driver es1371_driver = {
3085 .name = "es1371",
3086 .id_table = id_table,
3087 .probe = es1371_probe,
3088 .remove = __devexit_p(es1371_remove),
3089 };
3090
3091 static int __init init_es1371(void)
3092 {
3093 printk(KERN_INFO PFX "version v0.32 time " __TIME__ " " __DATE__ "\n");
3094 return pci_register_driver(&es1371_driver);
3095 }
3096
3097 static void __exit cleanup_es1371(void)
3098 {
3099 printk(KERN_INFO PFX "unloading\n");
3100 pci_unregister_driver(&es1371_driver);
3101 }
3102
3103 module_init(init_es1371);
3104 module_exit(cleanup_es1371);
3105
3106 /* --------------------------------------------------------------------- */
3107
3108 #ifndef MODULE
3109
3110 /* format is: es1371=[spdif,[nomix,[amplifier]]] */
3111
3112 static int __init es1371_setup(char *str)
3113 {
3114 static unsigned __initdata nr_dev = 0;
3115
3116 if (nr_dev >= NR_DEVICE)
3117 return 0;
3118
3119 (void)
3120 ((get_option(&str, &spdif[nr_dev]) == 2)
3121 && (get_option(&str, &nomix[nr_dev]) == 2)
3122 && (get_option(&str, &amplifier[nr_dev])));
3123
3124 nr_dev++;
3125 return 1;
3126 }
3127
3128 __setup("es1371=", es1371_setup);
3129
3130 #endif /* MODULE */
Support for the Chinese Samsung S3C2440 based development boards