2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn.helgaas@hp.com>
9 * Copyright (C) 2004 Silicon Graphics, Inc.
11 * Note: Above list of copyright holders is incomplete...
13 #include <linux/config.h>
15 #include <linux/acpi.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/smp_lock.h>
23 #include <linux/spinlock.h>
25 #include <asm/machvec.h>
27 #include <asm/segment.h>
28 #include <asm/system.h>
33 #include <asm/hw_irq.h>
37 * Low-level SAL-based PCI configuration access functions. Note that SAL
38 * calls are already serialized (via sal_lock), so we don't need another
39 * synchronization mechanism here.
42 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
43 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
45 /* SAL 3.2 adds support for extended config space. */
47 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
48 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
51 pci_sal_read (unsigned int seg
, unsigned int bus
, unsigned int devfn
,
52 int reg
, int len
, u32
*value
)
57 if (!value
|| (seg
> 65535) || (bus
> 255) || (devfn
> 255) || (reg
> 4095))
60 if ((seg
| reg
) <= 255) {
61 addr
= PCI_SAL_ADDRESS(seg
, bus
, devfn
, reg
);
64 addr
= PCI_SAL_EXT_ADDRESS(seg
, bus
, devfn
, reg
);
67 result
= ia64_sal_pci_config_read(addr
, mode
, len
, &data
);
76 pci_sal_write (unsigned int seg
, unsigned int bus
, unsigned int devfn
,
77 int reg
, int len
, u32 value
)
82 if ((seg
> 65535) || (bus
> 255) || (devfn
> 255) || (reg
> 4095))
85 if ((seg
| reg
) <= 255) {
86 addr
= PCI_SAL_ADDRESS(seg
, bus
, devfn
, reg
);
89 addr
= PCI_SAL_EXT_ADDRESS(seg
, bus
, devfn
, reg
);
92 result
= ia64_sal_pci_config_write(addr
, mode
, len
, value
);
98 static struct pci_raw_ops pci_sal_ops
= {
100 .write
= pci_sal_write
103 struct pci_raw_ops
*raw_pci_ops
= &pci_sal_ops
;
106 pci_read (struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*value
)
108 return raw_pci_ops
->read(pci_domain_nr(bus
), bus
->number
,
109 devfn
, where
, size
, value
);
113 pci_write (struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 value
)
115 return raw_pci_ops
->write(pci_domain_nr(bus
), bus
->number
,
116 devfn
, where
, size
, value
);
119 struct pci_ops pci_root_ops
= {
125 extern acpi_status
acpi_map_iosapic(acpi_handle
, u32
, void *, void **);
126 static void acpi_map_iosapics(void)
128 acpi_get_devices(NULL
, acpi_map_iosapic
, NULL
, NULL
);
131 static void acpi_map_iosapics(void)
135 #endif /* CONFIG_NUMA */
145 subsys_initcall(pci_acpi_init
);
147 /* Called by ACPI when it finds a new root bus. */
149 static struct pci_controller
* __devinit
150 alloc_pci_controller (int seg
)
152 struct pci_controller
*controller
;
154 controller
= kmalloc(sizeof(*controller
), GFP_KERNEL
);
158 memset(controller
, 0, sizeof(*controller
));
159 controller
->segment
= seg
;
164 add_io_space (struct acpi_resource_address64
*addr
)
170 if (addr
->address_translation_offset
== 0)
171 return IO_SPACE_BASE(0); /* part of legacy IO space */
173 if (addr
->attribute
.io
.translation_attribute
== ACPI_SPARSE_TRANSLATION
)
176 offset
= (u64
) ioremap(addr
->address_translation_offset
, 0);
177 for (i
= 0; i
< num_io_spaces
; i
++)
178 if (io_space
[i
].mmio_base
== offset
&&
179 io_space
[i
].sparse
== sparse
)
180 return IO_SPACE_BASE(i
);
182 if (num_io_spaces
== MAX_IO_SPACES
) {
183 printk("Too many IO port spaces\n");
188 io_space
[i
].mmio_base
= offset
;
189 io_space
[i
].sparse
= sparse
;
191 return IO_SPACE_BASE(i
);
194 static acpi_status __devinit
195 count_window (struct acpi_resource
*resource
, void *data
)
197 unsigned int *windows
= (unsigned int *) data
;
198 struct acpi_resource_address64 addr
;
201 status
= acpi_resource_to_address64(resource
, &addr
);
202 if (ACPI_SUCCESS(status
))
203 if (addr
.resource_type
== ACPI_MEMORY_RANGE
||
204 addr
.resource_type
== ACPI_IO_RANGE
)
210 struct pci_root_info
{
211 struct pci_controller
*controller
;
215 static __devinit acpi_status
add_window(struct acpi_resource
*res
, void *data
)
217 struct pci_root_info
*info
= data
;
218 struct pci_window
*window
;
219 struct acpi_resource_address64 addr
;
221 unsigned long flags
, offset
= 0;
222 struct resource
*root
;
224 status
= acpi_resource_to_address64(res
, &addr
);
225 if (!ACPI_SUCCESS(status
))
228 if (!addr
.address_length
)
231 if (addr
.resource_type
== ACPI_MEMORY_RANGE
) {
232 flags
= IORESOURCE_MEM
;
233 root
= &iomem_resource
;
234 offset
= addr
.address_translation_offset
;
235 } else if (addr
.resource_type
== ACPI_IO_RANGE
) {
236 flags
= IORESOURCE_IO
;
237 root
= &ioport_resource
;
238 offset
= add_io_space(&addr
);
244 window
= &info
->controller
->window
[info
->controller
->windows
++];
245 window
->resource
.name
= info
->name
;
246 window
->resource
.flags
= flags
;
247 window
->resource
.start
= addr
.min_address_range
+ offset
;
248 window
->resource
.end
= addr
.max_address_range
+ offset
;
249 window
->resource
.child
= NULL
;
250 window
->offset
= offset
;
252 if (insert_resource(root
, &window
->resource
)) {
253 printk(KERN_ERR
"alloc 0x%lx-0x%lx from %s for %s failed\n",
254 window
->resource
.start
, window
->resource
.end
,
255 root
->name
, info
->name
);
261 static void __devinit
262 pcibios_setup_root_windows(struct pci_bus
*bus
, struct pci_controller
*ctrl
)
267 for (i
= 0; i
< ctrl
->windows
; i
++) {
268 struct resource
*res
= &ctrl
->window
[i
].resource
;
269 /* HP's firmware has a hack to work around a Windows bug.
270 * Ignore these tiny memory ranges */
271 if ((res
->flags
& IORESOURCE_MEM
) &&
272 (res
->end
- res
->start
< 16))
274 if (j
>= PCI_BUS_NUM_RESOURCES
) {
275 printk("Ignoring range [%lx-%lx] (%lx)\n", res
->start
,
276 res
->end
, res
->flags
);
279 bus
->resource
[j
++] = res
;
283 struct pci_bus
* __devinit
284 pci_acpi_scan_root(struct acpi_device
*device
, int domain
, int bus
)
286 struct pci_root_info info
;
287 struct pci_controller
*controller
;
288 unsigned int windows
= 0;
289 struct pci_bus
*pbus
;
292 controller
= alloc_pci_controller(domain
);
296 controller
->acpi_handle
= device
->handle
;
298 acpi_walk_resources(device
->handle
, METHOD_NAME__CRS
, count_window
,
300 controller
->window
= kmalloc(sizeof(*controller
->window
) * windows
,
302 if (!controller
->window
)
305 name
= kmalloc(16, GFP_KERNEL
);
309 sprintf(name
, "PCI Bus %04x:%02x", domain
, bus
);
310 info
.controller
= controller
;
312 acpi_walk_resources(device
->handle
, METHOD_NAME__CRS
, add_window
,
315 pbus
= pci_scan_bus(bus
, &pci_root_ops
, controller
);
317 pcibios_setup_root_windows(pbus
, controller
);
322 kfree(controller
->window
);
329 void pcibios_resource_to_bus(struct pci_dev
*dev
,
330 struct pci_bus_region
*region
, struct resource
*res
)
332 struct pci_controller
*controller
= PCI_CONTROLLER(dev
);
333 unsigned long offset
= 0;
336 for (i
= 0; i
< controller
->windows
; i
++) {
337 struct pci_window
*window
= &controller
->window
[i
];
338 if (!(window
->resource
.flags
& res
->flags
))
340 if (window
->resource
.start
> res
->start
)
342 if (window
->resource
.end
< res
->end
)
344 offset
= window
->offset
;
348 region
->start
= res
->start
- offset
;
349 region
->end
= res
->end
- offset
;
351 EXPORT_SYMBOL(pcibios_resource_to_bus
);
353 void pcibios_bus_to_resource(struct pci_dev
*dev
,
354 struct resource
*res
, struct pci_bus_region
*region
)
356 struct pci_controller
*controller
= PCI_CONTROLLER(dev
);
357 unsigned long offset
= 0;
360 for (i
= 0; i
< controller
->windows
; i
++) {
361 struct pci_window
*window
= &controller
->window
[i
];
362 if (!(window
->resource
.flags
& res
->flags
))
364 if (window
->resource
.start
- window
->offset
> region
->start
)
366 if (window
->resource
.end
- window
->offset
< region
->end
)
368 offset
= window
->offset
;
372 res
->start
= region
->start
+ offset
;
373 res
->end
= region
->end
+ offset
;
376 static void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
)
378 struct pci_bus_region region
;
380 int limit
= (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) ? \
381 PCI_BRIDGE_RESOURCES
: PCI_NUM_RESOURCES
;
383 for (i
= 0; i
< limit
; i
++) {
384 if (!dev
->resource
[i
].flags
)
386 region
.start
= dev
->resource
[i
].start
;
387 region
.end
= dev
->resource
[i
].end
;
388 pcibios_bus_to_resource(dev
, &dev
->resource
[i
], ®ion
);
389 pci_claim_resource(dev
, i
);
394 * Called after each bus is probed, but before its children are examined.
397 pcibios_fixup_bus (struct pci_bus
*b
)
401 list_for_each_entry(dev
, &b
->devices
, bus_list
)
402 pcibios_fixup_device_resources(dev
);
408 pcibios_update_irq (struct pci_dev
*dev
, int irq
)
410 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
412 /* ??? FIXME -- record old value for shutdown. */
416 pcibios_enable_resources (struct pci_dev
*dev
, int mask
)
425 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
427 for (idx
=0; idx
<6; idx
++) {
428 /* Only set up the desired resources. */
429 if (!(mask
& (1 << idx
)))
432 r
= &dev
->resource
[idx
];
433 if (!r
->start
&& r
->end
) {
435 "PCI: Device %s not available because of resource collisions\n",
439 if (r
->flags
& IORESOURCE_IO
)
440 cmd
|= PCI_COMMAND_IO
;
441 if (r
->flags
& IORESOURCE_MEM
)
442 cmd
|= PCI_COMMAND_MEMORY
;
444 if (dev
->resource
[PCI_ROM_RESOURCE
].start
)
445 cmd
|= PCI_COMMAND_MEMORY
;
446 if (cmd
!= old_cmd
) {
447 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev
), old_cmd
, cmd
);
448 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
454 pcibios_enable_device (struct pci_dev
*dev
, int mask
)
458 ret
= pcibios_enable_resources(dev
, mask
);
462 return acpi_pci_irq_enable(dev
);
465 #ifdef CONFIG_ACPI_DEALLOCATE_IRQ
467 pcibios_disable_device (struct pci_dev
*dev
)
469 acpi_pci_irq_disable(dev
);
471 #endif /* CONFIG_ACPI_DEALLOCATE_IRQ */
474 pcibios_align_resource (void *data
, struct resource
*res
,
475 unsigned long size
, unsigned long align
)
480 * PCI BIOS setup, always defaults to SAL interface
483 pcibios_setup (char *str
)
489 pci_mmap_page_range (struct pci_dev
*dev
, struct vm_area_struct
*vma
,
490 enum pci_mmap_state mmap_state
, int write_combine
)
493 * I/O space cannot be accessed via normal processor loads and
494 * stores on this platform.
496 if (mmap_state
== pci_mmap_io
)
498 * XXX we could relax this for I/O spaces for which ACPI
499 * indicates that the space is 1-to-1 mapped. But at the
500 * moment, we don't support multiple PCI address spaces and
501 * the legacy I/O space is not 1-to-1 mapped, so this is moot.
506 * Leave vm_pgoff as-is, the PCI space address is the physical
507 * address on this platform.
509 vma
->vm_flags
|= (VM_SHM
| VM_RESERVED
| VM_IO
);
511 if (write_combine
&& efi_range_is_wc(vma
->vm_start
,
512 vma
->vm_end
- vma
->vm_start
))
513 vma
->vm_page_prot
= pgprot_writecombine(vma
->vm_page_prot
);
515 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
517 if (remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
518 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
))
525 * ia64_pci_get_legacy_mem - generic legacy mem routine
526 * @bus: bus to get legacy memory base address for
528 * Find the base of legacy memory for @bus. This is typically the first
529 * megabyte of bus address space for @bus or is simply 0 on platforms whose
530 * chipsets support legacy I/O and memory routing. Returns the base address
531 * or an error pointer if an error occurred.
533 * This is the ia64 generic version of this routine. Other platforms
534 * are free to override it with a machine vector.
536 char *ia64_pci_get_legacy_mem(struct pci_bus
*bus
)
538 return (char *)__IA64_UNCACHED_OFFSET
;
542 * pci_mmap_legacy_page_range - map legacy memory space to userland
543 * @bus: bus whose legacy space we're mapping
544 * @vma: vma passed in by mmap
546 * Map legacy memory space for this device back to userspace using a machine
547 * vector to get the base address.
550 pci_mmap_legacy_page_range(struct pci_bus
*bus
, struct vm_area_struct
*vma
)
554 addr
= pci_get_legacy_mem(bus
);
556 return PTR_ERR(addr
);
558 vma
->vm_pgoff
+= (unsigned long)addr
>> PAGE_SHIFT
;
559 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
560 vma
->vm_flags
|= (VM_SHM
| VM_RESERVED
| VM_IO
);
562 if (remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
563 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
))
570 * ia64_pci_legacy_read - read from legacy I/O space
572 * @port: legacy port value
573 * @val: caller allocated storage for returned value
574 * @size: number of bytes to read
576 * Simply reads @size bytes from @port and puts the result in @val.
578 * Again, this (and the write routine) are generic versions that can be
579 * overridden by the platform. This is necessary on platforms that don't
580 * support legacy I/O routing or that hard fail on legacy I/O timeouts.
582 int ia64_pci_legacy_read(struct pci_bus
*bus
, u16 port
, u32
*val
, u8 size
)
605 * ia64_pci_legacy_write - perform a legacy I/O write
607 * @port: port to write
608 * @val: value to write
609 * @size: number of bytes to write from @val
611 * Simply writes @size bytes of @val to @port.
613 int ia64_pci_legacy_write(struct pci_dev
*bus
, u16 port
, u32 val
, u8 size
)
636 * pci_cacheline_size - determine cacheline size for PCI devices
639 * We want to use the line-size of the outer-most cache. We assume
640 * that this line-size is the same for all CPUs.
642 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
644 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
647 pci_cacheline_size (void)
649 u64 levels
, unique_caches
;
651 pal_cache_config_info_t cci
;
652 static u8 cacheline_size
;
655 return cacheline_size
;
657 status
= ia64_pal_cache_summary(&levels
, &unique_caches
);
659 printk(KERN_ERR
"%s: ia64_pal_cache_summary() failed (status=%ld)\n",
660 __FUNCTION__
, status
);
661 return SMP_CACHE_BYTES
;
664 status
= ia64_pal_cache_config_info(levels
- 1, /* cache_type (data_or_unified)= */ 2,
667 printk(KERN_ERR
"%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
668 __FUNCTION__
, status
);
669 return SMP_CACHE_BYTES
;
671 cacheline_size
= 1 << cci
.pcci_line_size
;
672 return cacheline_size
;
676 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
677 * @dev: the PCI device for which MWI is enabled
679 * For ia64, we can get the cacheline sizes from PAL.
681 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
684 pcibios_prep_mwi (struct pci_dev
*dev
)
686 unsigned long desired_linesize
, current_linesize
;
690 desired_linesize
= pci_cacheline_size();
692 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &pci_linesize
);
693 current_linesize
= 4 * pci_linesize
;
694 if (desired_linesize
!= current_linesize
) {
695 printk(KERN_WARNING
"PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
696 pci_name(dev
), current_linesize
);
697 if (current_linesize
> desired_linesize
) {
698 printk(" expected %lu bytes instead\n", desired_linesize
);
701 printk(" correcting to %lu\n", desired_linesize
);
702 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, desired_linesize
/ 4);
708 int pci_vector_resources(int last
, int nr_released
)
710 int count
= nr_released
;
712 count
+= (IA64_LAST_DEVICE_VECTOR
- last
);