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drivers/net/wan: fix sparse warning: make symbol static
[linux-2.6/mini2440.git] / drivers / net / smc91x.h
blob3e7c6a3cbc650c8f0a39afa4bc49eb48f7aac191
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37 #include <linux/smc91x.h>
38
39 /*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE) ||\
45 defined(CONFIG_MACH_ZYLONITE) ||\
46 defined(CONFIG_MACH_LITTLETON) ||\
47 defined(CONFIG_ARCH_VIPER)
48
49 #include <asm/mach-types.h>
50
51 /* Now the bus width is specified in the platform data
52 * pretend here to support all I/O access types
53 */
54 #define SMC_CAN_USE_8BIT 1
55 #define SMC_CAN_USE_16BIT 1
56 #define SMC_CAN_USE_32BIT 1
57 #define SMC_NOWAIT 1
58
59 #define SMC_IO_SHIFT (lp->io_shift)
60
61 #define SMC_inb(a, r) readb((a) + (r))
62 #define SMC_inw(a, r) readw((a) + (r))
63 #define SMC_inl(a, r) readl((a) + (r))
64 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
65 #define SMC_outl(v, a, r) writel(v, (a) + (r))
66 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
67 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
68 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
69 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
70 #define SMC_IRQ_FLAGS (-1) /* from resource */
71
72 /* We actually can't write halfwords properly if not word aligned */
73 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
74 {
75 if (machine_is_mainstone() && reg & 2) {
76 unsigned int v = val << 16;
77 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
78 writel(v, ioaddr + (reg & ~2));
79 } else {
80 writew(val, ioaddr + reg);
81 }
82 }
83
84 #elif defined(CONFIG_BLACKFIN)
85
86 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
87 #define RPC_LSA_DEFAULT RPC_LED_100_10
88 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
89
90 #define SMC_CAN_USE_8BIT 0
91 #define SMC_CAN_USE_16BIT 1
92 # if defined(CONFIG_BF561)
93 #define SMC_CAN_USE_32BIT 1
94 # else
95 #define SMC_CAN_USE_32BIT 0
96 # endif
97 #define SMC_IO_SHIFT 0
98 #define SMC_NOWAIT 1
99 #define SMC_USE_BFIN_DMA 0
100
101 #define SMC_inw(a, r) readw((a) + (r))
102 #define SMC_outw(v, a, r) writew(v, (a) + (r))
103 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
104 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
105 # if SMC_CAN_USE_32BIT
106 #define SMC_inl(a, r) readl((a) + (r))
107 #define SMC_outl(v, a, r) writel(v, (a) + (r))
108 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
109 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
110 # endif
111
112 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
113
114 /* We can only do 16-bit reads and writes in the static memory space. */
115 #define SMC_CAN_USE_8BIT 0
116 #define SMC_CAN_USE_16BIT 1
117 #define SMC_CAN_USE_32BIT 0
118 #define SMC_NOWAIT 1
119
120 #define SMC_IO_SHIFT 0
121
122 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
123 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
124 #define SMC_insw(a, r, p, l) \
125 do { \
126 unsigned long __port = (a) + (r); \
127 u16 *__p = (u16 *)(p); \
128 int __l = (l); \
129 insw(__port, __p, __l); \
130 while (__l > 0) { \
131 *__p = swab16(*__p); \
132 __p++; \
133 __l--; \
134 } \
135 } while (0)
136 #define SMC_outsw(a, r, p, l) \
137 do { \
138 unsigned long __port = (a) + (r); \
139 u16 *__p = (u16 *)(p); \
140 int __l = (l); \
141 while (__l > 0) { \
142 /* Believe it or not, the swab isn't needed. */ \
143 outw( /* swab16 */ (*__p++), __port); \
144 __l--; \
145 } \
146 } while (0)
147 #define SMC_IRQ_FLAGS (0)
148
149 #elif defined(CONFIG_SA1100_PLEB)
150 /* We can only do 16-bit reads and writes in the static memory space. */
151 #define SMC_CAN_USE_8BIT 1
152 #define SMC_CAN_USE_16BIT 1
153 #define SMC_CAN_USE_32BIT 0
154 #define SMC_IO_SHIFT 0
155 #define SMC_NOWAIT 1
156
157 #define SMC_inb(a, r) readb((a) + (r))
158 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
159 #define SMC_inw(a, r) readw((a) + (r))
160 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
161 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
162 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
163 #define SMC_outw(v, a, r) writew(v, (a) + (r))
164 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
165
166 #define SMC_IRQ_FLAGS (-1)
167
168 #elif defined(CONFIG_SA1100_ASSABET)
169
170 #include <mach/neponset.h>
171
172 /* We can only do 8-bit reads and writes in the static memory space. */
173 #define SMC_CAN_USE_8BIT 1
174 #define SMC_CAN_USE_16BIT 0
175 #define SMC_CAN_USE_32BIT 0
176 #define SMC_NOWAIT 1
177
178 /* The first two address lines aren't connected... */
179 #define SMC_IO_SHIFT 2
180
181 #define SMC_inb(a, r) readb((a) + (r))
182 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
183 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
184 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
185 #define SMC_IRQ_FLAGS (-1) /* from resource */
186
187 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
188
189 #define SMC_CAN_USE_8BIT 0
190 #define SMC_CAN_USE_16BIT 1
191 #define SMC_CAN_USE_32BIT 0
192 #define SMC_IO_SHIFT 0
193 #define SMC_NOWAIT 1
194
195 #define SMC_inw(a, r) readw((a) + (r))
196 #define SMC_outw(v, a, r) writew(v, (a) + (r))
197 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
198 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
199
200 #elif defined(CONFIG_ARCH_INNOKOM) || \
201 defined(CONFIG_ARCH_PXA_IDP) || \
202 defined(CONFIG_ARCH_RAMSES) || \
203 defined(CONFIG_ARCH_PCM027)
204
205 #define SMC_CAN_USE_8BIT 1
206 #define SMC_CAN_USE_16BIT 1
207 #define SMC_CAN_USE_32BIT 1
208 #define SMC_IO_SHIFT 0
209 #define SMC_NOWAIT 1
210 #define SMC_USE_PXA_DMA 1
211
212 #define SMC_inb(a, r) readb((a) + (r))
213 #define SMC_inw(a, r) readw((a) + (r))
214 #define SMC_inl(a, r) readl((a) + (r))
215 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
216 #define SMC_outl(v, a, r) writel(v, (a) + (r))
217 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
218 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
219 #define SMC_IRQ_FLAGS (-1) /* from resource */
220
221 /* We actually can't write halfwords properly if not word aligned */
222 static inline void
223 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
224 {
225 if (reg & 2) {
226 unsigned int v = val << 16;
227 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
228 writel(v, ioaddr + (reg & ~2));
229 } else {
230 writew(val, ioaddr + reg);
231 }
232 }
233
234 #elif defined(CONFIG_ARCH_OMAP)
235
236 /* We can only do 16-bit reads and writes in the static memory space. */
237 #define SMC_CAN_USE_8BIT 0
238 #define SMC_CAN_USE_16BIT 1
239 #define SMC_CAN_USE_32BIT 0
240 #define SMC_IO_SHIFT 0
241 #define SMC_NOWAIT 1
242
243 #define SMC_inw(a, r) readw((a) + (r))
244 #define SMC_outw(v, a, r) writew(v, (a) + (r))
245 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
246 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
247 #define SMC_IRQ_FLAGS (-1) /* from resource */
248
249 #elif defined(CONFIG_SH_SH4202_MICRODEV)
250
251 #define SMC_CAN_USE_8BIT 0
252 #define SMC_CAN_USE_16BIT 1
253 #define SMC_CAN_USE_32BIT 0
254
255 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
256 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
257 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
258 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
259 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
260 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
261 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
262 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
263 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
264 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
265
266 #define SMC_IRQ_FLAGS (0)
267
268 #elif defined(CONFIG_M32R)
269
270 #define SMC_CAN_USE_8BIT 0
271 #define SMC_CAN_USE_16BIT 1
272 #define SMC_CAN_USE_32BIT 0
273
274 #define SMC_inb(a, r) inb(((u32)a) + (r))
275 #define SMC_inw(a, r) inw(((u32)a) + (r))
276 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
277 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
278 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
279 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
280
281 #define SMC_IRQ_FLAGS (0)
282
283 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
284 #define RPC_LSB_DEFAULT RPC_LED_100_10
285
286 #elif defined(CONFIG_MACH_LPD79520) \
287 || defined(CONFIG_MACH_LPD7A400) \
288 || defined(CONFIG_MACH_LPD7A404)
289
290 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
291 * way that the CPU handles chip selects and the way that the SMC chip
292 * expects the chip select to operate. Refer to
293 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
294 * IOBARRIER is a byte, in order that we read the least-common
295 * denominator. It would be wasteful to read 32 bits from an 8-bit
296 * accessible region.
297 *
298 * There is no explicit protection against interrupts intervening
299 * between the writew and the IOBARRIER. In SMC ISR there is a
300 * preamble that performs an IOBARRIER in the extremely unlikely event
301 * that the driver interrupts itself between a writew to the chip an
302 * the IOBARRIER that follows *and* the cache is large enough that the
303 * first off-chip access while handing the interrupt is to the SMC
304 * chip. Other devices in the same address space as the SMC chip must
305 * be aware of the potential for trouble and perform a similar
306 * IOBARRIER on entry to their ISR.
307 */
308
309 #include <mach/constants.h> /* IOBARRIER_VIRT */
310
311 #define SMC_CAN_USE_8BIT 0
312 #define SMC_CAN_USE_16BIT 1
313 #define SMC_CAN_USE_32BIT 0
314 #define SMC_NOWAIT 0
315 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
316
317 #define SMC_inw(a,r)\
318 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
319 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
320
321 #define SMC_insw LPD7_SMC_insw
322 static inline void LPD7_SMC_insw (unsigned char* a, int r,
323 unsigned char* p, int l)
324 {
325 unsigned short* ps = (unsigned short*) p;
326 while (l-- > 0) {
327 *ps++ = readw (a + r);
328 LPD7X_IOBARRIER;
329 }
330 }
331
332 #define SMC_outsw LPD7_SMC_outsw
333 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
334 unsigned char* p, int l)
335 {
336 unsigned short* ps = (unsigned short*) p;
337 while (l-- > 0) {
338 writew (*ps++, a + r);
339 LPD7X_IOBARRIER;
340 }
341 }
342
343 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
344
345 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
346 #define RPC_LSB_DEFAULT RPC_LED_100_10
347
348 #elif defined(CONFIG_SOC_AU1X00)
349
350 #include <au1xxx.h>
351
352 /* We can only do 16-bit reads and writes in the static memory space. */
353 #define SMC_CAN_USE_8BIT 0
354 #define SMC_CAN_USE_16BIT 1
355 #define SMC_CAN_USE_32BIT 0
356 #define SMC_IO_SHIFT 0
357 #define SMC_NOWAIT 1
358
359 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
360 #define SMC_insw(a, r, p, l) \
361 do { \
362 unsigned long _a = (unsigned long)((a) + (r)); \
363 int _l = (l); \
364 u16 *_p = (u16 *)(p); \
365 while (_l-- > 0) \
366 *_p++ = au_readw(_a); \
367 } while(0)
368 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
369 #define SMC_outsw(a, r, p, l) \
370 do { \
371 unsigned long _a = (unsigned long)((a) + (r)); \
372 int _l = (l); \
373 const u16 *_p = (const u16 *)(p); \
374 while (_l-- > 0) \
375 au_writew(*_p++ , _a); \
376 } while(0)
377
378 #define SMC_IRQ_FLAGS (0)
379
380 #elif defined(CONFIG_ARCH_VERSATILE)
381
382 #define SMC_CAN_USE_8BIT 1
383 #define SMC_CAN_USE_16BIT 1
384 #define SMC_CAN_USE_32BIT 1
385 #define SMC_NOWAIT 1
386
387 #define SMC_inb(a, r) readb((a) + (r))
388 #define SMC_inw(a, r) readw((a) + (r))
389 #define SMC_inl(a, r) readl((a) + (r))
390 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
391 #define SMC_outw(v, a, r) writew(v, (a) + (r))
392 #define SMC_outl(v, a, r) writel(v, (a) + (r))
393 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
394 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
395 #define SMC_IRQ_FLAGS (-1) /* from resource */
396
397 #elif defined(CONFIG_MN10300)
398
399 /*
400 * MN10300/AM33 configuration
401 */
402
403 #include <asm/unit/smc91111.h>
404
405 #else
406
407 /*
408 * Default configuration
409 */
410
411 #define SMC_CAN_USE_8BIT 1
412 #define SMC_CAN_USE_16BIT 1
413 #define SMC_CAN_USE_32BIT 1
414 #define SMC_NOWAIT 1
415
416 #define SMC_IO_SHIFT (lp->io_shift)
417
418 #define SMC_inb(a, r) readb((a) + (r))
419 #define SMC_inw(a, r) readw((a) + (r))
420 #define SMC_inl(a, r) readl((a) + (r))
421 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
422 #define SMC_outw(v, a, r) writew(v, (a) + (r))
423 #define SMC_outl(v, a, r) writel(v, (a) + (r))
424 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
425 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
426 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
427 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
428
429 #define RPC_LSA_DEFAULT RPC_LED_100_10
430 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
431
432 #endif
433
434
435 /* store this information for the driver.. */
436 struct smc_local {
437 /*
438 * If I have to wait until memory is available to send a
439 * packet, I will store the skbuff here, until I get the
440 * desired memory. Then, I'll send it out and free it.
441 */
442 struct sk_buff *pending_tx_skb;
443 struct tasklet_struct tx_task;
444
445 /* version/revision of the SMC91x chip */
446 int version;
447
448 /* Contains the current active transmission mode */
449 int tcr_cur_mode;
450
451 /* Contains the current active receive mode */
452 int rcr_cur_mode;
453
454 /* Contains the current active receive/phy mode */
455 int rpc_cur_mode;
456 int ctl_rfduplx;
457 int ctl_rspeed;
458
459 u32 msg_enable;
460 u32 phy_type;
461 struct mii_if_info mii;
462
463 /* work queue */
464 struct work_struct phy_configure;
465 struct net_device *dev;
466 int work_pending;
467
468 spinlock_t lock;
469
470 #ifdef CONFIG_ARCH_PXA
471 /* DMA needs the physical address of the chip */
472 u_long physaddr;
473 struct device *device;
474 #endif
475 void __iomem *base;
476 void __iomem *datacs;
477
478 /* the low address lines on some platforms aren't connected... */
479 int io_shift;
480
481 struct smc91x_platdata cfg;
482 };
483
484 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
485 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
486 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
487
488 #ifdef CONFIG_ARCH_PXA
489 /*
490 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
491 * always happening in irq context so no need to worry about races. TX is
492 * different and probably not worth it for that reason, and not as critical
493 * as RX which can overrun memory and lose packets.
494 */
495 #include <linux/dma-mapping.h>
496 #include <asm/dma.h>
497 #include <mach/pxa-regs.h>
498
499 #ifdef SMC_insl
500 #undef SMC_insl
501 #define SMC_insl(a, r, p, l) \
502 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
503 static inline void
504 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
505 u_char *buf, int len)
506 {
507 u_long physaddr = lp->physaddr;
508 dma_addr_t dmabuf;
509
510 /* fallback if no DMA available */
511 if (dma == (unsigned char)-1) {
512 readsl(ioaddr + reg, buf, len);
513 return;
514 }
515
516 /* 64 bit alignment is required for memory to memory DMA */
517 if ((long)buf & 4) {
518 *((u32 *)buf) = SMC_inl(ioaddr, reg);
519 buf += 4;
520 len--;
521 }
522
523 len *= 4;
524 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
525 DCSR(dma) = DCSR_NODESC;
526 DTADR(dma) = dmabuf;
527 DSADR(dma) = physaddr + reg;
528 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
529 DCMD_WIDTH4 | (DCMD_LENGTH & len));
530 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
531 while (!(DCSR(dma) & DCSR_STOPSTATE))
532 cpu_relax();
533 DCSR(dma) = 0;
534 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
535 }
536 #endif
537
538 #ifdef SMC_insw
539 #undef SMC_insw
540 #define SMC_insw(a, r, p, l) \
541 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
542 static inline void
543 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
544 u_char *buf, int len)
545 {
546 u_long physaddr = lp->physaddr;
547 dma_addr_t dmabuf;
548
549 /* fallback if no DMA available */
550 if (dma == (unsigned char)-1) {
551 readsw(ioaddr + reg, buf, len);
552 return;
553 }
554
555 /* 64 bit alignment is required for memory to memory DMA */
556 while ((long)buf & 6) {
557 *((u16 *)buf) = SMC_inw(ioaddr, reg);
558 buf += 2;
559 len--;
560 }
561
562 len *= 2;
563 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
564 DCSR(dma) = DCSR_NODESC;
565 DTADR(dma) = dmabuf;
566 DSADR(dma) = physaddr + reg;
567 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
568 DCMD_WIDTH2 | (DCMD_LENGTH & len));
569 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
570 while (!(DCSR(dma) & DCSR_STOPSTATE))
571 cpu_relax();
572 DCSR(dma) = 0;
573 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
574 }
575 #endif
576
577 static void
578 smc_pxa_dma_irq(int dma, void *dummy)
579 {
580 DCSR(dma) = 0;
581 }
582 #endif /* CONFIG_ARCH_PXA */
583
584
585 /*
586 * Everything a particular hardware setup needs should have been defined
587 * at this point. Add stubs for the undefined cases, mainly to avoid
588 * compilation warnings since they'll be optimized away, or to prevent buggy
589 * use of them.
590 */
591
592 #if ! SMC_CAN_USE_32BIT
593 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
594 #define SMC_outl(x, ioaddr, reg) BUG()
595 #define SMC_insl(a, r, p, l) BUG()
596 #define SMC_outsl(a, r, p, l) BUG()
597 #endif
598
599 #if !defined(SMC_insl) || !defined(SMC_outsl)
600 #define SMC_insl(a, r, p, l) BUG()
601 #define SMC_outsl(a, r, p, l) BUG()
602 #endif
603
604 #if ! SMC_CAN_USE_16BIT
605
606 /*
607 * Any 16-bit access is performed with two 8-bit accesses if the hardware
608 * can't do it directly. Most registers are 16-bit so those are mandatory.
609 */
610 #define SMC_outw(x, ioaddr, reg) \
611 do { \
612 unsigned int __val16 = (x); \
613 SMC_outb( __val16, ioaddr, reg ); \
614 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
615 } while (0)
616 #define SMC_inw(ioaddr, reg) \
617 ({ \
618 unsigned int __val16; \
619 __val16 = SMC_inb( ioaddr, reg ); \
620 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
621 __val16; \
622 })
623
624 #define SMC_insw(a, r, p, l) BUG()
625 #define SMC_outsw(a, r, p, l) BUG()
626
627 #endif
628
629 #if !defined(SMC_insw) || !defined(SMC_outsw)
630 #define SMC_insw(a, r, p, l) BUG()
631 #define SMC_outsw(a, r, p, l) BUG()
632 #endif
633
634 #if ! SMC_CAN_USE_8BIT
635 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
636 #define SMC_outb(x, ioaddr, reg) BUG()
637 #define SMC_insb(a, r, p, l) BUG()
638 #define SMC_outsb(a, r, p, l) BUG()
639 #endif
640
641 #if !defined(SMC_insb) || !defined(SMC_outsb)
642 #define SMC_insb(a, r, p, l) BUG()
643 #define SMC_outsb(a, r, p, l) BUG()
644 #endif
645
646 #ifndef SMC_CAN_USE_DATACS
647 #define SMC_CAN_USE_DATACS 0
648 #endif
649
650 #ifndef SMC_IO_SHIFT
651 #define SMC_IO_SHIFT 0
652 #endif
653
654 #ifndef SMC_IRQ_FLAGS
655 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
656 #endif
657
658 #ifndef SMC_INTERRUPT_PREAMBLE
659 #define SMC_INTERRUPT_PREAMBLE
660 #endif
661
662
663 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
664 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
665 #define SMC_DATA_EXTENT (4)
666
667 /*
668 . Bank Select Register:
669 .
670 . yyyy yyyy 0000 00xx
671 . xx = bank number
672 . yyyy yyyy = 0x33, for identification purposes.
673 */
674 #define BANK_SELECT (14 << SMC_IO_SHIFT)
675
676
677 // Transmit Control Register
678 /* BANK 0 */
679 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
680 #define TCR_ENABLE 0x0001 // When 1 we can transmit
681 #define TCR_LOOP 0x0002 // Controls output pin LBK
682 #define TCR_FORCOL 0x0004 // When 1 will force a collision
683 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
684 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
685 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
686 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
687 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
688 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
689 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
690
691 #define TCR_CLEAR 0 /* do NOTHING */
692 /* the default settings for the TCR register : */
693 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
694
695
696 // EPH Status Register
697 /* BANK 0 */
698 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
699 #define ES_TX_SUC 0x0001 // Last TX was successful
700 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
701 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
702 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
703 #define ES_16COL 0x0010 // 16 Collisions Reached
704 #define ES_SQET 0x0020 // Signal Quality Error Test
705 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
706 #define ES_TXDEFR 0x0080 // Transmit Deferred
707 #define ES_LATCOL 0x0200 // Late collision detected on last tx
708 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
709 #define ES_EXC_DEF 0x0800 // Excessive Deferral
710 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
711 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
712 #define ES_TXUNRN 0x8000 // Tx Underrun
713
714
715 // Receive Control Register
716 /* BANK 0 */
717 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
718 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
719 #define RCR_PRMS 0x0002 // Enable promiscuous mode
720 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
721 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
722 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
723 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
724 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
725 #define RCR_SOFTRST 0x8000 // resets the chip
726
727 /* the normal settings for the RCR register : */
728 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
729 #define RCR_CLEAR 0x0 // set it to a base state
730
731
732 // Counter Register
733 /* BANK 0 */
734 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
735
736
737 // Memory Information Register
738 /* BANK 0 */
739 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
740
741
742 // Receive/Phy Control Register
743 /* BANK 0 */
744 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
745 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
746 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
747 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
748 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
749 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
750
751 #ifndef RPC_LSA_DEFAULT
752 #define RPC_LSA_DEFAULT RPC_LED_100
753 #endif
754 #ifndef RPC_LSB_DEFAULT
755 #define RPC_LSB_DEFAULT RPC_LED_FD
756 #endif
757
758 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
759
760
761 /* Bank 0 0x0C is reserved */
762
763 // Bank Select Register
764 /* All Banks */
765 #define BSR_REG 0x000E
766
767
768 // Configuration Reg
769 /* BANK 1 */
770 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
771 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
772 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
773 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
774 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
775
776 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
777 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
778
779
780 // Base Address Register
781 /* BANK 1 */
782 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
783
784
785 // Individual Address Registers
786 /* BANK 1 */
787 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
788 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
789 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
790
791
792 // General Purpose Register
793 /* BANK 1 */
794 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
795
796
797 // Control Register
798 /* BANK 1 */
799 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
800 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
801 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
802 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
803 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
804 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
805 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
806 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
807 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
808
809
810 // MMU Command Register
811 /* BANK 2 */
812 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
813 #define MC_BUSY 1 // When 1 the last release has not completed
814 #define MC_NOP (0<<5) // No Op
815 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
816 #define MC_RESET (2<<5) // Reset MMU to initial state
817 #define MC_REMOVE (3<<5) // Remove the current rx packet
818 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
819 #define MC_FREEPKT (5<<5) // Release packet in PNR register
820 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
821 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
822
823
824 // Packet Number Register
825 /* BANK 2 */
826 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
827
828
829 // Allocation Result Register
830 /* BANK 2 */
831 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
832 #define AR_FAILED 0x80 // Alocation Failed
833
834
835 // TX FIFO Ports Register
836 /* BANK 2 */
837 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
838 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
839
840 // RX FIFO Ports Register
841 /* BANK 2 */
842 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
843 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
844
845 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
846
847 // Pointer Register
848 /* BANK 2 */
849 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
850 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
851 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
852 #define PTR_READ 0x2000 // When 1 the operation is a read
853
854
855 // Data Register
856 /* BANK 2 */
857 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
858
859
860 // Interrupt Status/Acknowledge Register
861 /* BANK 2 */
862 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
863
864
865 // Interrupt Mask Register
866 /* BANK 2 */
867 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
868 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
869 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
870 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
871 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
872 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
873 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
874 #define IM_TX_INT 0x02 // Transmit Interrupt
875 #define IM_RCV_INT 0x01 // Receive Interrupt
876
877
878 // Multicast Table Registers
879 /* BANK 3 */
880 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
881 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
882 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
883 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
884
885
886 // Management Interface Register (MII)
887 /* BANK 3 */
888 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
889 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
890 #define MII_MDOE 0x0008 // MII Output Enable
891 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
892 #define MII_MDI 0x0002 // MII Input, pin MDI
893 #define MII_MDO 0x0001 // MII Output, pin MDO
894
895
896 // Revision Register
897 /* BANK 3 */
898 /* ( hi: chip id low: rev # ) */
899 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
900
901
902 // Early RCV Register
903 /* BANK 3 */
904 /* this is NOT on SMC9192 */
905 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
906 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
907 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
908
909
910 // External Register
911 /* BANK 7 */
912 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
913
914
915 #define CHIP_9192 3
916 #define CHIP_9194 4
917 #define CHIP_9195 5
918 #define CHIP_9196 6
919 #define CHIP_91100 7
920 #define CHIP_91100FD 8
921 #define CHIP_91111FD 9
922
923 static const char * chip_ids[ 16 ] = {
924 NULL, NULL, NULL,
925 /* 3 */ "SMC91C90/91C92",
926 /* 4 */ "SMC91C94",
927 /* 5 */ "SMC91C95",
928 /* 6 */ "SMC91C96",
929 /* 7 */ "SMC91C100",
930 /* 8 */ "SMC91C100FD",
931 /* 9 */ "SMC91C11xFD",
932 NULL, NULL, NULL,
933 NULL, NULL, NULL};
934
935
936 /*
937 . Receive status bits
938 */
939 #define RS_ALGNERR 0x8000
940 #define RS_BRODCAST 0x4000
941 #define RS_BADCRC 0x2000
942 #define RS_ODDFRAME 0x1000
943 #define RS_TOOLONG 0x0800
944 #define RS_TOOSHORT 0x0400
945 #define RS_MULTICAST 0x0001
946 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
947
948
949 /*
950 * PHY IDs
951 * LAN83C183 == LAN91C111 Internal PHY
952 */
953 #define PHY_LAN83C183 0x0016f840
954 #define PHY_LAN83C180 0x02821c50
955
956 /*
957 * PHY Register Addresses (LAN91C111 Internal PHY)
958 *
959 * Generic PHY registers can be found in <linux/mii.h>
960 *
961 * These phy registers are specific to our on-board phy.
962 */
963
964 // PHY Configuration Register 1
965 #define PHY_CFG1_REG 0x10
966 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
967 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
968 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
969 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
970 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
971 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
972 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
973 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
974 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
975 #define PHY_CFG1_TLVL_MASK 0x003C
976 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
977
978
979 // PHY Configuration Register 2
980 #define PHY_CFG2_REG 0x11
981 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
982 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
983 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
984 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
985
986 // PHY Status Output (and Interrupt status) Register
987 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
988 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
989 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
990 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
991 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
992 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
993 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
994 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
995 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
996 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
997 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
998
999 // PHY Interrupt/Status Mask Register
1000 #define PHY_MASK_REG 0x13 // Interrupt Mask
1001 // Uses the same bit definitions as PHY_INT_REG
1002
1003
1004 /*
1005 * SMC91C96 ethernet config and status registers.
1006 * These are in the "attribute" space.
1007 */
1008 #define ECOR 0x8000
1009 #define ECOR_RESET 0x80
1010 #define ECOR_LEVEL_IRQ 0x40
1011 #define ECOR_WR_ATTRIB 0x04
1012 #define ECOR_ENABLE 0x01
1013
1014 #define ECSR 0x8002
1015 #define ECSR_IOIS8 0x20
1016 #define ECSR_PWRDWN 0x04
1017 #define ECSR_INT 0x02
1018
1019 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1020
1021
1022 /*
1023 * Macros to abstract register access according to the data bus
1024 * capabilities. Please use those and not the in/out primitives.
1025 * Note: the following macros do *not* select the bank -- this must
1026 * be done separately as needed in the main code. The SMC_REG() macro
1027 * only uses the bank argument for debugging purposes (when enabled).
1028 *
1029 * Note: despite inline functions being safer, everything leading to this
1030 * should preferably be macros to let BUG() display the line number in
1031 * the core source code since we're interested in the top call site
1032 * not in any inline function location.
1033 */
1034
1035 #if SMC_DEBUG > 0
1036 #define SMC_REG(lp, reg, bank) \
1037 ({ \
1038 int __b = SMC_CURRENT_BANK(lp); \
1039 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1040 printk( "%s: bank reg screwed (0x%04x)\n", \
1041 CARDNAME, __b ); \
1042 BUG(); \
1043 } \
1044 reg<<SMC_IO_SHIFT; \
1045 })
1046 #else
1047 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1048 #endif
1049
1050 /*
1051 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1052 * aligned to a 32 bit boundary. I tell you that does exist!
1053 * Fortunately the affected register accesses can be easily worked around
1054 * since we can write zeroes to the preceeding 16 bits without adverse
1055 * effects and use a 32-bit access.
1056 *
1057 * Enforce it on any 32-bit capable setup for now.
1058 */
1059 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
1060
1061 #define SMC_GET_PN(lp) \
1062 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1063 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1064
1065 #define SMC_SET_PN(lp, x) \
1066 do { \
1067 if (SMC_MUST_ALIGN_WRITE(lp)) \
1068 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1069 else if (SMC_8BIT(lp)) \
1070 SMC_outb(x, ioaddr, PN_REG(lp)); \
1071 else \
1072 SMC_outw(x, ioaddr, PN_REG(lp)); \
1073 } while (0)
1074
1075 #define SMC_GET_AR(lp) \
1076 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1077 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1078
1079 #define SMC_GET_TXFIFO(lp) \
1080 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1081 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1082
1083 #define SMC_GET_RXFIFO(lp) \
1084 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1085 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1086
1087 #define SMC_GET_INT(lp) \
1088 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1089 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1090
1091 #define SMC_ACK_INT(lp, x) \
1092 do { \
1093 if (SMC_8BIT(lp)) \
1094 SMC_outb(x, ioaddr, INT_REG(lp)); \
1095 else { \
1096 unsigned long __flags; \
1097 int __mask; \
1098 local_irq_save(__flags); \
1099 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1100 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1101 local_irq_restore(__flags); \
1102 } \
1103 } while (0)
1104
1105 #define SMC_GET_INT_MASK(lp) \
1106 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1107 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1108
1109 #define SMC_SET_INT_MASK(lp, x) \
1110 do { \
1111 if (SMC_8BIT(lp)) \
1112 SMC_outb(x, ioaddr, IM_REG(lp)); \
1113 else \
1114 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1115 } while (0)
1116
1117 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1118
1119 #define SMC_SELECT_BANK(lp, x) \
1120 do { \
1121 if (SMC_MUST_ALIGN_WRITE(lp)) \
1122 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1123 else \
1124 SMC_outw(x, ioaddr, BANK_SELECT); \
1125 } while (0)
1126
1127 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1128
1129 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1130
1131 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1132
1133 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1134
1135 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1136
1137 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1138
1139 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1140
1141 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1142
1143 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1144
1145 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1146
1147 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1148
1149 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1150
1151 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1152
1153 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1154
1155 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1156
1157 #define SMC_SET_PTR(lp, x) \
1158 do { \
1159 if (SMC_MUST_ALIGN_WRITE(lp)) \
1160 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1161 else \
1162 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1163 } while (0)
1164
1165 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1166
1167 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1168
1169 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1170
1171 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1172
1173 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1174
1175 #define SMC_SET_RPC(lp, x) \
1176 do { \
1177 if (SMC_MUST_ALIGN_WRITE(lp)) \
1178 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1179 else \
1180 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1181 } while (0)
1182
1183 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1184
1185 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1186
1187 #ifndef SMC_GET_MAC_ADDR
1188 #define SMC_GET_MAC_ADDR(lp, addr) \
1189 do { \
1190 unsigned int __v; \
1191 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1192 addr[0] = __v; addr[1] = __v >> 8; \
1193 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1194 addr[2] = __v; addr[3] = __v >> 8; \
1195 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1196 addr[4] = __v; addr[5] = __v >> 8; \
1197 } while (0)
1198 #endif
1199
1200 #define SMC_SET_MAC_ADDR(lp, addr) \
1201 do { \
1202 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1203 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1204 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1205 } while (0)
1206
1207 #define SMC_SET_MCAST(lp, x) \
1208 do { \
1209 const unsigned char *mt = (x); \
1210 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1211 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1212 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1213 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1214 } while (0)
1215
1216 #define SMC_PUT_PKT_HDR(lp, status, length) \
1217 do { \
1218 if (SMC_32BIT(lp)) \
1219 SMC_outl((status) | (length)<<16, ioaddr, \
1220 DATA_REG(lp)); \
1221 else { \
1222 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1223 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1224 } \
1225 } while (0)
1226
1227 #define SMC_GET_PKT_HDR(lp, status, length) \
1228 do { \
1229 if (SMC_32BIT(lp)) { \
1230 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1231 (status) = __val & 0xffff; \
1232 (length) = __val >> 16; \
1233 } else { \
1234 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1235 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1236 } \
1237 } while (0)
1238
1239 #define SMC_PUSH_DATA(lp, p, l) \
1240 do { \
1241 if (SMC_32BIT(lp)) { \
1242 void *__ptr = (p); \
1243 int __len = (l); \
1244 void __iomem *__ioaddr = ioaddr; \
1245 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1246 __len -= 2; \
1247 SMC_outw(*(u16 *)__ptr, ioaddr, \
1248 DATA_REG(lp)); \
1249 __ptr += 2; \
1250 } \
1251 if (SMC_CAN_USE_DATACS && lp->datacs) \
1252 __ioaddr = lp->datacs; \
1253 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1254 if (__len & 2) { \
1255 __ptr += (__len & ~3); \
1256 SMC_outw(*((u16 *)__ptr), ioaddr, \
1257 DATA_REG(lp)); \
1258 } \
1259 } else if (SMC_16BIT(lp)) \
1260 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1261 else if (SMC_8BIT(lp)) \
1262 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1263 } while (0)
1264
1265 #define SMC_PULL_DATA(lp, p, l) \
1266 do { \
1267 if (SMC_32BIT(lp)) { \
1268 void *__ptr = (p); \
1269 int __len = (l); \
1270 void __iomem *__ioaddr = ioaddr; \
1271 if ((unsigned long)__ptr & 2) { \
1272 /* \
1273 * We want 32bit alignment here. \
1274 * Since some buses perform a full \
1275 * 32bit fetch even for 16bit data \
1276 * we can't use SMC_inw() here. \
1277 * Back both source (on-chip) and \
1278 * destination pointers of 2 bytes. \
1279 * This is possible since the call to \
1280 * SMC_GET_PKT_HDR() already advanced \
1281 * the source pointer of 4 bytes, and \
1282 * the skb_reserve(skb, 2) advanced \
1283 * the destination pointer of 2 bytes. \
1284 */ \
1285 __ptr -= 2; \
1286 __len += 2; \
1287 SMC_SET_PTR(lp, \
1288 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1289 } \
1290 if (SMC_CAN_USE_DATACS && lp->datacs) \
1291 __ioaddr = lp->datacs; \
1292 __len += 2; \
1293 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1294 } else if (SMC_16BIT(lp)) \
1295 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1296 else if (SMC_8BIT(lp)) \
1297 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1298 } while (0)
1299
1300 #endif /* _SMC91X_H_ */
Support for the Chinese Samsung S3C2440 based development boards