1 #include <linux/kernel.h>
2 #include <linux/errno.h>
3 #include <linux/string.h>
5 #include <linux/slab.h>
6 #include <linux/delay.h>
7 #include <linux/interrupt.h>
8 #include <linux/platform_device.h>
10 #include <asm/setup.h>
11 #include <asm/system.h>
13 #include <asm/amigahw.h>
14 #include <asm/amigaints.h>
15 #include <asm/apollohw.h>
17 #include <linux/module.h>
19 /* apollo video HW definitions */
22 * Control Registers. IOBASE + $x
24 * Note: these are the Memory/IO BASE definitions for a mono card set to the
27 * Control 3A and 3B serve identical functions except that 3A
28 * deals with control 1 and 3b deals with Color LUT reg.
31 #define AP_IOBASE 0x3b0 /* Base address of 1 plane board. */
32 #define AP_STATUS isaIO2mem(AP_IOBASE+0) /* Status register. Read */
33 #define AP_WRITE_ENABLE isaIO2mem(AP_IOBASE+0) /* Write Enable Register Write */
34 #define AP_DEVICE_ID isaIO2mem(AP_IOBASE+1) /* Device ID Register. Read */
35 #define AP_ROP_1 isaIO2mem(AP_IOBASE+2) /* Raster Operation reg. Write Word */
36 #define AP_DIAG_MEM_REQ isaIO2mem(AP_IOBASE+4) /* Diagnostic Memory Request. Write Word */
37 #define AP_CONTROL_0 isaIO2mem(AP_IOBASE+8) /* Control Register 0. Read/Write */
38 #define AP_CONTROL_1 isaIO2mem(AP_IOBASE+0xa) /* Control Register 1. Read/Write */
39 #define AP_CONTROL_3A isaIO2mem(AP_IOBASE+0xe) /* Control Register 3a. Read/Write */
40 #define AP_CONTROL_2 isaIO2mem(AP_IOBASE+0xc) /* Control Register 2. Read/Write */
43 #define FRAME_BUFFER_START 0x0FA0000
44 #define FRAME_BUFFER_LEN 0x40000
47 #define VECTOR_MODE 0x40 /* 010x.xxxx */
48 #define DBLT_MODE 0x80 /* 100x.xxxx */
49 #define NORMAL_MODE 0xE0 /* 111x.xxxx */
50 #define SHIFT_BITS 0x1F /* xxx1.1111 */
51 /* other bits are Shift value */
54 #define AD_BLT 0x80 /* 1xxx.xxxx */
55 #define NORMAL 0x80 /* 1xxx.xxxx */ /* What is happening here ?? */
56 #define INVERSE 0x00 /* 0xxx.xxxx */ /* Clearing this reverses the screen */
57 #define PIX_BLT 0x00 /* 0xxx.xxxx */
59 #define AD_HIBIT 0x40 /* xIxx.xxxx */
61 #define ROP_EN 0x10 /* xxx1.xxxx */
62 #define DST_EQ_SRC 0x00 /* xxx0.xxxx */
63 #define nRESET_SYNC 0x08 /* xxxx.1xxx */
64 #define SYNC_ENAB 0x02 /* xxxx.xx1x */
66 #define BLANK_DISP 0x00 /* xxxx.xxx0 */
67 #define ENAB_DISP 0x01 /* xxxx.xxx1 */
69 #define NORM_CREG1 (nRESET_SYNC | SYNC_ENAB | ENAB_DISP) /* no reset sync */
74 * Following 3 defines are common to 1, 4 and 8 plane.
77 #define S_DATA_1s 0x00 /* 00xx.xxxx */ /* set source to all 1's -- vector drawing */
78 #define S_DATA_PIX 0x40 /* 01xx.xxxx */ /* takes source from ls-bits and replicates over 16 bits */
79 #define S_DATA_PLN 0xC0 /* 11xx.xxxx */ /* normal, each data access =16-bits in
80 one plane of image mem */
83 # define RESET_CREG 0x80 /* 1000.0000 */
85 /* ROP REG - all one nibble */
86 /* ********* NOTE : this is used r0,r1,r2,r3 *********** */
87 #define ROP(r2,r3,r0,r1) ( (U_SHORT)((r0)|((r1)<<4)|((r2)<<8)|((r3)<<12)) )
89 #define SRC_AND_DEST 0x1
90 #define SRC_AND_nDEST 0x2
92 #define nSRC_AND_DEST 0x4
94 #define SRC_XOR_DEST 0x6
95 #define SRC_OR_DEST 0x7
96 #define SRC_NOR_DEST 0x8
97 #define SRC_XNOR_DEST 0x9
99 #define SRC_OR_nDEST 0xB
101 #define nSRC_OR_DEST 0xD
102 #define SRC_NAND_DEST 0xE
105 #define SWAP(A) ((A>>8) | ((A&0xff) <<8))
107 /* frame buffer operations */
109 static int dnfb_blank(int blank
, struct fb_info
*info
);
110 static void dnfb_copyarea(struct fb_info
*info
, const struct fb_copyarea
*area
);
112 static struct fb_ops dn_fb_ops
= {
113 .owner
= THIS_MODULE
,
114 .fb_blank
= dnfb_blank
,
115 .fb_fillrect
= cfb_fillrect
,
116 .fb_copyarea
= dnfb_copyarea
,
117 .fb_imageblit
= cfb_imageblit
,
120 struct fb_var_screeninfo dnfb_var __devinitdata
= {
123 .xres_virtual
= 2048,
124 .yres_virtual
= 1024,
128 .vmode
= FB_VMODE_NONINTERLACED
,
131 static struct fb_fix_screeninfo dnfb_fix __devinitdata
= {
133 .smem_start
= (FRAME_BUFFER_START
+ IO_BASE
),
134 .smem_len
= FRAME_BUFFER_LEN
,
135 .type
= FB_TYPE_PACKED_PIXELS
,
136 .visual
= FB_VISUAL_MONO10
,
140 static int dnfb_blank(int blank
, struct fb_info
*info
)
143 out_8(AP_CONTROL_3A
, 0x0);
145 out_8(AP_CONTROL_3A
, 0x1);
150 void dnfb_copyarea(struct fb_info
*info
, const struct fb_copyarea
*area
)
153 int incr
, y_delta
, pre_read
= 0, x_end
, x_word_count
;
154 uint start_mask
, end_mask
, dest
;
158 incr
= (area
->dy
<= area
->sy
) ? 1 : -1;
160 src
= (ushort
*)(info
->screen_base
+ area
->sy
* info
->fix
.line_length
+
162 dest
= area
->dy
* (info
->fix
.line_length
>> 1) + (area
->dx
>> 4);
165 y_delta
= (info
->fix
.line_length
* 8) - area
->sx
- area
->width
;
166 x_end
= area
->dx
+ area
->width
- 1;
167 x_word_count
= (x_end
>> 4) - (area
->dx
>> 4) + 1;
168 start_mask
= 0xffff0000 >> (area
->dx
& 0xf);
169 end_mask
= 0x7ffff >> (x_end
& 0xf);
171 (((area
->dx
& 0xf) - (area
->sx
& 0xf)) % 16) | (0x4 << 5));
172 if ((area
->dx
& 0xf) < (area
->sx
& 0xf))
175 y_delta
= -((info
->fix
.line_length
* 8) - area
->sx
- area
->width
);
176 x_end
= area
->dx
- area
->width
+ 1;
177 x_word_count
= (area
->dx
>> 4) - (x_end
>> 4) + 1;
178 start_mask
= 0x7ffff >> (area
->dx
& 0xf);
179 end_mask
= 0xffff0000 >> (x_end
& 0xf);
181 ((-((area
->sx
& 0xf) - (area
->dx
& 0xf))) % 16) |
183 if ((area
->dx
& 0xf) > (area
->sx
& 0xf))
187 for (i
= 0; i
< area
->height
; i
++) {
189 out_8(AP_CONTROL_3A
, 0xc | (dest
>> 16));
197 out_8(AP_WRITE_ENABLE
, start_mask
);
201 out_8(AP_WRITE_ENABLE
, 0);
203 for (j
= 1; j
< (x_word_count
- 1); j
++) {
209 out_8(AP_WRITE_ENABLE
, start_mask
);
214 out_8(AP_WRITE_ENABLE
, start_mask
| end_mask
);
219 src
+= (y_delta
/ 16);
220 dest
+= (y_delta
/ 16);
222 out_8(AP_CONTROL_0
, NORMAL_MODE
);
229 static int __devinit
dnfb_probe(struct platform_device
*dev
)
231 struct fb_info
*info
;
234 info
= framebuffer_alloc(0, &dev
->dev
);
238 info
->fbops
= &dn_fb_ops
;
239 info
->fix
= dnfb_fix
;
240 info
->var
= dnfb_var
;
241 info
->var
.red
.length
= 1;
242 info
->var
.red
.offset
= 0;
243 info
->var
.green
= info
->var
.blue
= info
->var
.red
;
244 info
->screen_base
= (u_char
*) info
->fix
.smem_start
;
246 err
= fb_alloc_cmap(&info
->cmap
, 2, 0);
248 framebuffer_release(info
);
252 err
= register_framebuffer(info
);
254 fb_dealloc_cmap(&info
->cmap
);
255 framebuffer_release(info
);
258 platform_set_drvdata(dev
, info
);
260 /* now we have registered we can safely setup the hardware */
261 out_8(AP_CONTROL_3A
, RESET_CREG
);
262 out_be16(AP_WRITE_ENABLE
, 0x0);
263 out_8(AP_CONTROL_0
, NORMAL_MODE
);
264 out_8(AP_CONTROL_1
, (AD_BLT
| DST_EQ_SRC
| NORM_CREG1
));
265 out_8(AP_CONTROL_2
, S_DATA_PLN
);
266 out_be16(AP_ROP_1
, SWAP(0x3));
268 printk("apollo frame buffer alive and kicking !\n");
272 static struct platform_driver dnfb_driver
= {
279 static struct platform_device dnfb_device
= {
283 int __init
dnfb_init(void)
287 if (fb_get_options("dnfb", NULL
))
290 ret
= platform_driver_register(&dnfb_driver
);
293 ret
= platform_device_register(&dnfb_device
);
295 platform_driver_unregister(&dnfb_driver
);
300 module_init(dnfb_init
);
302 MODULE_LICENSE("GPL");