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wl12xx: Use chipset specific join commands
[linux-2.6/mini2440.git] / drivers / net / wireless / wl12xx / wl1251.c
blob77494a9046e570b817008783a74c3280b68bd9aa
1 /*
2 * This file is part of wl12xx
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Contact: Kalle Valo <kalle.valo@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26
27 #include "wl1251.h"
28 #include "reg.h"
29 #include "spi.h"
30 #include "boot.h"
31 #include "event.h"
32 #include "acx.h"
33 #include "wl1251_tx.h"
34 #include "rx.h"
35 #include "ps.h"
36 #include "init.h"
37
38 static struct wl12xx_partition_set wl1251_part_table[PART_TABLE_LEN] = {
39 [PART_DOWN] = {
40 .mem = {
41 .start = 0x00000000,
42 .size = 0x00016800
43 },
44 .reg = {
45 .start = REGISTERS_BASE,
46 .size = REGISTERS_DOWN_SIZE
47 },
48 },
49
50 [PART_WORK] = {
51 .mem = {
52 .start = 0x00028000,
53 .size = 0x00014000
54 },
55 .reg = {
56 .start = REGISTERS_BASE,
57 .size = REGISTERS_WORK_SIZE
58 },
59 },
60
61 /* WL1251 doesn't use the DRPW partition, so we don't set it here */
62 };
63
64 static enum wl12xx_acx_int_reg wl1251_acx_reg_table[ACX_REG_TABLE_LEN] = {
65 [ACX_REG_INTERRUPT_TRIG] = (REGISTERS_BASE + 0x0474),
66 [ACX_REG_INTERRUPT_TRIG_H] = (REGISTERS_BASE + 0x0478),
67 [ACX_REG_INTERRUPT_MASK] = (REGISTERS_BASE + 0x0494),
68 [ACX_REG_HINT_MASK_SET] = (REGISTERS_BASE + 0x0498),
69 [ACX_REG_HINT_MASK_CLR] = (REGISTERS_BASE + 0x049C),
70 [ACX_REG_INTERRUPT_NO_CLEAR] = (REGISTERS_BASE + 0x04B0),
71 [ACX_REG_INTERRUPT_CLEAR] = (REGISTERS_BASE + 0x04A4),
72 [ACX_REG_INTERRUPT_ACK] = (REGISTERS_BASE + 0x04A8),
73 [ACX_REG_SLV_SOFT_RESET] = (REGISTERS_BASE + 0x0000),
74 [ACX_REG_EE_START] = (REGISTERS_BASE + 0x080C),
75 [ACX_REG_ECPU_CONTROL] = (REGISTERS_BASE + 0x0804)
76 };
77
78 static int wl1251_upload_firmware(struct wl12xx *wl)
79 {
80 struct wl12xx_partition_set *p_table = wl->chip.p_table;
81 int addr, chunk_num, partition_limit;
82 size_t fw_data_len;
83 u8 *p;
84
85 /* whal_FwCtrl_LoadFwImageSm() */
86
87 wl12xx_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
88 wl12xx_reg_read32(wl, CHIP_ID_B));
89
90 /* 10.0 check firmware length and set partition */
91 fw_data_len = (wl->fw[4] << 24) | (wl->fw[5] << 16) |
92 (wl->fw[6] << 8) | (wl->fw[7]);
93
94 wl12xx_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
95 CHUNK_SIZE);
96
97 if ((fw_data_len % 4) != 0) {
98 wl12xx_error("firmware length not multiple of four");
99 return -EIO;
100 }
101
102 wl12xx_set_partition(wl,
103 p_table[PART_DOWN].mem.start,
104 p_table[PART_DOWN].mem.size,
105 p_table[PART_DOWN].reg.start,
106 p_table[PART_DOWN].reg.size);
107
108 /* 10.1 set partition limit and chunk num */
109 chunk_num = 0;
110 partition_limit = p_table[PART_DOWN].mem.size;
111
112 while (chunk_num < fw_data_len / CHUNK_SIZE) {
113 /* 10.2 update partition, if needed */
114 addr = p_table[PART_DOWN].mem.start +
115 (chunk_num + 2) * CHUNK_SIZE;
116 if (addr > partition_limit) {
117 addr = p_table[PART_DOWN].mem.start +
118 chunk_num * CHUNK_SIZE;
119 partition_limit = chunk_num * CHUNK_SIZE +
120 p_table[PART_DOWN].mem.size;
121 wl12xx_set_partition(wl,
122 addr,
123 p_table[PART_DOWN].mem.size,
124 p_table[PART_DOWN].reg.start,
125 p_table[PART_DOWN].reg.size);
126 }
127
128 /* 10.3 upload the chunk */
129 addr = p_table[PART_DOWN].mem.start + chunk_num * CHUNK_SIZE;
130 p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
131 wl12xx_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
132 p, addr);
133 wl12xx_spi_mem_write(wl, addr, p, CHUNK_SIZE);
134
135 chunk_num++;
136 }
137
138 /* 10.4 upload the last chunk */
139 addr = p_table[PART_DOWN].mem.start + chunk_num * CHUNK_SIZE;
140 p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
141 wl12xx_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
142 fw_data_len % CHUNK_SIZE, p, addr);
143 wl12xx_spi_mem_write(wl, addr, p, fw_data_len % CHUNK_SIZE);
144
145 return 0;
146 }
147
148 static int wl1251_upload_nvs(struct wl12xx *wl)
149 {
150 size_t nvs_len, nvs_bytes_written, burst_len;
151 int nvs_start, i;
152 u32 dest_addr, val;
153 u8 *nvs_ptr, *nvs;
154
155 nvs = wl->nvs;
156 if (nvs == NULL)
157 return -ENODEV;
158
159 nvs_ptr = nvs;
160
161 nvs_len = wl->nvs_len;
162 nvs_start = wl->fw_len;
163
164 /*
165 * Layout before the actual NVS tables:
166 * 1 byte : burst length.
167 * 2 bytes: destination address.
168 * n bytes: data to burst copy.
169 *
170 * This is ended by a 0 length, then the NVS tables.
171 */
172
173 while (nvs_ptr[0]) {
174 burst_len = nvs_ptr[0];
175 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
176
177 /* We move our pointer to the data */
178 nvs_ptr += 3;
179
180 for (i = 0; i < burst_len; i++) {
181 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
182 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
183
184 wl12xx_debug(DEBUG_BOOT,
185 "nvs burst write 0x%x: 0x%x",
186 dest_addr, val);
187 wl12xx_mem_write32(wl, dest_addr, val);
188
189 nvs_ptr += 4;
190 dest_addr += 4;
191 }
192 }
193
194 /*
195 * We've reached the first zero length, the first NVS table
196 * is 7 bytes further.
197 */
198 nvs_ptr += 7;
199 nvs_len -= nvs_ptr - nvs;
200 nvs_len = ALIGN(nvs_len, 4);
201
202 /* Now we must set the partition correctly */
203 wl12xx_set_partition(wl, nvs_start,
204 wl->chip.p_table[PART_DOWN].mem.size,
205 wl->chip.p_table[PART_DOWN].reg.start,
206 wl->chip.p_table[PART_DOWN].reg.size);
207
208 /* And finally we upload the NVS tables */
209 nvs_bytes_written = 0;
210 while (nvs_bytes_written < nvs_len) {
211 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
212 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
213
214 val = cpu_to_le32(val);
215
216 wl12xx_debug(DEBUG_BOOT,
217 "nvs write table 0x%x: 0x%x",
218 nvs_start, val);
219 wl12xx_mem_write32(wl, nvs_start, val);
220
221 nvs_ptr += 4;
222 nvs_bytes_written += 4;
223 nvs_start += 4;
224 }
225
226 return 0;
227 }
228
229 static int wl1251_boot(struct wl12xx *wl)
230 {
231 int ret = 0, minor_minor_e2_ver;
232 u32 tmp, boot_data;
233
234 ret = wl12xx_boot_soft_reset(wl);
235 if (ret < 0)
236 goto out;
237
238 /* 2. start processing NVS file */
239 ret = wl->chip.op_upload_nvs(wl);
240 if (ret < 0)
241 goto out;
242
243 /* write firmware's last address (ie. it's length) to
244 * ACX_EEPROMLESS_IND_REG */
245 wl12xx_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
246
247 /* 6. read the EEPROM parameters */
248 tmp = wl12xx_reg_read32(wl, SCR_PAD2);
249
250 /* 7. read bootdata */
251 wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
252 wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
253 tmp = wl12xx_reg_read32(wl, SCR_PAD3);
254
255 /* 8. check bootdata and call restart sequence */
256 wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
257 minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;
258
259 wl12xx_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
260 "minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
261 wl->boot_attr.radio_type, wl->boot_attr.major,
262 wl->boot_attr.minor, minor_minor_e2_ver);
263
264 ret = wl12xx_boot_init_seq(wl);
265 if (ret < 0)
266 goto out;
267
268 /* 9. NVS processing done */
269 boot_data = wl12xx_reg_read32(wl, ACX_REG_ECPU_CONTROL);
270
271 wl12xx_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);
272
273 /* 10. check that ECPU_CONTROL_HALT bits are set in
274 * pWhalBus->uBootData and start uploading firmware
275 */
276 if ((boot_data & ECPU_CONTROL_HALT) == 0) {
277 wl12xx_error("boot failed, ECPU_CONTROL_HALT not set");
278 ret = -EIO;
279 goto out;
280 }
281
282 ret = wl->chip.op_upload_fw(wl);
283 if (ret < 0)
284 goto out;
285
286 /* 10.5 start firmware */
287 ret = wl12xx_boot_run_firmware(wl);
288 if (ret < 0)
289 goto out;
290
291 out:
292 return ret;
293 }
294
295 static int wl1251_mem_cfg(struct wl12xx *wl)
296 {
297 struct wl1251_acx_config_memory *mem_conf;
298 int ret, i;
299
300 wl12xx_debug(DEBUG_ACX, "wl1251 mem cfg");
301
302 mem_conf = kzalloc(sizeof(*mem_conf), GFP_KERNEL);
303 if (!mem_conf) {
304 ret = -ENOMEM;
305 goto out;
306 }
307
308 /* memory config */
309 mem_conf->mem_config.num_stations = cpu_to_le16(DEFAULT_NUM_STATIONS);
310 mem_conf->mem_config.rx_mem_block_num = 35;
311 mem_conf->mem_config.tx_min_mem_block_num = 64;
312 mem_conf->mem_config.num_tx_queues = MAX_TX_QUEUES;
313 mem_conf->mem_config.host_if_options = HOSTIF_PKT_RING;
314 mem_conf->mem_config.num_ssid_profiles = 1;
315 mem_conf->mem_config.debug_buffer_size =
316 cpu_to_le16(TRACE_BUFFER_MAX_SIZE);
317
318 /* RX queue config */
319 mem_conf->rx_queue_config.dma_address = 0;
320 mem_conf->rx_queue_config.num_descs = ACX_RX_DESC_DEF;
321 mem_conf->rx_queue_config.priority = DEFAULT_RXQ_PRIORITY;
322 mem_conf->rx_queue_config.type = DEFAULT_RXQ_TYPE;
323
324 /* TX queue config */
325 for (i = 0; i < MAX_TX_QUEUES; i++) {
326 mem_conf->tx_queue_config[i].num_descs = ACX_TX_DESC_DEF;
327 mem_conf->tx_queue_config[i].attributes = i;
328 }
329
330 ret = wl12xx_cmd_configure(wl, ACX_MEM_CFG, mem_conf,
331 sizeof(*mem_conf));
332 if (ret < 0) {
333 wl12xx_warning("wl1251 mem config failed: %d", ret);
334 goto out;
335 }
336
337 out:
338 kfree(mem_conf);
339 return ret;
340 }
341
342 static int wl1251_hw_init_mem_config(struct wl12xx *wl)
343 {
344 int ret;
345
346 ret = wl1251_mem_cfg(wl);
347 if (ret < 0)
348 return ret;
349
350 wl->target_mem_map = kzalloc(sizeof(struct wl1251_acx_mem_map),
351 GFP_KERNEL);
352 if (!wl->target_mem_map) {
353 wl12xx_error("couldn't allocate target memory map");
354 return -ENOMEM;
355 }
356
357 /* we now ask for the firmware built memory map */
358 ret = wl12xx_acx_mem_map(wl, wl->target_mem_map,
359 sizeof(struct wl1251_acx_mem_map));
360 if (ret < 0) {
361 wl12xx_error("couldn't retrieve firmware memory map");
362 kfree(wl->target_mem_map);
363 wl->target_mem_map = NULL;
364 return ret;
365 }
366
367 return 0;
368 }
369
370 static void wl1251_set_ecpu_ctrl(struct wl12xx *wl, u32 flag)
371 {
372 u32 cpu_ctrl;
373
374 /* 10.5.0 run the firmware (I) */
375 cpu_ctrl = wl12xx_reg_read32(wl, ACX_REG_ECPU_CONTROL);
376
377 /* 10.5.1 run the firmware (II) */
378 cpu_ctrl &= ~flag;
379 wl12xx_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
380 }
381
382 static void wl1251_target_enable_interrupts(struct wl12xx *wl)
383 {
384 /* Enable target's interrupts */
385 wl->intr_mask = WL1251_ACX_INTR_RX0_DATA |
386 WL1251_ACX_INTR_RX1_DATA |
387 WL1251_ACX_INTR_TX_RESULT |
388 WL1251_ACX_INTR_EVENT_A |
389 WL1251_ACX_INTR_EVENT_B |
390 WL1251_ACX_INTR_INIT_COMPLETE;
391 wl12xx_boot_target_enable_interrupts(wl);
392 }
393
394 static void wl1251_fw_version(struct wl12xx *wl)
395 {
396 wl12xx_acx_fw_version(wl, wl->chip.fw_ver, sizeof(wl->chip.fw_ver));
397 }
398
399 static void wl1251_irq_work(struct work_struct *work)
400 {
401 u32 intr;
402 struct wl12xx *wl =
403 container_of(work, struct wl12xx, irq_work);
404 int ret;
405
406 mutex_lock(&wl->mutex);
407
408 wl12xx_debug(DEBUG_IRQ, "IRQ work");
409
410 if (wl->state == WL12XX_STATE_OFF)
411 goto out;
412
413 ret = wl12xx_ps_elp_wakeup(wl);
414 if (ret < 0)
415 goto out;
416
417 wl12xx_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1251_ACX_INTR_ALL);
418
419 intr = wl12xx_reg_read32(wl, ACX_REG_INTERRUPT_CLEAR);
420 wl12xx_debug(DEBUG_IRQ, "intr: 0x%x", intr);
421
422 if (wl->data_path) {
423 wl->rx_counter =
424 wl12xx_mem_read32(wl, wl->data_path->rx_control_addr);
425
426 /* We handle a frmware bug here */
427 switch ((wl->rx_counter - wl->rx_handled) & 0xf) {
428 case 0:
429 wl12xx_debug(DEBUG_IRQ, "RX: FW and host in sync");
430 intr &= ~WL1251_ACX_INTR_RX0_DATA;
431 intr &= ~WL1251_ACX_INTR_RX1_DATA;
432 break;
433 case 1:
434 wl12xx_debug(DEBUG_IRQ, "RX: FW +1");
435 intr |= WL1251_ACX_INTR_RX0_DATA;
436 intr &= ~WL1251_ACX_INTR_RX1_DATA;
437 break;
438 case 2:
439 wl12xx_debug(DEBUG_IRQ, "RX: FW +2");
440 intr |= WL1251_ACX_INTR_RX0_DATA;
441 intr |= WL1251_ACX_INTR_RX1_DATA;
442 break;
443 default:
444 wl12xx_warning("RX: FW and host out of sync: %d",
445 wl->rx_counter - wl->rx_handled);
446 break;
447 }
448
449 wl->rx_handled = wl->rx_counter;
450
451
452 wl12xx_debug(DEBUG_IRQ, "RX counter: %d", wl->rx_counter);
453 }
454
455 intr &= wl->intr_mask;
456
457 if (intr == 0) {
458 wl12xx_debug(DEBUG_IRQ, "INTR is 0");
459 wl12xx_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
460 ~(wl->intr_mask));
461
462 goto out_sleep;
463 }
464
465 if (intr & WL1251_ACX_INTR_RX0_DATA) {
466 wl12xx_debug(DEBUG_IRQ, "WL1251_ACX_INTR_RX0_DATA");
467 wl12xx_rx(wl);
468 }
469
470 if (intr & WL1251_ACX_INTR_RX1_DATA) {
471 wl12xx_debug(DEBUG_IRQ, "WL1251_ACX_INTR_RX1_DATA");
472 wl12xx_rx(wl);
473 }
474
475 if (intr & WL1251_ACX_INTR_TX_RESULT) {
476 wl12xx_debug(DEBUG_IRQ, "WL1251_ACX_INTR_TX_RESULT");
477 wl1251_tx_complete(wl);
478 }
479
480 if (intr & (WL1251_ACX_INTR_EVENT_A | WL1251_ACX_INTR_EVENT_B)) {
481 wl12xx_debug(DEBUG_IRQ, "WL1251_ACX_INTR_EVENT (0x%x)", intr);
482 if (intr & WL1251_ACX_INTR_EVENT_A)
483 wl12xx_event_handle(wl, 0);
484 else
485 wl12xx_event_handle(wl, 1);
486 }
487
488 if (intr & WL1251_ACX_INTR_INIT_COMPLETE)
489 wl12xx_debug(DEBUG_IRQ, "WL1251_ACX_INTR_INIT_COMPLETE");
490
491 wl12xx_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
492
493 out_sleep:
494 wl12xx_ps_elp_sleep(wl);
495
496 out:
497 mutex_unlock(&wl->mutex);
498 }
499
500 static int wl1251_hw_init_txq_fill(u8 qid,
501 struct acx_tx_queue_qos_config *config,
502 u32 num_blocks)
503 {
504 config->qid = qid;
505
506 switch (qid) {
507 case QOS_AC_BE:
508 config->high_threshold =
509 (QOS_TX_HIGH_BE_DEF * num_blocks) / 100;
510 config->low_threshold =
511 (QOS_TX_LOW_BE_DEF * num_blocks) / 100;
512 break;
513 case QOS_AC_BK:
514 config->high_threshold =
515 (QOS_TX_HIGH_BK_DEF * num_blocks) / 100;
516 config->low_threshold =
517 (QOS_TX_LOW_BK_DEF * num_blocks) / 100;
518 break;
519 case QOS_AC_VI:
520 config->high_threshold =
521 (QOS_TX_HIGH_VI_DEF * num_blocks) / 100;
522 config->low_threshold =
523 (QOS_TX_LOW_VI_DEF * num_blocks) / 100;
524 break;
525 case QOS_AC_VO:
526 config->high_threshold =
527 (QOS_TX_HIGH_VO_DEF * num_blocks) / 100;
528 config->low_threshold =
529 (QOS_TX_LOW_VO_DEF * num_blocks) / 100;
530 break;
531 default:
532 wl12xx_error("Invalid TX queue id: %d", qid);
533 return -EINVAL;
534 }
535
536 return 0;
537 }
538
539 static int wl1251_hw_init_tx_queue_config(struct wl12xx *wl)
540 {
541 struct acx_tx_queue_qos_config *config;
542 struct wl1251_acx_mem_map *wl_mem_map = wl->target_mem_map;
543 int ret, i;
544
545 wl12xx_debug(DEBUG_ACX, "acx tx queue config");
546
547 config = kzalloc(sizeof(*config), GFP_KERNEL);
548 if (!config) {
549 ret = -ENOMEM;
550 goto out;
551 }
552
553 for (i = 0; i < MAX_NUM_OF_AC; i++) {
554 ret = wl1251_hw_init_txq_fill(i, config,
555 wl_mem_map->num_tx_mem_blocks);
556 if (ret < 0)
557 goto out;
558
559 ret = wl12xx_cmd_configure(wl, ACX_TX_QUEUE_CFG,
560 config, sizeof(*config));
561 if (ret < 0)
562 goto out;
563 }
564
565 out:
566 kfree(config);
567 return ret;
568 }
569
570 static int wl1251_hw_init_data_path_config(struct wl12xx *wl)
571 {
572 int ret;
573
574 /* asking for the data path parameters */
575 wl->data_path = kzalloc(sizeof(struct acx_data_path_params_resp),
576 GFP_KERNEL);
577 if (!wl->data_path) {
578 wl12xx_error("Couldnt allocate data path parameters");
579 return -ENOMEM;
580 }
581
582 ret = wl12xx_acx_data_path_params(wl, wl->data_path);
583 if (ret < 0) {
584 kfree(wl->data_path);
585 wl->data_path = NULL;
586 return ret;
587 }
588
589 return 0;
590 }
591
592 static int wl1251_hw_init(struct wl12xx *wl)
593 {
594 struct wl1251_acx_mem_map *wl_mem_map;
595 int ret;
596
597 ret = wl12xx_hw_init_hwenc_config(wl);
598 if (ret < 0)
599 return ret;
600
601 /* Template settings */
602 ret = wl12xx_hw_init_templates_config(wl);
603 if (ret < 0)
604 return ret;
605
606 /* Default memory configuration */
607 ret = wl1251_hw_init_mem_config(wl);
608 if (ret < 0)
609 return ret;
610
611 /* Default data path configuration */
612 ret = wl1251_hw_init_data_path_config(wl);
613 if (ret < 0)
614 goto out_free_memmap;
615
616 /* RX config */
617 ret = wl12xx_hw_init_rx_config(wl,
618 RX_CFG_PROMISCUOUS | RX_CFG_TSF,
619 RX_FILTER_OPTION_DEF);
620 /* RX_CONFIG_OPTION_ANY_DST_ANY_BSS,
621 RX_FILTER_OPTION_FILTER_ALL); */
622 if (ret < 0)
623 goto out_free_data_path;
624
625 /* TX queues config */
626 ret = wl1251_hw_init_tx_queue_config(wl);
627 if (ret < 0)
628 goto out_free_data_path;
629
630 /* PHY layer config */
631 ret = wl12xx_hw_init_phy_config(wl);
632 if (ret < 0)
633 goto out_free_data_path;
634
635 /* Beacon filtering */
636 ret = wl12xx_hw_init_beacon_filter(wl);
637 if (ret < 0)
638 goto out_free_data_path;
639
640 /* Bluetooth WLAN coexistence */
641 ret = wl12xx_hw_init_pta(wl);
642 if (ret < 0)
643 goto out_free_data_path;
644
645 /* Energy detection */
646 ret = wl12xx_hw_init_energy_detection(wl);
647 if (ret < 0)
648 goto out_free_data_path;
649
650 /* Beacons and boradcast settings */
651 ret = wl12xx_hw_init_beacon_broadcast(wl);
652 if (ret < 0)
653 goto out_free_data_path;
654
655 /* Enable data path */
656 ret = wl12xx_cmd_data_path(wl, wl->channel, 1);
657 if (ret < 0)
658 goto out_free_data_path;
659
660 /* Default power state */
661 ret = wl12xx_hw_init_power_auth(wl);
662 if (ret < 0)
663 goto out_free_data_path;
664
665 wl_mem_map = wl->target_mem_map;
666 wl12xx_info("%d tx blocks at 0x%x, %d rx blocks at 0x%x",
667 wl_mem_map->num_tx_mem_blocks,
668 wl->data_path->tx_control_addr,
669 wl_mem_map->num_rx_mem_blocks,
670 wl->data_path->rx_control_addr);
671
672 return 0;
673
674 out_free_data_path:
675 kfree(wl->data_path);
676
677 out_free_memmap:
678 kfree(wl->target_mem_map);
679
680 return ret;
681 }
682
683 static int wl1251_plt_init(struct wl12xx *wl)
684 {
685 int ret;
686
687 ret = wl1251_hw_init_mem_config(wl);
688 if (ret < 0)
689 return ret;
690
691 ret = wl12xx_cmd_data_path(wl, wl->channel, 1);
692 if (ret < 0)
693 return ret;
694
695 return 0;
696 }
697
698 void wl1251_setup(struct wl12xx *wl)
699 {
700 /* FIXME: Is it better to use strncpy here or is this ok? */
701 wl->chip.fw_filename = WL1251_FW_NAME;
702 wl->chip.nvs_filename = WL1251_NVS_NAME;
703
704 /* Now we know what chip we're using, so adjust the power on sleep
705 * time accordingly */
706 wl->chip.power_on_sleep = WL1251_POWER_ON_SLEEP;
707
708 wl->chip.intr_cmd_complete = WL1251_ACX_INTR_CMD_COMPLETE;
709 wl->chip.intr_init_complete = WL1251_ACX_INTR_INIT_COMPLETE;
710
711 wl->chip.op_upload_nvs = wl1251_upload_nvs;
712 wl->chip.op_upload_fw = wl1251_upload_firmware;
713 wl->chip.op_boot = wl1251_boot;
714 wl->chip.op_set_ecpu_ctrl = wl1251_set_ecpu_ctrl;
715 wl->chip.op_target_enable_interrupts = wl1251_target_enable_interrupts;
716 wl->chip.op_hw_init = wl1251_hw_init;
717 wl->chip.op_plt_init = wl1251_plt_init;
718 wl->chip.op_fw_version = wl1251_fw_version;
719 wl->chip.op_tx_flush = wl1251_tx_flush;
720 wl->chip.op_cmd_join = wl1251_cmd_join;
721
722 wl->chip.p_table = wl1251_part_table;
723 wl->chip.acx_reg_table = wl1251_acx_reg_table;
724
725 INIT_WORK(&wl->irq_work, wl1251_irq_work);
726 INIT_WORK(&wl->tx_work, wl1251_tx_work);
727
728 }
Support for the Chinese Samsung S3C2440 based development boards