arch/mips/txx9/rbtx4938/setup.c

   1 /*
   2  * Setup pointers to hardware-dependent routines.
   3  * Copyright (C) 2000-2001 Toshiba Corporation
   4  *
   5  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   6  * terms of the GNU General Public License version 2. This program is
   7  * licensed "as is" without any warranty of any kind, whether express
   8  * or implied.
   9  *
  10  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  11  */
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/ioport.h>
  15 #include <linux/delay.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/gpio.h>
  18
  19 #include <asm/reboot.h>
  20 #include <asm/io.h>
  21 #include <asm/txx9/generic.h>
  22 #include <asm/txx9/pci.h>
  23 #include <asm/txx9/rbtx4938.h>
  24 #include <linux/spi/spi.h>
  25 #include <asm/txx9/spi.h>
  26 #include <asm/txx9pio.h>
  27
  28 static void rbtx4938_machine_restart(char *command)
  29 {
  30         local_irq_disable();
  31         writeb(1, rbtx4938_softresetlock_addr);
  32         writeb(1, rbtx4938_sfvol_addr);
  33         writeb(1, rbtx4938_softreset_addr);
  34         /* fallback */
  35         (*_machine_halt)();
  36 }
  37
  38 static void __init rbtx4938_pci_setup(void)
  39 {
  40 #ifdef CONFIG_PCI
  41         int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
  42         struct pci_controller *c = &txx9_primary_pcic;
  43
  44         register_pci_controller(c);
  45
  46         if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
  47                 txx9_pci_option =
  48                         (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
  49                         TXX9_PCI_OPT_CLK_66; /* already configured */
  50
  51         /* Reset PCI Bus */
  52         writeb(0, rbtx4938_pcireset_addr);
  53         /* Reset PCIC */
  54         txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  55         if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
  56             TXX9_PCI_OPT_CLK_66)
  57                 tx4938_pciclk66_setup();
  58         mdelay(10);
  59         /* clear PCIC reset */
  60         txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  61         writeb(1, rbtx4938_pcireset_addr);
  62         iob();
  63
  64         tx4938_report_pciclk();
  65         tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
  66         if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
  67             TXX9_PCI_OPT_CLK_AUTO &&
  68             txx9_pci66_check(c, 0, 0)) {
  69                 /* Reset PCI Bus */
  70                 writeb(0, rbtx4938_pcireset_addr);
  71                 /* Reset PCIC */
  72                 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  73                 tx4938_pciclk66_setup();
  74                 mdelay(10);
  75                 /* clear PCIC reset */
  76                 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  77                 writeb(1, rbtx4938_pcireset_addr);
  78                 iob();
  79                 /* Reinitialize PCIC */
  80                 tx4938_report_pciclk();
  81                 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
  82         }
  83
  84         if (__raw_readq(&tx4938_ccfgptr->pcfg) &
  85             (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
  86                 /* Reset PCIC1 */
  87                 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
  88                 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
  89                 if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
  90                       & TX4938_CCFG_PCI1DMD))
  91                         tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
  92                 mdelay(10);
  93                 /* clear PCIC1 reset */
  94                 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
  95                 tx4938_report_pci1clk();
  96
  97                 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
  98                 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
  99                 register_pci_controller(c);
 100                 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
 101         }
 102         tx4938_setup_pcierr_irq();
 103 #endif /* CONFIG_PCI */
 104 }
 105
 106 /* SPI support */
 107
 108 /* chip select for SPI devices */
 109 #define SEEPROM1_CS     7       /* PIO7 */
 110 #define SEEPROM2_CS     0       /* IOC */
 111 #define SEEPROM3_CS     1       /* IOC */
 112 #define SRTC_CS 2       /* IOC */
 113
 114 static int __init rbtx4938_ethaddr_init(void)
 115 {
 116 #ifdef CONFIG_PCI
 117         unsigned char dat[17];
 118         unsigned char sum;
 119         int i;
 120
 121         /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
 122         if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
 123                 printk(KERN_ERR "seeprom: read error.\n");
 124                 return -ENODEV;
 125         } else {
 126                 if (strcmp(dat, "MAC") != 0)
 127                         printk(KERN_WARNING "seeprom: bad signature.\n");
 128                 for (i = 0, sum = 0; i < sizeof(dat); i++)
 129                         sum += dat[i];
 130                 if (sum)
 131                         printk(KERN_WARNING "seeprom: bad checksum.\n");
 132         }
 133         tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
 134 #endif /* CONFIG_PCI */
 135         return 0;
 136 }
 137
 138 static void __init rbtx4938_spi_setup(void)
 139 {
 140         /* set SPI_SEL */
 141         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
 142 }
 143
 144 static struct resource rbtx4938_fpga_resource;
 145
 146 static void __init rbtx4938_time_init(void)
 147 {
 148         tx4938_time_init(0);
 149 }
 150
 151 static void __init rbtx4938_mem_setup(void)
 152 {
 153         unsigned long long pcfg;
 154         char *argptr;
 155
 156         if (txx9_master_clock == 0)
 157                 txx9_master_clock = 25000000; /* 25MHz */
 158
 159         tx4938_setup();
 160
 161 #ifdef CONFIG_PCI
 162         txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
 163         txx9_board_pcibios_setup = tx4927_pcibios_setup;
 164 #else
 165         set_io_port_base(RBTX4938_ETHER_BASE);
 166 #endif
 167
 168         tx4938_sio_init(7372800, 0);
 169 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 170         argptr = prom_getcmdline();
 171         if (!strstr(argptr, "console="))
 172                 strcat(argptr, " console=ttyS0,38400");
 173 #endif
 174
 175 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
 176         printk(KERN_INFO "PIOSEL: disabling both ata and nand selection\n");
 177         txx9_clear64(&tx4938_ccfgptr->pcfg,
 178                      TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
 179 #endif
 180
 181 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
 182         printk(KERN_INFO "PIOSEL: enabling nand selection\n");
 183         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
 184         txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
 185 #endif
 186
 187 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
 188         printk(KERN_INFO "PIOSEL: enabling ata selection\n");
 189         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
 190         txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
 191 #endif
 192
 193         rbtx4938_spi_setup();
 194         pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);    /* updated */
 195         /* fixup piosel */
 196         if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
 197             TX4938_PCFG_ATA_SEL)
 198                 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
 199                        rbtx4938_piosel_addr);
 200         else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
 201                  TX4938_PCFG_NDF_SEL)
 202                 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
 203                        rbtx4938_piosel_addr);
 204         else
 205                 writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
 206                        rbtx4938_piosel_addr);
 207
 208         rbtx4938_fpga_resource.name = "FPGA Registers";
 209         rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
 210         rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
 211         rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 212         if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
 213                 printk(KERN_ERR "request resource for fpga failed\n");
 214
 215         _machine_restart = rbtx4938_machine_restart;
 216
 217         writeb(0xff, rbtx4938_led_addr);
 218         printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
 219                readb(rbtx4938_fpga_rev_addr),
 220                readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
 221 }
 222
 223 static void __init rbtx4938_ne_init(void)
 224 {
 225         struct resource res[] = {
 226                 {
 227                         .start  = RBTX4938_RTL_8019_BASE,
 228                         .end    = RBTX4938_RTL_8019_BASE + 0x20 - 1,
 229                         .flags  = IORESOURCE_IO,
 230                 }, {
 231                         .start  = RBTX4938_RTL_8019_IRQ,
 232                         .flags  = IORESOURCE_IRQ,
 233                 }
 234         };
 235         platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
 236 }
 237
 238 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
 239
 240 static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
 241                                   int value)
 242 {
 243         u8 val;
 244         unsigned long flags;
 245         spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
 246         val = readb(rbtx4938_spics_addr);
 247         if (value)
 248                 val |= 1 << offset;
 249         else
 250                 val &= ~(1 << offset);
 251         writeb(val, rbtx4938_spics_addr);
 252         mmiowb();
 253         spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
 254 }
 255
 256 static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
 257                                      unsigned int offset, int value)
 258 {
 259         rbtx4938_spi_gpio_set(chip, offset, value);
 260         return 0;
 261 }
 262
 263 static struct gpio_chip rbtx4938_spi_gpio_chip = {
 264         .set = rbtx4938_spi_gpio_set,
 265         .direction_output = rbtx4938_spi_gpio_dir_out,
 266         .label = "RBTX4938-SPICS",
 267         .base = 16,
 268         .ngpio = 3,
 269 };
 270
 271 static int __init rbtx4938_spi_init(void)
 272 {
 273         struct spi_board_info srtc_info = {
 274                 .modalias = "rtc-rs5c348",
 275                 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
 276                 .bus_num = 0,
 277                 .chip_select = 16 + SRTC_CS,
 278                 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS  */
 279                 .mode = SPI_MODE_1 | SPI_CS_HIGH,
 280         };
 281         spi_register_board_info(&srtc_info, 1);
 282         spi_eeprom_register(SEEPROM1_CS);
 283         spi_eeprom_register(16 + SEEPROM2_CS);
 284         spi_eeprom_register(16 + SEEPROM3_CS);
 285         gpio_request(16 + SRTC_CS, "rtc-rs5c348");
 286         gpio_direction_output(16 + SRTC_CS, 0);
 287         gpio_request(SEEPROM1_CS, "seeprom1");
 288         gpio_direction_output(SEEPROM1_CS, 1);
 289         gpio_request(16 + SEEPROM2_CS, "seeprom2");
 290         gpio_direction_output(16 + SEEPROM2_CS, 1);
 291         gpio_request(16 + SEEPROM3_CS, "seeprom3");
 292         gpio_direction_output(16 + SEEPROM3_CS, 1);
 293         tx4938_spi_init(0);
 294         return 0;
 295 }
 296
 297 static void __init rbtx4938_arch_init(void)
 298 {
 299         gpiochip_add(&rbtx4938_spi_gpio_chip);
 300         rbtx4938_pci_setup();
 301         rbtx4938_spi_init();
 302 }
 303
 304 static void __init rbtx4938_device_init(void)
 305 {
 306         rbtx4938_ethaddr_init();
 307         rbtx4938_ne_init();
 308         tx4938_wdt_init();
 309 }
 310
 311 struct txx9_board_vec rbtx4938_vec __initdata = {
 312         .system = "Toshiba RBTX4938",
 313         .prom_init = rbtx4938_prom_init,
 314         .mem_setup = rbtx4938_mem_setup,
 315         .irq_setup = rbtx4938_irq_setup,
 316         .time_init = rbtx4938_time_init,
 317         .device_init = rbtx4938_device_init,
 318         .arch_init = rbtx4938_arch_init,
 319 #ifdef CONFIG_PCI
 320         .pci_map_irq = rbtx4938_pci_map_irq,
 321 #endif
 322 };