1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/sysrq.h>
34 #include "intel_drv.h"
36 #define MAX_NOPID ((u32)~0)
39 * Interrupts that are always left unmasked.
41 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
42 * we leave them always unmasked in IMR and then control enabling them through
45 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
46 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
47 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
48 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
50 /** Interrupts that we mask and unmask at runtime. */
51 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
53 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
54 PIPE_VBLANK_INTERRUPT_STATUS)
56 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
57 PIPE_VBLANK_INTERRUPT_ENABLE)
59 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
60 DRM_I915_VBLANK_PIPE_B)
63 igdng_enable_graphics_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
65 if ((dev_priv
->gt_irq_mask_reg
& mask
) != 0) {
66 dev_priv
->gt_irq_mask_reg
&= ~mask
;
67 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
68 (void) I915_READ(GTIMR
);
73 igdng_disable_graphics_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
75 if ((dev_priv
->gt_irq_mask_reg
& mask
) != mask
) {
76 dev_priv
->gt_irq_mask_reg
|= mask
;
77 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
78 (void) I915_READ(GTIMR
);
82 /* For display hotplug interrupt */
84 igdng_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
87 dev_priv
->irq_mask_reg
&= ~mask
;
88 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
89 (void) I915_READ(DEIMR
);
94 igdng_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
96 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
97 dev_priv
->irq_mask_reg
|= mask
;
98 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
99 (void) I915_READ(DEIMR
);
104 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
106 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
107 dev_priv
->irq_mask_reg
&= ~mask
;
108 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
109 (void) I915_READ(IMR
);
114 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
116 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
117 dev_priv
->irq_mask_reg
|= mask
;
118 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
119 (void) I915_READ(IMR
);
124 i915_pipestat(int pipe
)
134 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
136 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
137 u32 reg
= i915_pipestat(pipe
);
139 dev_priv
->pipestat
[pipe
] |= mask
;
140 /* Enable the interrupt, clear any pending status */
141 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
] | (mask
>> 16));
142 (void) I915_READ(reg
);
147 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
149 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
150 u32 reg
= i915_pipestat(pipe
);
152 dev_priv
->pipestat
[pipe
] &= ~mask
;
153 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
]);
154 (void) I915_READ(reg
);
159 * i915_pipe_enabled - check if a pipe is enabled
161 * @pipe: pipe to check
163 * Reading certain registers when the pipe is disabled can hang the chip.
164 * Use this routine to make sure the PLL is running and the pipe is active
165 * before reading such registers if unsure.
168 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
170 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
171 unsigned long pipeconf
= pipe
? PIPEBCONF
: PIPEACONF
;
173 if (I915_READ(pipeconf
) & PIPEACONF_ENABLE
)
179 /* Called from drm generic code, passed a 'crtc', which
180 * we use as a pipe index
182 u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
184 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
185 unsigned long high_frame
;
186 unsigned long low_frame
;
187 u32 high1
, high2
, low
, count
;
189 high_frame
= pipe
? PIPEBFRAMEHIGH
: PIPEAFRAMEHIGH
;
190 low_frame
= pipe
? PIPEBFRAMEPIXEL
: PIPEAFRAMEPIXEL
;
192 if (!i915_pipe_enabled(dev
, pipe
)) {
193 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe
);
198 * High & low register fields aren't synchronized, so make sure
199 * we get a low value that's stable across two reads of the high
203 high1
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
204 PIPE_FRAME_HIGH_SHIFT
);
205 low
= ((I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
) >>
206 PIPE_FRAME_LOW_SHIFT
);
207 high2
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
208 PIPE_FRAME_HIGH_SHIFT
);
209 } while (high1
!= high2
);
211 count
= (high1
<< 8) | low
;
216 u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
218 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
219 int reg
= pipe
? PIPEB_FRMCOUNT_GM45
: PIPEA_FRMCOUNT_GM45
;
221 if (!i915_pipe_enabled(dev
, pipe
)) {
222 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe
);
226 return I915_READ(reg
);
230 * Handle hotplug events outside the interrupt handler proper.
232 static void i915_hotplug_work_func(struct work_struct
*work
)
234 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
236 struct drm_device
*dev
= dev_priv
->dev
;
237 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
238 struct drm_connector
*connector
;
240 if (mode_config
->num_connector
) {
241 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
242 struct intel_output
*intel_output
= to_intel_output(connector
);
244 if (intel_output
->hot_plug
)
245 (*intel_output
->hot_plug
) (intel_output
);
248 /* Just fire off a uevent and let userspace tell us what to do */
249 drm_sysfs_hotplug_event(dev
);
252 irqreturn_t
igdng_irq_handler(struct drm_device
*dev
)
254 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
257 u32 new_de_iir
, new_gt_iir
;
258 struct drm_i915_master_private
*master_priv
;
260 de_iir
= I915_READ(DEIIR
);
261 gt_iir
= I915_READ(GTIIR
);
264 if (de_iir
== 0 && gt_iir
== 0)
269 I915_WRITE(DEIIR
, de_iir
);
270 new_de_iir
= I915_READ(DEIIR
);
271 I915_WRITE(GTIIR
, gt_iir
);
272 new_gt_iir
= I915_READ(GTIIR
);
274 if (dev
->primary
->master
) {
275 master_priv
= dev
->primary
->master
->driver_priv
;
276 if (master_priv
->sarea_priv
)
277 master_priv
->sarea_priv
->last_dispatch
=
278 READ_BREADCRUMB(dev_priv
);
281 if (gt_iir
& GT_USER_INTERRUPT
) {
282 dev_priv
->mm
.irq_gem_seqno
= i915_get_gem_seqno(dev
);
283 DRM_WAKEUP(&dev_priv
->irq_queue
);
293 static void i915_capture_error_state(struct drm_device
*dev
)
295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
296 struct drm_i915_error_state
*error
;
299 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
300 if (dev_priv
->first_error
)
303 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
305 DRM_DEBUG("out ot memory, not capturing error state\n");
309 error
->eir
= I915_READ(EIR
);
310 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
311 error
->pipeastat
= I915_READ(PIPEASTAT
);
312 error
->pipebstat
= I915_READ(PIPEBSTAT
);
313 error
->instpm
= I915_READ(INSTPM
);
314 if (!IS_I965G(dev
)) {
315 error
->ipeir
= I915_READ(IPEIR
);
316 error
->ipehr
= I915_READ(IPEHR
);
317 error
->instdone
= I915_READ(INSTDONE
);
318 error
->acthd
= I915_READ(ACTHD
);
320 error
->ipeir
= I915_READ(IPEIR_I965
);
321 error
->ipehr
= I915_READ(IPEHR_I965
);
322 error
->instdone
= I915_READ(INSTDONE_I965
);
323 error
->instps
= I915_READ(INSTPS
);
324 error
->instdone1
= I915_READ(INSTDONE1
);
325 error
->acthd
= I915_READ(ACTHD_I965
);
328 dev_priv
->first_error
= error
;
331 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
334 irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
)
336 struct drm_device
*dev
= (struct drm_device
*) arg
;
337 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
338 struct drm_i915_master_private
*master_priv
;
340 u32 pipea_stats
, pipeb_stats
;
344 unsigned long irqflags
;
348 atomic_inc(&dev_priv
->irq_received
);
351 return igdng_irq_handler(dev
);
353 iir
= I915_READ(IIR
);
356 vblank_status
= I915_START_VBLANK_INTERRUPT_STATUS
;
357 vblank_enable
= PIPE_START_VBLANK_INTERRUPT_ENABLE
;
359 vblank_status
= I915_VBLANK_INTERRUPT_STATUS
;
360 vblank_enable
= I915_VBLANK_INTERRUPT_ENABLE
;
364 irq_received
= iir
!= 0;
366 /* Can't rely on pipestat interrupt bit in iir as it might
367 * have been cleared after the pipestat interrupt was received.
368 * It doesn't set the bit in iir again, but it still produces
369 * interrupts (for non-MSI).
371 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
372 pipea_stats
= I915_READ(PIPEASTAT
);
373 pipeb_stats
= I915_READ(PIPEBSTAT
);
376 * Clear the PIPE(A|B)STAT regs before the IIR
378 if (pipea_stats
& 0x8000ffff) {
379 if (pipea_stats
& PIPE_FIFO_UNDERRUN_STATUS
)
380 DRM_DEBUG("pipe a underrun\n");
381 I915_WRITE(PIPEASTAT
, pipea_stats
);
385 if (pipeb_stats
& 0x8000ffff) {
386 if (pipeb_stats
& PIPE_FIFO_UNDERRUN_STATUS
)
387 DRM_DEBUG("pipe b underrun\n");
388 I915_WRITE(PIPEBSTAT
, pipeb_stats
);
391 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
398 /* Consume port. Then clear IIR or we'll miss events */
399 if ((I915_HAS_HOTPLUG(dev
)) &&
400 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
401 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
403 DRM_DEBUG("hotplug event received, stat 0x%08x\n",
405 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
406 schedule_work(&dev_priv
->hotplug_work
);
408 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
409 I915_READ(PORT_HOTPLUG_STAT
);
412 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
) {
413 u32 eir
= I915_READ(EIR
);
415 i915_capture_error_state(dev
);
417 printk(KERN_ERR
"render error detected, EIR: 0x%08x\n",
419 if (eir
& I915_ERROR_PAGE_TABLE
) {
420 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
421 printk(KERN_ERR
"page table error\n");
422 printk(KERN_ERR
" PGTBL_ER: 0x%08x\n",
424 I915_WRITE(PGTBL_ER
, pgtbl_err
);
425 (void)I915_READ(PGTBL_ER
);
427 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
428 printk(KERN_ERR
"memory refresh error\n");
429 printk(KERN_ERR
"PIPEASTAT: 0x%08x\n",
431 printk(KERN_ERR
"PIPEBSTAT: 0x%08x\n",
433 /* pipestat has already been acked */
435 if (eir
& I915_ERROR_INSTRUCTION
) {
436 printk(KERN_ERR
"instruction error\n");
437 printk(KERN_ERR
" INSTPM: 0x%08x\n",
439 if (!IS_I965G(dev
)) {
440 u32 ipeir
= I915_READ(IPEIR
);
442 printk(KERN_ERR
" IPEIR: 0x%08x\n",
444 printk(KERN_ERR
" IPEHR: 0x%08x\n",
446 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
447 I915_READ(INSTDONE
));
448 printk(KERN_ERR
" ACTHD: 0x%08x\n",
450 I915_WRITE(IPEIR
, ipeir
);
451 (void)I915_READ(IPEIR
);
453 u32 ipeir
= I915_READ(IPEIR_I965
);
455 printk(KERN_ERR
" IPEIR: 0x%08x\n",
456 I915_READ(IPEIR_I965
));
457 printk(KERN_ERR
" IPEHR: 0x%08x\n",
458 I915_READ(IPEHR_I965
));
459 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
460 I915_READ(INSTDONE_I965
));
461 printk(KERN_ERR
" INSTPS: 0x%08x\n",
463 printk(KERN_ERR
" INSTDONE1: 0x%08x\n",
464 I915_READ(INSTDONE1
));
465 printk(KERN_ERR
" ACTHD: 0x%08x\n",
466 I915_READ(ACTHD_I965
));
467 I915_WRITE(IPEIR_I965
, ipeir
);
468 (void)I915_READ(IPEIR_I965
);
472 I915_WRITE(EIR
, eir
);
473 (void)I915_READ(EIR
);
474 eir
= I915_READ(EIR
);
477 * some errors might have become stuck,
480 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
481 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
482 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
486 I915_WRITE(IIR
, iir
);
487 new_iir
= I915_READ(IIR
); /* Flush posted writes */
489 if (dev
->primary
->master
) {
490 master_priv
= dev
->primary
->master
->driver_priv
;
491 if (master_priv
->sarea_priv
)
492 master_priv
->sarea_priv
->last_dispatch
=
493 READ_BREADCRUMB(dev_priv
);
496 if (iir
& I915_USER_INTERRUPT
) {
497 dev_priv
->mm
.irq_gem_seqno
= i915_get_gem_seqno(dev
);
498 DRM_WAKEUP(&dev_priv
->irq_queue
);
501 if (pipea_stats
& vblank_status
) {
503 drm_handle_vblank(dev
, 0);
506 if (pipeb_stats
& vblank_status
) {
508 drm_handle_vblank(dev
, 1);
511 if ((pipeb_stats
& I915_LEGACY_BLC_EVENT_STATUS
) ||
512 (iir
& I915_ASLE_INTERRUPT
))
513 opregion_asle_intr(dev
);
515 /* With MSI, interrupts are only generated when iir
516 * transitions from zero to nonzero. If another bit got
517 * set while we were handling the existing iir bits, then
518 * we would never get another interrupt.
520 * This is fine on non-MSI as well, as if we hit this path
521 * we avoid exiting the interrupt handler only to generate
524 * Note that for MSI this could cause a stray interrupt report
525 * if an interrupt landed in the time between writing IIR and
526 * the posting read. This should be rare enough to never
527 * trigger the 99% of 100,000 interrupts test for disabling
536 static int i915_emit_irq(struct drm_device
* dev
)
538 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
539 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
542 i915_kernel_lost_context(dev
);
547 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
548 dev_priv
->counter
= 1;
549 if (master_priv
->sarea_priv
)
550 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
553 OUT_RING(MI_STORE_DWORD_INDEX
);
554 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
555 OUT_RING(dev_priv
->counter
);
556 OUT_RING(MI_USER_INTERRUPT
);
559 return dev_priv
->counter
;
562 void i915_user_irq_get(struct drm_device
*dev
)
564 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
565 unsigned long irqflags
;
567 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
568 if (dev
->irq_enabled
&& (++dev_priv
->user_irq_refcount
== 1)) {
570 igdng_enable_graphics_irq(dev_priv
, GT_USER_INTERRUPT
);
572 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
574 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
577 void i915_user_irq_put(struct drm_device
*dev
)
579 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
580 unsigned long irqflags
;
582 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
583 BUG_ON(dev
->irq_enabled
&& dev_priv
->user_irq_refcount
<= 0);
584 if (dev
->irq_enabled
&& (--dev_priv
->user_irq_refcount
== 0)) {
586 igdng_disable_graphics_irq(dev_priv
, GT_USER_INTERRUPT
);
588 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
590 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
593 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
595 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
596 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
599 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr
,
600 READ_BREADCRUMB(dev_priv
));
602 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
603 if (master_priv
->sarea_priv
)
604 master_priv
->sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
608 if (master_priv
->sarea_priv
)
609 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
611 i915_user_irq_get(dev
);
612 DRM_WAIT_ON(ret
, dev_priv
->irq_queue
, 3 * DRM_HZ
,
613 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
614 i915_user_irq_put(dev
);
617 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
618 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->counter
);
624 /* Needs the lock as it touches the ring.
626 int i915_irq_emit(struct drm_device
*dev
, void *data
,
627 struct drm_file
*file_priv
)
629 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
630 drm_i915_irq_emit_t
*emit
= data
;
633 if (!dev_priv
|| !dev_priv
->ring
.virtual_start
) {
634 DRM_ERROR("called with no initialization\n");
638 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
640 mutex_lock(&dev
->struct_mutex
);
641 result
= i915_emit_irq(dev
);
642 mutex_unlock(&dev
->struct_mutex
);
644 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
645 DRM_ERROR("copy_to_user\n");
652 /* Doesn't need the hardware lock.
654 int i915_irq_wait(struct drm_device
*dev
, void *data
,
655 struct drm_file
*file_priv
)
657 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
658 drm_i915_irq_wait_t
*irqwait
= data
;
661 DRM_ERROR("called with no initialization\n");
665 return i915_wait_irq(dev
, irqwait
->irq_seq
);
668 /* Called from drm generic code, passed 'crtc' which
669 * we use as a pipe index
671 int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
673 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
674 unsigned long irqflags
;
675 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
678 pipeconf
= I915_READ(pipeconf_reg
);
679 if (!(pipeconf
& PIPEACONF_ENABLE
))
685 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
687 i915_enable_pipestat(dev_priv
, pipe
,
688 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
690 i915_enable_pipestat(dev_priv
, pipe
,
691 PIPE_VBLANK_INTERRUPT_ENABLE
);
692 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
696 /* Called from drm generic code, passed 'crtc' which
697 * we use as a pipe index
699 void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
701 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
702 unsigned long irqflags
;
707 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
708 i915_disable_pipestat(dev_priv
, pipe
,
709 PIPE_VBLANK_INTERRUPT_ENABLE
|
710 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
711 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
714 void i915_enable_interrupt (struct drm_device
*dev
)
716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
719 opregion_enable_asle(dev
);
720 dev_priv
->irq_enabled
= 1;
724 /* Set the vblank monitor pipe
726 int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
727 struct drm_file
*file_priv
)
729 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
732 DRM_ERROR("called with no initialization\n");
739 int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
740 struct drm_file
*file_priv
)
742 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
743 drm_i915_vblank_pipe_t
*pipe
= data
;
746 DRM_ERROR("called with no initialization\n");
750 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
756 * Schedule buffer swap at given vertical blank.
758 int i915_vblank_swap(struct drm_device
*dev
, void *data
,
759 struct drm_file
*file_priv
)
761 /* The delayed swap mechanism was fundamentally racy, and has been
762 * removed. The model was that the client requested a delayed flip/swap
763 * from the kernel, then waited for vblank before continuing to perform
764 * rendering. The problem was that the kernel might wake the client
765 * up before it dispatched the vblank swap (since the lock has to be
766 * held while touching the ringbuffer), in which case the client would
767 * clear and start the next frame before the swap occurred, and
768 * flicker would occur in addition to likely missing the vblank.
770 * In the absence of this ioctl, userland falls back to a correct path
771 * of waiting for a vblank, then dispatching the swap on its own.
772 * Context switching to userland and back is plenty fast enough for
773 * meeting the requirements of vblank swapping.
780 static void igdng_irq_preinstall(struct drm_device
*dev
)
782 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
784 I915_WRITE(HWSTAM
, 0xeffe);
786 /* XXX hotplug from PCH */
788 I915_WRITE(DEIMR
, 0xffffffff);
789 I915_WRITE(DEIER
, 0x0);
790 (void) I915_READ(DEIER
);
793 I915_WRITE(GTIMR
, 0xffffffff);
794 I915_WRITE(GTIER
, 0x0);
795 (void) I915_READ(GTIER
);
798 static int igdng_irq_postinstall(struct drm_device
*dev
)
800 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
801 /* enable kind of interrupts always enabled */
802 u32 display_mask
= DE_MASTER_IRQ_CONTROL
/*| DE_PCH_EVENT */;
803 u32 render_mask
= GT_USER_INTERRUPT
;
805 dev_priv
->irq_mask_reg
= ~display_mask
;
806 dev_priv
->de_irq_enable_reg
= display_mask
;
808 /* should always can generate irq */
809 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
810 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
811 I915_WRITE(DEIER
, dev_priv
->de_irq_enable_reg
);
812 (void) I915_READ(DEIER
);
814 /* user interrupt should be enabled, but masked initial */
815 dev_priv
->gt_irq_mask_reg
= 0xffffffff;
816 dev_priv
->gt_irq_enable_reg
= render_mask
;
818 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
819 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
820 I915_WRITE(GTIER
, dev_priv
->gt_irq_enable_reg
);
821 (void) I915_READ(GTIER
);
826 void i915_driver_irq_preinstall(struct drm_device
* dev
)
828 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
830 atomic_set(&dev_priv
->irq_received
, 0);
832 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
835 igdng_irq_preinstall(dev
);
839 if (I915_HAS_HOTPLUG(dev
)) {
840 I915_WRITE(PORT_HOTPLUG_EN
, 0);
841 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
844 I915_WRITE(HWSTAM
, 0xeffe);
845 I915_WRITE(PIPEASTAT
, 0);
846 I915_WRITE(PIPEBSTAT
, 0);
847 I915_WRITE(IMR
, 0xffffffff);
848 I915_WRITE(IER
, 0x0);
849 (void) I915_READ(IER
);
852 int i915_driver_irq_postinstall(struct drm_device
*dev
)
854 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
855 u32 enable_mask
= I915_INTERRUPT_ENABLE_FIX
| I915_INTERRUPT_ENABLE_VAR
;
858 DRM_INIT_WAITQUEUE(&dev_priv
->irq_queue
);
860 dev_priv
->vblank_pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
863 return igdng_irq_postinstall(dev
);
865 /* Unmask the interrupts that we always want on. */
866 dev_priv
->irq_mask_reg
= ~I915_INTERRUPT_ENABLE_FIX
;
868 dev_priv
->pipestat
[0] = 0;
869 dev_priv
->pipestat
[1] = 0;
871 if (I915_HAS_HOTPLUG(dev
)) {
872 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
874 /* Leave other bits alone */
875 hotplug_en
|= HOTPLUG_EN_MASK
;
876 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
878 dev_priv
->hotplug_supported_mask
= CRT_HOTPLUG_INT_STATUS
|
879 TV_HOTPLUG_INT_STATUS
| SDVOC_HOTPLUG_INT_STATUS
|
880 SDVOB_HOTPLUG_INT_STATUS
;
882 dev_priv
->hotplug_supported_mask
|=
883 HDMIB_HOTPLUG_INT_STATUS
|
884 HDMIC_HOTPLUG_INT_STATUS
|
885 HDMID_HOTPLUG_INT_STATUS
;
887 /* Enable in IER... */
888 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
889 /* and unmask in IMR */
890 i915_enable_irq(dev_priv
, I915_DISPLAY_PORT_INTERRUPT
);
894 * Enable some error detection, note the instruction error mask
895 * bit is reserved, so we leave it masked.
898 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
899 GM45_ERROR_MEM_PRIV
|
901 I915_ERROR_MEMORY_REFRESH
);
903 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
904 I915_ERROR_MEMORY_REFRESH
);
906 I915_WRITE(EMR
, error_mask
);
908 /* Disable pipe interrupt enables, clear pending pipe status */
909 I915_WRITE(PIPEASTAT
, I915_READ(PIPEASTAT
) & 0x8000ffff);
910 I915_WRITE(PIPEBSTAT
, I915_READ(PIPEBSTAT
) & 0x8000ffff);
911 /* Clear pending interrupt status */
912 I915_WRITE(IIR
, I915_READ(IIR
));
914 I915_WRITE(IER
, enable_mask
);
915 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
916 (void) I915_READ(IER
);
918 opregion_enable_asle(dev
);
923 static void igdng_irq_uninstall(struct drm_device
*dev
)
925 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
926 I915_WRITE(HWSTAM
, 0xffffffff);
928 I915_WRITE(DEIMR
, 0xffffffff);
929 I915_WRITE(DEIER
, 0x0);
930 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
932 I915_WRITE(GTIMR
, 0xffffffff);
933 I915_WRITE(GTIER
, 0x0);
934 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
937 void i915_driver_irq_uninstall(struct drm_device
* dev
)
939 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
944 dev_priv
->vblank_pipe
= 0;
947 igdng_irq_uninstall(dev
);
951 if (I915_HAS_HOTPLUG(dev
)) {
952 I915_WRITE(PORT_HOTPLUG_EN
, 0);
953 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
956 I915_WRITE(HWSTAM
, 0xffffffff);
957 I915_WRITE(PIPEASTAT
, 0);
958 I915_WRITE(PIPEBSTAT
, 0);
959 I915_WRITE(IMR
, 0xffffffff);
960 I915_WRITE(IER
, 0x0);
962 I915_WRITE(PIPEASTAT
, I915_READ(PIPEASTAT
) & 0x8000ffff);
963 I915_WRITE(PIPEBSTAT
, I915_READ(PIPEBSTAT
) & 0x8000ffff);
964 I915_WRITE(IIR
, I915_READ(IIR
));