2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
42 #include <asm/timer.h>
43 #include <asm/i8259.h>
45 #include <asm/msidef.h>
46 #include <asm/hypertransport.h>
48 #include <mach_apic.h>
49 #include <mach_apicdef.h>
51 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
52 atomic_t irq_mis_count
;
54 /* Where if anywhere is the i8259 connect in external int mode */
55 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
57 static DEFINE_SPINLOCK(ioapic_lock
);
58 static DEFINE_SPINLOCK(vector_lock
);
60 int timer_over_8254 __initdata
= 1;
63 * Is the SiS APIC rmw bug present ?
64 * -1 = don't know, 0 = no, 1 = yes
66 int sis_apic_bug
= -1;
69 * # of IRQ routing registers
71 int nr_ioapic_registers
[MAX_IO_APICS
];
73 static int disable_timer_pin_1 __initdata
;
76 * Rough estimation of how many shared IRQs there are, can
79 #define MAX_PLUS_SHARED_IRQS NR_IRQS
80 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
83 * This is performance-critical, we want to do it O(1)
85 * the indexing order of this array favors 1:1 mappings
86 * between pins and IRQs.
89 static struct irq_pin_list
{
91 } irq_2_pin
[PIN_MAP_SIZE
];
95 unsigned int unused
[3];
99 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
101 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
102 + (mp_ioapics
[idx
].mpc_apicaddr
& ~PAGE_MASK
);
105 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
107 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
108 writel(reg
, &io_apic
->index
);
109 return readl(&io_apic
->data
);
112 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
114 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
115 writel(reg
, &io_apic
->index
);
116 writel(value
, &io_apic
->data
);
120 * Re-write a value: to be used for read-modify-write
121 * cycles where the read already set up the index register.
123 * Older SiS APIC requires we rewrite the index register
125 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
127 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
129 writel(reg
, &io_apic
->index
);
130 writel(value
, &io_apic
->data
);
134 struct { u32 w1
, w2
; };
135 struct IO_APIC_route_entry entry
;
138 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
140 union entry_union eu
;
142 spin_lock_irqsave(&ioapic_lock
, flags
);
143 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
144 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
145 spin_unlock_irqrestore(&ioapic_lock
, flags
);
150 * When we write a new IO APIC routing entry, we need to write the high
151 * word first! If the mask bit in the low word is clear, we will enable
152 * the interrupt, and we need to make sure the entry is fully populated
153 * before that happens.
156 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
158 union entry_union eu
;
160 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
161 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
164 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
167 spin_lock_irqsave(&ioapic_lock
, flags
);
168 __ioapic_write_entry(apic
, pin
, e
);
169 spin_unlock_irqrestore(&ioapic_lock
, flags
);
173 * When we mask an IO APIC routing entry, we need to write the low
174 * word first, in order to set the mask bit before we change the
177 static void ioapic_mask_entry(int apic
, int pin
)
180 union entry_union eu
= { .entry
.mask
= 1 };
182 spin_lock_irqsave(&ioapic_lock
, flags
);
183 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
184 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
185 spin_unlock_irqrestore(&ioapic_lock
, flags
);
189 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
190 * shared ISA-space IRQs, so we have to support them. We are super
191 * fast in the common case, and fast for shared ISA-space IRQs.
193 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
195 static int first_free_entry
= NR_IRQS
;
196 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
199 entry
= irq_2_pin
+ entry
->next
;
201 if (entry
->pin
!= -1) {
202 entry
->next
= first_free_entry
;
203 entry
= irq_2_pin
+ entry
->next
;
204 if (++first_free_entry
>= PIN_MAP_SIZE
)
205 panic("io_apic.c: whoops");
212 * Reroute an IRQ to a different pin.
214 static void __init
replace_pin_at_irq(unsigned int irq
,
215 int oldapic
, int oldpin
,
216 int newapic
, int newpin
)
218 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
221 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
222 entry
->apic
= newapic
;
227 entry
= irq_2_pin
+ entry
->next
;
231 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
233 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
234 unsigned int pin
, reg
;
240 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
243 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
246 entry
= irq_2_pin
+ entry
->next
;
251 static void __mask_IO_APIC_irq (unsigned int irq
)
253 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
257 static void __unmask_IO_APIC_irq (unsigned int irq
)
259 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
262 /* mask = 1, trigger = 0 */
263 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
265 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
268 /* mask = 0, trigger = 1 */
269 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
271 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
274 static void mask_IO_APIC_irq (unsigned int irq
)
278 spin_lock_irqsave(&ioapic_lock
, flags
);
279 __mask_IO_APIC_irq(irq
);
280 spin_unlock_irqrestore(&ioapic_lock
, flags
);
283 static void unmask_IO_APIC_irq (unsigned int irq
)
287 spin_lock_irqsave(&ioapic_lock
, flags
);
288 __unmask_IO_APIC_irq(irq
);
289 spin_unlock_irqrestore(&ioapic_lock
, flags
);
292 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
294 struct IO_APIC_route_entry entry
;
296 /* Check delivery_mode to be sure we're not clearing an SMI pin */
297 entry
= ioapic_read_entry(apic
, pin
);
298 if (entry
.delivery_mode
== dest_SMI
)
302 * Disable it in the IO-APIC irq-routing table:
304 ioapic_mask_entry(apic
, pin
);
307 static void clear_IO_APIC (void)
311 for (apic
= 0; apic
< nr_ioapics
; apic
++)
312 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
313 clear_IO_APIC_pin(apic
, pin
);
317 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
321 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
322 unsigned int apicid_value
;
325 cpus_and(tmp
, cpumask
, cpu_online_map
);
329 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
331 apicid_value
= cpu_mask_to_apicid(cpumask
);
332 /* Prepare to do the io_apic_write */
333 apicid_value
= apicid_value
<< 24;
334 spin_lock_irqsave(&ioapic_lock
, flags
);
339 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
342 entry
= irq_2_pin
+ entry
->next
;
344 irq_desc
[irq
].affinity
= cpumask
;
345 spin_unlock_irqrestore(&ioapic_lock
, flags
);
348 #if defined(CONFIG_IRQBALANCE)
349 # include <asm/processor.h> /* kernel_thread() */
350 # include <linux/kernel_stat.h> /* kstat */
351 # include <linux/slab.h> /* kmalloc() */
352 # include <linux/timer.h> /* time_after() */
354 #define IRQBALANCE_CHECK_ARCH -999
355 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
356 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
357 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
358 #define BALANCED_IRQ_LESS_DELTA (HZ)
360 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
361 static int physical_balance __read_mostly
;
362 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
364 static struct irq_cpu_info
{
365 unsigned long * last_irq
;
366 unsigned long * irq_delta
;
368 } irq_cpu_data
[NR_CPUS
];
370 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
371 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
372 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
374 #define IDLE_ENOUGH(cpu,now) \
375 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
377 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
379 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
381 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
382 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
385 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
387 balance_irq_affinity
[irq
] = mask
;
390 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
391 unsigned long now
, int direction
)
399 if (unlikely(cpu
== curr_cpu
))
402 if (direction
== 1) {
411 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
412 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
417 static inline void balance_irq(int cpu
, int irq
)
419 unsigned long now
= jiffies
;
420 cpumask_t allowed_mask
;
421 unsigned int new_cpu
;
423 if (irqbalance_disabled
)
426 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
427 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
428 if (cpu
!= new_cpu
) {
429 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
433 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
437 for_each_online_cpu(i
) {
438 for (j
= 0; j
< NR_IRQS
; j
++) {
439 if (!irq_desc
[j
].action
)
441 /* Is it a significant load ? */
442 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
443 useful_load_threshold
)
448 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
449 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
453 static void do_irq_balance(void)
456 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
457 unsigned long move_this_load
= 0;
458 int max_loaded
= 0, min_loaded
= 0;
460 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
462 int tmp_loaded
, first_attempt
= 1;
463 unsigned long tmp_cpu_irq
;
464 unsigned long imbalance
= 0;
465 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
467 for_each_possible_cpu(i
) {
472 package_index
= CPU_TO_PACKAGEINDEX(i
);
473 for (j
= 0; j
< NR_IRQS
; j
++) {
474 unsigned long value_now
, delta
;
475 /* Is this an active IRQ or balancing disabled ? */
476 if (!irq_desc
[j
].action
|| irq_balancing_disabled(j
))
478 if ( package_index
== i
)
479 IRQ_DELTA(package_index
,j
) = 0;
480 /* Determine the total count per processor per IRQ */
481 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
483 /* Determine the activity per processor per IRQ */
484 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
486 /* Update last_cpu_irq[][] for the next time */
487 LAST_CPU_IRQ(i
,j
) = value_now
;
489 /* Ignore IRQs whose rate is less than the clock */
490 if (delta
< useful_load_threshold
)
492 /* update the load for the processor or package total */
493 IRQ_DELTA(package_index
,j
) += delta
;
495 /* Keep track of the higher numbered sibling as well */
496 if (i
!= package_index
)
499 * We have sibling A and sibling B in the package
501 * cpu_irq[A] = load for cpu A + load for cpu B
502 * cpu_irq[B] = load for cpu B
504 CPU_IRQ(package_index
) += delta
;
507 /* Find the least loaded processor package */
508 for_each_online_cpu(i
) {
509 if (i
!= CPU_TO_PACKAGEINDEX(i
))
511 if (min_cpu_irq
> CPU_IRQ(i
)) {
512 min_cpu_irq
= CPU_IRQ(i
);
516 max_cpu_irq
= ULONG_MAX
;
519 /* Look for heaviest loaded processor.
520 * We may come back to get the next heaviest loaded processor.
521 * Skip processors with trivial loads.
525 for_each_online_cpu(i
) {
526 if (i
!= CPU_TO_PACKAGEINDEX(i
))
528 if (max_cpu_irq
<= CPU_IRQ(i
))
530 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
531 tmp_cpu_irq
= CPU_IRQ(i
);
536 if (tmp_loaded
== -1) {
537 /* In the case of small number of heavy interrupt sources,
538 * loading some of the cpus too much. We use Ingo's original
539 * approach to rotate them around.
541 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
542 rotate_irqs_among_cpus(useful_load_threshold
);
545 goto not_worth_the_effort
;
548 first_attempt
= 0; /* heaviest search */
549 max_cpu_irq
= tmp_cpu_irq
; /* load */
550 max_loaded
= tmp_loaded
; /* processor */
551 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
553 /* if imbalance is less than approx 10% of max load, then
554 * observe diminishing returns action. - quit
556 if (imbalance
< (max_cpu_irq
>> 3))
557 goto not_worth_the_effort
;
560 /* if we select an IRQ to move that can't go where we want, then
561 * see if there is another one to try.
565 for (j
= 0; j
< NR_IRQS
; j
++) {
566 /* Is this an active IRQ? */
567 if (!irq_desc
[j
].action
)
569 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
571 /* Try to find the IRQ that is closest to the imbalance
572 * without going over.
574 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
575 move_this_load
= IRQ_DELTA(max_loaded
,j
);
579 if (selected_irq
== -1) {
583 imbalance
= move_this_load
;
585 /* For physical_balance case, we accumulated both load
586 * values in the one of the siblings cpu_irq[],
587 * to use the same code for physical and logical processors
588 * as much as possible.
590 * NOTE: the cpu_irq[] array holds the sum of the load for
591 * sibling A and sibling B in the slot for the lowest numbered
592 * sibling (A), _AND_ the load for sibling B in the slot for
593 * the higher numbered sibling.
595 * We seek the least loaded sibling by making the comparison
598 load
= CPU_IRQ(min_loaded
) >> 1;
599 for_each_cpu_mask(j
, per_cpu(cpu_sibling_map
, min_loaded
)) {
600 if (load
> CPU_IRQ(j
)) {
601 /* This won't change cpu_sibling_map[min_loaded] */
607 cpus_and(allowed_mask
,
609 balance_irq_affinity
[selected_irq
]);
610 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
611 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
613 if (!cpus_empty(tmp
)) {
614 /* mark for change destination */
615 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
617 /* Since we made a change, come back sooner to
618 * check for more variation.
620 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
621 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
626 not_worth_the_effort
:
628 * if we did not find an IRQ to move, then adjust the time interval
631 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
632 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
636 static int balanced_irq(void *unused
)
639 unsigned long prev_balance_time
= jiffies
;
640 long time_remaining
= balanced_irq_interval
;
642 /* push everything to CPU 0 to give us a starting point. */
643 for (i
= 0 ; i
< NR_IRQS
; i
++) {
644 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
645 set_pending_irq(i
, cpumask_of_cpu(0));
650 time_remaining
= schedule_timeout_interruptible(time_remaining
);
652 if (time_after(jiffies
,
653 prev_balance_time
+balanced_irq_interval
)) {
656 prev_balance_time
= jiffies
;
657 time_remaining
= balanced_irq_interval
;
664 static int __init
balanced_irq_init(void)
667 struct cpuinfo_x86
*c
;
670 cpus_shift_right(tmp
, cpu_online_map
, 2);
672 /* When not overwritten by the command line ask subarchitecture. */
673 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
674 irqbalance_disabled
= NO_BALANCE_IRQ
;
675 if (irqbalance_disabled
)
678 /* disable irqbalance completely if there is only one processor online */
679 if (num_online_cpus() < 2) {
680 irqbalance_disabled
= 1;
684 * Enable physical balance only if more than 1 physical processor
687 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
688 physical_balance
= 1;
690 for_each_online_cpu(i
) {
691 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
692 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
693 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
694 printk(KERN_ERR
"balanced_irq_init: out of memory");
697 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
698 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
701 printk(KERN_INFO
"Starting balanced_irq\n");
702 if (!IS_ERR(kthread_run(balanced_irq
, NULL
, "kirqd")))
704 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
706 for_each_possible_cpu(i
) {
707 kfree(irq_cpu_data
[i
].irq_delta
);
708 irq_cpu_data
[i
].irq_delta
= NULL
;
709 kfree(irq_cpu_data
[i
].last_irq
);
710 irq_cpu_data
[i
].last_irq
= NULL
;
715 int __devinit
irqbalance_disable(char *str
)
717 irqbalance_disabled
= 1;
721 __setup("noirqbalance", irqbalance_disable
);
723 late_initcall(balanced_irq_init
);
724 #endif /* CONFIG_IRQBALANCE */
725 #endif /* CONFIG_SMP */
728 void send_IPI_self(int vector
)
735 apic_wait_icr_idle();
736 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
738 * Send the IPI. The write to APIC_ICR fires this off.
740 apic_write_around(APIC_ICR
, cfg
);
742 #endif /* !CONFIG_SMP */
746 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
747 * specific CPU-side IRQs.
751 static int pirq_entries
[MAX_PIRQS
];
752 static int pirqs_enabled
;
753 int skip_ioapic_setup
;
755 static int __init
ioapic_pirq_setup(char *str
)
758 int ints
[MAX_PIRQS
+1];
760 get_options(str
, ARRAY_SIZE(ints
), ints
);
762 for (i
= 0; i
< MAX_PIRQS
; i
++)
763 pirq_entries
[i
] = -1;
766 apic_printk(APIC_VERBOSE
, KERN_INFO
767 "PIRQ redirection, working around broken MP-BIOS.\n");
769 if (ints
[0] < MAX_PIRQS
)
772 for (i
= 0; i
< max
; i
++) {
773 apic_printk(APIC_VERBOSE
, KERN_DEBUG
774 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
776 * PIRQs are mapped upside down, usually.
778 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
783 __setup("pirq=", ioapic_pirq_setup
);
786 * Find the IRQ entry number of a certain pin.
788 static int find_irq_entry(int apic
, int pin
, int type
)
792 for (i
= 0; i
< mp_irq_entries
; i
++)
793 if (mp_irqs
[i
].mpc_irqtype
== type
&&
794 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
795 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
796 mp_irqs
[i
].mpc_dstirq
== pin
)
803 * Find the pin to which IRQ[irq] (ISA) is connected
805 static int __init
find_isa_irq_pin(int irq
, int type
)
809 for (i
= 0; i
< mp_irq_entries
; i
++) {
810 int lbus
= mp_irqs
[i
].mpc_srcbus
;
812 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
813 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
814 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
816 (mp_irqs
[i
].mpc_irqtype
== type
) &&
817 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
819 return mp_irqs
[i
].mpc_dstirq
;
824 static int __init
find_isa_irq_apic(int irq
, int type
)
828 for (i
= 0; i
< mp_irq_entries
; i
++) {
829 int lbus
= mp_irqs
[i
].mpc_srcbus
;
831 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
832 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
833 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
835 (mp_irqs
[i
].mpc_irqtype
== type
) &&
836 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
839 if (i
< mp_irq_entries
) {
841 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
842 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
851 * Find a specific PCI IRQ entry.
852 * Not an __init, possibly needed by modules
854 static int pin_2_irq(int idx
, int apic
, int pin
);
856 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
858 int apic
, i
, best_guess
= -1;
860 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
861 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
862 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
863 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
866 for (i
= 0; i
< mp_irq_entries
; i
++) {
867 int lbus
= mp_irqs
[i
].mpc_srcbus
;
869 for (apic
= 0; apic
< nr_ioapics
; apic
++)
870 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
871 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
874 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
875 !mp_irqs
[i
].mpc_irqtype
&&
877 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
878 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
880 if (!(apic
|| IO_APIC_IRQ(irq
)))
883 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
886 * Use the first all-but-pin matching entry as a
887 * best-guess fuzzy result for broken mptables.
895 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
898 * This function currently is only a helper for the i386 smp boot process where
899 * we need to reprogram the ioredtbls to cater for the cpus which have come online
900 * so mask in all cases should simply be TARGET_CPUS
903 void __init
setup_ioapic_dest(void)
905 int pin
, ioapic
, irq
, irq_entry
;
907 if (skip_ioapic_setup
== 1)
910 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
911 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
912 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
915 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
916 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
924 * EISA Edge/Level control register, ELCR
926 static int EISA_ELCR(unsigned int irq
)
929 unsigned int port
= 0x4d0 + (irq
>> 3);
930 return (inb(port
) >> (irq
& 7)) & 1;
932 apic_printk(APIC_VERBOSE
, KERN_INFO
933 "Broken MPtable reports ISA irq %d\n", irq
);
937 /* EISA interrupts are always polarity zero and can be edge or level
938 * trigger depending on the ELCR value. If an interrupt is listed as
939 * EISA conforming in the MP table, that means its trigger type must
940 * be read in from the ELCR */
942 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
943 #define default_EISA_polarity(idx) (0)
945 /* ISA interrupts are always polarity zero edge triggered,
946 * when listed as conforming in the MP table. */
948 #define default_ISA_trigger(idx) (0)
949 #define default_ISA_polarity(idx) (0)
951 /* PCI interrupts are always polarity one level triggered,
952 * when listed as conforming in the MP table. */
954 #define default_PCI_trigger(idx) (1)
955 #define default_PCI_polarity(idx) (1)
957 /* MCA interrupts are always polarity zero level triggered,
958 * when listed as conforming in the MP table. */
960 #define default_MCA_trigger(idx) (1)
961 #define default_MCA_polarity(idx) (0)
963 static int MPBIOS_polarity(int idx
)
965 int bus
= mp_irqs
[idx
].mpc_srcbus
;
969 * Determine IRQ line polarity (high active or low active):
971 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
973 case 0: /* conforms, ie. bus-type dependent polarity */
975 switch (mp_bus_id_to_type
[bus
])
977 case MP_BUS_ISA
: /* ISA pin */
979 polarity
= default_ISA_polarity(idx
);
982 case MP_BUS_EISA
: /* EISA pin */
984 polarity
= default_EISA_polarity(idx
);
987 case MP_BUS_PCI
: /* PCI pin */
989 polarity
= default_PCI_polarity(idx
);
992 case MP_BUS_MCA
: /* MCA pin */
994 polarity
= default_MCA_polarity(idx
);
999 printk(KERN_WARNING
"broken BIOS!!\n");
1006 case 1: /* high active */
1011 case 2: /* reserved */
1013 printk(KERN_WARNING
"broken BIOS!!\n");
1017 case 3: /* low active */
1022 default: /* invalid */
1024 printk(KERN_WARNING
"broken BIOS!!\n");
1032 static int MPBIOS_trigger(int idx
)
1034 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1038 * Determine IRQ trigger mode (edge or level sensitive):
1040 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
1042 case 0: /* conforms, ie. bus-type dependent */
1044 switch (mp_bus_id_to_type
[bus
])
1046 case MP_BUS_ISA
: /* ISA pin */
1048 trigger
= default_ISA_trigger(idx
);
1051 case MP_BUS_EISA
: /* EISA pin */
1053 trigger
= default_EISA_trigger(idx
);
1056 case MP_BUS_PCI
: /* PCI pin */
1058 trigger
= default_PCI_trigger(idx
);
1061 case MP_BUS_MCA
: /* MCA pin */
1063 trigger
= default_MCA_trigger(idx
);
1068 printk(KERN_WARNING
"broken BIOS!!\n");
1080 case 2: /* reserved */
1082 printk(KERN_WARNING
"broken BIOS!!\n");
1091 default: /* invalid */
1093 printk(KERN_WARNING
"broken BIOS!!\n");
1101 static inline int irq_polarity(int idx
)
1103 return MPBIOS_polarity(idx
);
1106 static inline int irq_trigger(int idx
)
1108 return MPBIOS_trigger(idx
);
1111 static int pin_2_irq(int idx
, int apic
, int pin
)
1114 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1117 * Debugging check, we are in big trouble if this message pops up!
1119 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1120 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1122 switch (mp_bus_id_to_type
[bus
])
1124 case MP_BUS_ISA
: /* ISA pin */
1128 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1131 case MP_BUS_PCI
: /* PCI pin */
1134 * PCI IRQs are mapped in order
1138 irq
+= nr_ioapic_registers
[i
++];
1142 * For MPS mode, so far only needed by ES7000 platform
1144 if (ioapic_renumber_irq
)
1145 irq
= ioapic_renumber_irq(apic
, irq
);
1151 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1158 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1160 if ((pin
>= 16) && (pin
<= 23)) {
1161 if (pirq_entries
[pin
-16] != -1) {
1162 if (!pirq_entries
[pin
-16]) {
1163 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1164 "disabling PIRQ%d\n", pin
-16);
1166 irq
= pirq_entries
[pin
-16];
1167 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1168 "using PIRQ%d -> IRQ %d\n",
1176 static inline int IO_APIC_irq_trigger(int irq
)
1180 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1181 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1182 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1183 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1184 return irq_trigger(idx
);
1188 * nonexistent IRQs are edge default
1193 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1194 static u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1196 static int __assign_irq_vector(int irq
)
1198 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1201 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
1203 if (irq_vector
[irq
] > 0)
1204 return irq_vector
[irq
];
1206 vector
= current_vector
;
1207 offset
= current_offset
;
1210 if (vector
>= FIRST_SYSTEM_VECTOR
) {
1211 offset
= (offset
+ 1) % 8;
1212 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1214 if (vector
== current_vector
)
1216 if (test_and_set_bit(vector
, used_vectors
))
1219 current_vector
= vector
;
1220 current_offset
= offset
;
1221 irq_vector
[irq
] = vector
;
1226 static int assign_irq_vector(int irq
)
1228 unsigned long flags
;
1231 spin_lock_irqsave(&vector_lock
, flags
);
1232 vector
= __assign_irq_vector(irq
);
1233 spin_unlock_irqrestore(&vector_lock
, flags
);
1237 static struct irq_chip ioapic_chip
;
1239 #define IOAPIC_AUTO -1
1240 #define IOAPIC_EDGE 0
1241 #define IOAPIC_LEVEL 1
1243 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1245 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1246 trigger
== IOAPIC_LEVEL
) {
1247 irq_desc
[irq
].status
|= IRQ_LEVEL
;
1248 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1249 handle_fasteoi_irq
, "fasteoi");
1251 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1252 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1253 handle_edge_irq
, "edge");
1255 set_intr_gate(vector
, interrupt
[irq
]);
1258 static void __init
setup_IO_APIC_irqs(void)
1260 struct IO_APIC_route_entry entry
;
1261 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1262 unsigned long flags
;
1264 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1266 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1267 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1270 * add it to the IO-APIC irq-routing table:
1272 memset(&entry
,0,sizeof(entry
));
1274 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1275 entry
.dest_mode
= INT_DEST_MODE
;
1276 entry
.mask
= 0; /* enable IRQ */
1277 entry
.dest
.logical
.logical_dest
=
1278 cpu_mask_to_apicid(TARGET_CPUS
);
1280 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1283 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1284 " IO-APIC (apicid-pin) %d-%d",
1285 mp_ioapics
[apic
].mpc_apicid
,
1289 apic_printk(APIC_VERBOSE
, ", %d-%d",
1290 mp_ioapics
[apic
].mpc_apicid
, pin
);
1294 if (!first_notcon
) {
1295 apic_printk(APIC_VERBOSE
, " not connected.\n");
1299 entry
.trigger
= irq_trigger(idx
);
1300 entry
.polarity
= irq_polarity(idx
);
1302 if (irq_trigger(idx
)) {
1307 irq
= pin_2_irq(idx
, apic
, pin
);
1309 * skip adding the timer int on secondary nodes, which causes
1310 * a small but painful rift in the time-space continuum
1312 if (multi_timer_check(apic
, irq
))
1315 add_pin_to_irq(irq
, apic
, pin
);
1317 if (!apic
&& !IO_APIC_IRQ(irq
))
1320 if (IO_APIC_IRQ(irq
)) {
1321 vector
= assign_irq_vector(irq
);
1322 entry
.vector
= vector
;
1323 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1325 if (!apic
&& (irq
< 16))
1326 disable_8259A_irq(irq
);
1328 spin_lock_irqsave(&ioapic_lock
, flags
);
1329 __ioapic_write_entry(apic
, pin
, entry
);
1330 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1335 apic_printk(APIC_VERBOSE
, " not connected.\n");
1339 * Set up the 8259A-master output pin:
1341 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1343 struct IO_APIC_route_entry entry
;
1345 memset(&entry
,0,sizeof(entry
));
1347 disable_8259A_irq(0);
1350 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1353 * We use logical delivery to get the timer IRQ
1356 entry
.dest_mode
= INT_DEST_MODE
;
1357 entry
.mask
= 0; /* unmask IRQ now */
1358 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1359 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1362 entry
.vector
= vector
;
1365 * The timer IRQ doesn't have to know that behind the
1366 * scene we have a 8259A-master in AEOI mode ...
1368 irq_desc
[0].chip
= &ioapic_chip
;
1369 set_irq_handler(0, handle_edge_irq
);
1372 * Add it to the IO-APIC irq-routing table:
1374 ioapic_write_entry(apic
, pin
, entry
);
1376 enable_8259A_irq(0);
1379 void __init
print_IO_APIC(void)
1382 union IO_APIC_reg_00 reg_00
;
1383 union IO_APIC_reg_01 reg_01
;
1384 union IO_APIC_reg_02 reg_02
;
1385 union IO_APIC_reg_03 reg_03
;
1386 unsigned long flags
;
1388 if (apic_verbosity
== APIC_QUIET
)
1391 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1392 for (i
= 0; i
< nr_ioapics
; i
++)
1393 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1394 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1397 * We are a bit conservative about what we expect. We have to
1398 * know about every hardware change ASAP.
1400 printk(KERN_INFO
"testing the IO APIC.......................\n");
1402 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1404 spin_lock_irqsave(&ioapic_lock
, flags
);
1405 reg_00
.raw
= io_apic_read(apic
, 0);
1406 reg_01
.raw
= io_apic_read(apic
, 1);
1407 if (reg_01
.bits
.version
>= 0x10)
1408 reg_02
.raw
= io_apic_read(apic
, 2);
1409 if (reg_01
.bits
.version
>= 0x20)
1410 reg_03
.raw
= io_apic_read(apic
, 3);
1411 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1413 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1414 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1415 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1416 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1417 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1419 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1420 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1422 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1423 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1426 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1427 * but the value of reg_02 is read as the previous read register
1428 * value, so ignore it if reg_02 == reg_01.
1430 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1431 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1432 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1436 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1437 * or reg_03, but the value of reg_0[23] is read as the previous read
1438 * register value, so ignore it if reg_03 == reg_0[12].
1440 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1441 reg_03
.raw
!= reg_01
.raw
) {
1442 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1443 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1446 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1448 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1449 " Stat Dest Deli Vect: \n");
1451 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1452 struct IO_APIC_route_entry entry
;
1454 entry
= ioapic_read_entry(apic
, i
);
1456 printk(KERN_DEBUG
" %02x %03X %02X ",
1458 entry
.dest
.logical
.logical_dest
,
1459 entry
.dest
.physical
.physical_dest
1462 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1467 entry
.delivery_status
,
1469 entry
.delivery_mode
,
1474 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1475 for (i
= 0; i
< NR_IRQS
; i
++) {
1476 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1479 printk(KERN_DEBUG
"IRQ%d ", i
);
1481 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1484 entry
= irq_2_pin
+ entry
->next
;
1489 printk(KERN_INFO
".................................... done.\n");
1496 static void print_APIC_bitfield (int base
)
1501 if (apic_verbosity
== APIC_QUIET
)
1504 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1505 for (i
= 0; i
< 8; i
++) {
1506 v
= apic_read(base
+ i
*0x10);
1507 for (j
= 0; j
< 32; j
++) {
1517 void /*__init*/ print_local_APIC(void * dummy
)
1519 unsigned int v
, ver
, maxlvt
;
1521 if (apic_verbosity
== APIC_QUIET
)
1524 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1525 smp_processor_id(), hard_smp_processor_id());
1526 v
= apic_read(APIC_ID
);
1527 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1528 v
= apic_read(APIC_LVR
);
1529 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1530 ver
= GET_APIC_VERSION(v
);
1531 maxlvt
= lapic_get_maxlvt();
1533 v
= apic_read(APIC_TASKPRI
);
1534 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1536 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1537 v
= apic_read(APIC_ARBPRI
);
1538 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1539 v
& APIC_ARBPRI_MASK
);
1540 v
= apic_read(APIC_PROCPRI
);
1541 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1544 v
= apic_read(APIC_EOI
);
1545 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1546 v
= apic_read(APIC_RRR
);
1547 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1548 v
= apic_read(APIC_LDR
);
1549 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1550 v
= apic_read(APIC_DFR
);
1551 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1552 v
= apic_read(APIC_SPIV
);
1553 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1555 printk(KERN_DEBUG
"... APIC ISR field:\n");
1556 print_APIC_bitfield(APIC_ISR
);
1557 printk(KERN_DEBUG
"... APIC TMR field:\n");
1558 print_APIC_bitfield(APIC_TMR
);
1559 printk(KERN_DEBUG
"... APIC IRR field:\n");
1560 print_APIC_bitfield(APIC_IRR
);
1562 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1563 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1564 apic_write(APIC_ESR
, 0);
1565 v
= apic_read(APIC_ESR
);
1566 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1569 v
= apic_read(APIC_ICR
);
1570 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1571 v
= apic_read(APIC_ICR2
);
1572 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1574 v
= apic_read(APIC_LVTT
);
1575 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1577 if (maxlvt
> 3) { /* PC is LVT#4. */
1578 v
= apic_read(APIC_LVTPC
);
1579 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1581 v
= apic_read(APIC_LVT0
);
1582 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1583 v
= apic_read(APIC_LVT1
);
1584 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1586 if (maxlvt
> 2) { /* ERR is LVT#3. */
1587 v
= apic_read(APIC_LVTERR
);
1588 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1591 v
= apic_read(APIC_TMICT
);
1592 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1593 v
= apic_read(APIC_TMCCT
);
1594 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1595 v
= apic_read(APIC_TDCR
);
1596 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1600 void print_all_local_APICs (void)
1602 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1605 void /*__init*/ print_PIC(void)
1608 unsigned long flags
;
1610 if (apic_verbosity
== APIC_QUIET
)
1613 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1615 spin_lock_irqsave(&i8259A_lock
, flags
);
1617 v
= inb(0xa1) << 8 | inb(0x21);
1618 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1620 v
= inb(0xa0) << 8 | inb(0x20);
1621 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1625 v
= inb(0xa0) << 8 | inb(0x20);
1629 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1631 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1633 v
= inb(0x4d1) << 8 | inb(0x4d0);
1634 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1639 static void __init
enable_IO_APIC(void)
1641 union IO_APIC_reg_01 reg_01
;
1642 int i8259_apic
, i8259_pin
;
1644 unsigned long flags
;
1646 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1647 irq_2_pin
[i
].pin
= -1;
1648 irq_2_pin
[i
].next
= 0;
1651 for (i
= 0; i
< MAX_PIRQS
; i
++)
1652 pirq_entries
[i
] = -1;
1655 * The number of IO-APIC IRQ registers (== #pins):
1657 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1658 spin_lock_irqsave(&ioapic_lock
, flags
);
1659 reg_01
.raw
= io_apic_read(apic
, 1);
1660 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1661 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1663 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1665 /* See if any of the pins is in ExtINT mode */
1666 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1667 struct IO_APIC_route_entry entry
;
1668 entry
= ioapic_read_entry(apic
, pin
);
1671 /* If the interrupt line is enabled and in ExtInt mode
1672 * I have found the pin where the i8259 is connected.
1674 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1675 ioapic_i8259
.apic
= apic
;
1676 ioapic_i8259
.pin
= pin
;
1682 /* Look to see what if the MP table has reported the ExtINT */
1683 /* If we could not find the appropriate pin by looking at the ioapic
1684 * the i8259 probably is not connected the ioapic but give the
1685 * mptable a chance anyway.
1687 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1688 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1689 /* Trust the MP table if nothing is setup in the hardware */
1690 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1691 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1692 ioapic_i8259
.pin
= i8259_pin
;
1693 ioapic_i8259
.apic
= i8259_apic
;
1695 /* Complain if the MP table and the hardware disagree */
1696 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1697 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1699 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1703 * Do not trust the IO-APIC being empty at bootup
1709 * Not an __init, needed by the reboot code
1711 void disable_IO_APIC(void)
1714 * Clear the IO-APIC before rebooting:
1719 * If the i8259 is routed through an IOAPIC
1720 * Put that IOAPIC in virtual wire mode
1721 * so legacy interrupts can be delivered.
1723 if (ioapic_i8259
.pin
!= -1) {
1724 struct IO_APIC_route_entry entry
;
1726 memset(&entry
, 0, sizeof(entry
));
1727 entry
.mask
= 0; /* Enabled */
1728 entry
.trigger
= 0; /* Edge */
1730 entry
.polarity
= 0; /* High */
1731 entry
.delivery_status
= 0;
1732 entry
.dest_mode
= 0; /* Physical */
1733 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1735 entry
.dest
.physical
.physical_dest
=
1736 GET_APIC_ID(apic_read(APIC_ID
));
1739 * Add it to the IO-APIC irq-routing table:
1741 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1743 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1747 * function to set the IO-APIC physical IDs based on the
1748 * values stored in the MPC table.
1750 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1753 #ifndef CONFIG_X86_NUMAQ
1754 static void __init
setup_ioapic_ids_from_mpc(void)
1756 union IO_APIC_reg_00 reg_00
;
1757 physid_mask_t phys_id_present_map
;
1760 unsigned char old_id
;
1761 unsigned long flags
;
1764 * Don't check I/O APIC IDs for xAPIC systems. They have
1765 * no meaning without the serial APIC bus.
1767 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1768 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1771 * This is broken; anything with a real cpu count has to
1772 * circumvent this idiocy regardless.
1774 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1777 * Set the IOAPIC ID to the value stored in the MPC table.
1779 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1781 /* Read the register 0 value */
1782 spin_lock_irqsave(&ioapic_lock
, flags
);
1783 reg_00
.raw
= io_apic_read(apic
, 0);
1784 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1786 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1788 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1789 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1790 apic
, mp_ioapics
[apic
].mpc_apicid
);
1791 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1793 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1797 * Sanity check, is the ID really free? Every APIC in a
1798 * system must have a unique ID or we get lots of nice
1799 * 'stuck on smp_invalidate_needed IPI wait' messages.
1801 if (check_apicid_used(phys_id_present_map
,
1802 mp_ioapics
[apic
].mpc_apicid
)) {
1803 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1804 apic
, mp_ioapics
[apic
].mpc_apicid
);
1805 for (i
= 0; i
< get_physical_broadcast(); i
++)
1806 if (!physid_isset(i
, phys_id_present_map
))
1808 if (i
>= get_physical_broadcast())
1809 panic("Max APIC ID exceeded!\n");
1810 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1812 physid_set(i
, phys_id_present_map
);
1813 mp_ioapics
[apic
].mpc_apicid
= i
;
1816 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1817 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1818 "phys_id_present_map\n",
1819 mp_ioapics
[apic
].mpc_apicid
);
1820 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1825 * We need to adjust the IRQ routing table
1826 * if the ID changed.
1828 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1829 for (i
= 0; i
< mp_irq_entries
; i
++)
1830 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1831 mp_irqs
[i
].mpc_dstapic
1832 = mp_ioapics
[apic
].mpc_apicid
;
1835 * Read the right value from the MPC table and
1836 * write it into the ID register.
1838 apic_printk(APIC_VERBOSE
, KERN_INFO
1839 "...changing IO-APIC physical APIC ID to %d ...",
1840 mp_ioapics
[apic
].mpc_apicid
);
1842 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1843 spin_lock_irqsave(&ioapic_lock
, flags
);
1844 io_apic_write(apic
, 0, reg_00
.raw
);
1845 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1850 spin_lock_irqsave(&ioapic_lock
, flags
);
1851 reg_00
.raw
= io_apic_read(apic
, 0);
1852 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1853 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1854 printk("could not set ID!\n");
1856 apic_printk(APIC_VERBOSE
, " ok.\n");
1860 static void __init
setup_ioapic_ids_from_mpc(void) { }
1863 int no_timer_check __initdata
;
1865 static int __init
notimercheck(char *s
)
1870 __setup("no_timer_check", notimercheck
);
1873 * There is a nasty bug in some older SMP boards, their mptable lies
1874 * about the timer IRQ. We do the following to work around the situation:
1876 * - timer IRQ defaults to IO-APIC IRQ
1877 * - if this function detects that timer IRQs are defunct, then we fall
1878 * back to ISA timer IRQs
1880 static int __init
timer_irq_works(void)
1882 unsigned long t1
= jiffies
;
1883 unsigned long flags
;
1888 local_save_flags(flags
);
1890 /* Let ten ticks pass... */
1891 mdelay((10 * 1000) / HZ
);
1892 local_irq_restore(flags
);
1895 * Expect a few ticks at least, to be sure some possible
1896 * glue logic does not lock up after one or two first
1897 * ticks in a non-ExtINT mode. Also the local APIC
1898 * might have cached one ExtINT interrupt. Finally, at
1899 * least one tick may be lost due to delays.
1901 if (jiffies
- t1
> 4)
1908 * In the SMP+IOAPIC case it might happen that there are an unspecified
1909 * number of pending IRQ events unhandled. These cases are very rare,
1910 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1911 * better to do it this way as thus we do not have to be aware of
1912 * 'pending' interrupts in the IRQ path, except at this point.
1915 * Edge triggered needs to resend any interrupt
1916 * that was delayed but this is now handled in the device
1923 * Starting up a edge-triggered IO-APIC interrupt is
1924 * nasty - we need to make sure that we get the edge.
1925 * If it is already asserted for some reason, we need
1926 * return 1 to indicate that is was pending.
1928 * This is not complete - we should be able to fake
1929 * an edge even if it isn't on the 8259A...
1931 * (We do this for level-triggered IRQs too - it cannot hurt.)
1933 static unsigned int startup_ioapic_irq(unsigned int irq
)
1935 int was_pending
= 0;
1936 unsigned long flags
;
1938 spin_lock_irqsave(&ioapic_lock
, flags
);
1940 disable_8259A_irq(irq
);
1941 if (i8259A_irq_pending(irq
))
1944 __unmask_IO_APIC_irq(irq
);
1945 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1950 static void ack_ioapic_irq(unsigned int irq
)
1952 move_native_irq(irq
);
1956 static void ack_ioapic_quirk_irq(unsigned int irq
)
1961 move_native_irq(irq
);
1963 * It appears there is an erratum which affects at least version 0x11
1964 * of I/O APIC (that's the 82093AA and cores integrated into various
1965 * chipsets). Under certain conditions a level-triggered interrupt is
1966 * erroneously delivered as edge-triggered one but the respective IRR
1967 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1968 * message but it will never arrive and further interrupts are blocked
1969 * from the source. The exact reason is so far unknown, but the
1970 * phenomenon was observed when two consecutive interrupt requests
1971 * from a given source get delivered to the same CPU and the source is
1972 * temporarily disabled in between.
1974 * A workaround is to simulate an EOI message manually. We achieve it
1975 * by setting the trigger mode to edge and then to level when the edge
1976 * trigger mode gets detected in the TMR of a local APIC for a
1977 * level-triggered interrupt. We mask the source for the time of the
1978 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1979 * The idea is from Manfred Spraul. --macro
1981 i
= irq_vector
[irq
];
1983 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1987 if (!(v
& (1 << (i
& 0x1f)))) {
1988 atomic_inc(&irq_mis_count
);
1989 spin_lock(&ioapic_lock
);
1990 __mask_and_edge_IO_APIC_irq(irq
);
1991 __unmask_and_level_IO_APIC_irq(irq
);
1992 spin_unlock(&ioapic_lock
);
1996 static int ioapic_retrigger_irq(unsigned int irq
)
1998 send_IPI_self(irq_vector
[irq
]);
2003 static struct irq_chip ioapic_chip __read_mostly
= {
2005 .startup
= startup_ioapic_irq
,
2006 .mask
= mask_IO_APIC_irq
,
2007 .unmask
= unmask_IO_APIC_irq
,
2008 .ack
= ack_ioapic_irq
,
2009 .eoi
= ack_ioapic_quirk_irq
,
2011 .set_affinity
= set_ioapic_affinity_irq
,
2013 .retrigger
= ioapic_retrigger_irq
,
2017 static inline void init_IO_APIC_traps(void)
2022 * NOTE! The local APIC isn't very good at handling
2023 * multiple interrupts at the same interrupt level.
2024 * As the interrupt level is determined by taking the
2025 * vector number and shifting that right by 4, we
2026 * want to spread these out a bit so that they don't
2027 * all fall in the same interrupt level.
2029 * Also, we've got to be careful not to trash gate
2030 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2032 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2034 if (IO_APIC_IRQ(tmp
) && !irq_vector
[tmp
]) {
2036 * Hmm.. We don't have an entry for this,
2037 * so default to an old-fashioned 8259
2038 * interrupt if we can..
2041 make_8259A_irq(irq
);
2043 /* Strange. Oh, well.. */
2044 irq_desc
[irq
].chip
= &no_irq_chip
;
2050 * The local APIC irq-chip implementation:
2053 static void ack_apic(unsigned int irq
)
2058 static void mask_lapic_irq (unsigned int irq
)
2062 v
= apic_read(APIC_LVT0
);
2063 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2066 static void unmask_lapic_irq (unsigned int irq
)
2070 v
= apic_read(APIC_LVT0
);
2071 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2074 static struct irq_chip lapic_chip __read_mostly
= {
2075 .name
= "local-APIC-edge",
2076 .mask
= mask_lapic_irq
,
2077 .unmask
= unmask_lapic_irq
,
2081 static void setup_nmi (void)
2084 * Dirty trick to enable the NMI watchdog ...
2085 * We put the 8259A master into AEOI mode and
2086 * unmask on all local APICs LVT0 as NMI.
2088 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2089 * is from Maciej W. Rozycki - so we do not have to EOI from
2090 * the NMI handler or the timer interrupt.
2092 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2094 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2096 apic_printk(APIC_VERBOSE
, " done.\n");
2100 * This looks a bit hackish but it's about the only one way of sending
2101 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2102 * not support the ExtINT mode, unfortunately. We need to send these
2103 * cycles as some i82489DX-based boards have glue logic that keeps the
2104 * 8259A interrupt line asserted until INTA. --macro
2106 static inline void unlock_ExtINT_logic(void)
2109 struct IO_APIC_route_entry entry0
, entry1
;
2110 unsigned char save_control
, save_freq_select
;
2112 pin
= find_isa_irq_pin(8, mp_INT
);
2117 apic
= find_isa_irq_apic(8, mp_INT
);
2123 entry0
= ioapic_read_entry(apic
, pin
);
2124 clear_IO_APIC_pin(apic
, pin
);
2126 memset(&entry1
, 0, sizeof(entry1
));
2128 entry1
.dest_mode
= 0; /* physical delivery */
2129 entry1
.mask
= 0; /* unmask IRQ now */
2130 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2131 entry1
.delivery_mode
= dest_ExtINT
;
2132 entry1
.polarity
= entry0
.polarity
;
2136 ioapic_write_entry(apic
, pin
, entry1
);
2138 save_control
= CMOS_READ(RTC_CONTROL
);
2139 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2140 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2142 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2147 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2151 CMOS_WRITE(save_control
, RTC_CONTROL
);
2152 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2153 clear_IO_APIC_pin(apic
, pin
);
2155 ioapic_write_entry(apic
, pin
, entry0
);
2158 int timer_uses_ioapic_pin_0
;
2161 * This code may look a bit paranoid, but it's supposed to cooperate with
2162 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2163 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2164 * fanatically on his truly buggy board.
2166 static inline void __init
check_timer(void)
2168 int apic1
, pin1
, apic2
, pin2
;
2170 unsigned long flags
;
2172 local_irq_save(flags
);
2175 * get/set the timer IRQ vector:
2177 disable_8259A_irq(0);
2178 vector
= assign_irq_vector(0);
2179 set_intr_gate(vector
, interrupt
[0]);
2182 * Subtle, code in do_timer_interrupt() expects an AEOI
2183 * mode for the 8259A whenever interrupts are routed
2184 * through I/O APICs. Also IRQ0 has to be enabled in
2185 * the 8259A which implies the virtual wire has to be
2186 * disabled in the local APIC.
2188 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2191 if (timer_over_8254
> 0)
2192 enable_8259A_irq(0);
2194 pin1
= find_isa_irq_pin(0, mp_INT
);
2195 apic1
= find_isa_irq_apic(0, mp_INT
);
2196 pin2
= ioapic_i8259
.pin
;
2197 apic2
= ioapic_i8259
.apic
;
2200 timer_uses_ioapic_pin_0
= 1;
2202 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2203 vector
, apic1
, pin1
, apic2
, pin2
);
2207 * Ok, does IRQ0 through the IOAPIC work?
2209 unmask_IO_APIC_irq(0);
2210 if (timer_irq_works()) {
2211 if (nmi_watchdog
== NMI_IO_APIC
) {
2212 disable_8259A_irq(0);
2214 enable_8259A_irq(0);
2216 if (disable_timer_pin_1
> 0)
2217 clear_IO_APIC_pin(0, pin1
);
2220 clear_IO_APIC_pin(apic1
, pin1
);
2221 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2225 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2227 printk("\n..... (found pin %d) ...", pin2
);
2229 * legacy devices should be connected to IO APIC #0
2231 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2232 if (timer_irq_works()) {
2235 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2237 add_pin_to_irq(0, apic2
, pin2
);
2238 if (nmi_watchdog
== NMI_IO_APIC
) {
2244 * Cleanup, just in case ...
2246 clear_IO_APIC_pin(apic2
, pin2
);
2248 printk(" failed.\n");
2250 if (nmi_watchdog
== NMI_IO_APIC
) {
2251 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2255 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2257 disable_8259A_irq(0);
2258 set_irq_chip_and_handler_name(0, &lapic_chip
, handle_fasteoi_irq
,
2260 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2261 enable_8259A_irq(0);
2263 if (timer_irq_works()) {
2264 printk(" works.\n");
2267 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2268 printk(" failed.\n");
2270 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2275 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2277 unlock_ExtINT_logic();
2279 if (timer_irq_works()) {
2280 printk(" works.\n");
2283 printk(" failed :(.\n");
2284 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2285 "report. Then try booting with the 'noapic' option");
2287 local_irq_restore(flags
);
2292 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2293 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2294 * Linux doesn't really care, as it's not actually used
2295 * for any interrupt handling anyway.
2297 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2299 void __init
setup_IO_APIC(void)
2303 /* Reserve all the system vectors. */
2304 for (i
= FIRST_SYSTEM_VECTOR
; i
< NR_VECTORS
; i
++)
2305 set_bit(i
, used_vectors
);
2310 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2312 io_apic_irqs
= ~PIC_IRQS
;
2314 printk("ENABLING IO-APIC IRQs\n");
2317 * Set up IO-APIC IRQ routing.
2320 setup_ioapic_ids_from_mpc();
2322 setup_IO_APIC_irqs();
2323 init_IO_APIC_traps();
2329 static int __init
setup_disable_8254_timer(char *s
)
2331 timer_over_8254
= -1;
2334 static int __init
setup_enable_8254_timer(char *s
)
2336 timer_over_8254
= 2;
2340 __setup("disable_8254_timer", setup_disable_8254_timer
);
2341 __setup("enable_8254_timer", setup_enable_8254_timer
);
2344 * Called after all the initialization is done. If we didnt find any
2345 * APIC bugs then we can allow the modify fast path
2348 static int __init
io_apic_bug_finalize(void)
2350 if(sis_apic_bug
== -1)
2355 late_initcall(io_apic_bug_finalize
);
2357 struct sysfs_ioapic_data
{
2358 struct sys_device dev
;
2359 struct IO_APIC_route_entry entry
[0];
2361 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2363 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2365 struct IO_APIC_route_entry
*entry
;
2366 struct sysfs_ioapic_data
*data
;
2369 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2370 entry
= data
->entry
;
2371 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2372 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2377 static int ioapic_resume(struct sys_device
*dev
)
2379 struct IO_APIC_route_entry
*entry
;
2380 struct sysfs_ioapic_data
*data
;
2381 unsigned long flags
;
2382 union IO_APIC_reg_00 reg_00
;
2385 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2386 entry
= data
->entry
;
2388 spin_lock_irqsave(&ioapic_lock
, flags
);
2389 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2390 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2391 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2392 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2394 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2395 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2396 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2401 static struct sysdev_class ioapic_sysdev_class
= {
2403 .suspend
= ioapic_suspend
,
2404 .resume
= ioapic_resume
,
2407 static int __init
ioapic_init_sysfs(void)
2409 struct sys_device
* dev
;
2410 int i
, size
, error
= 0;
2412 error
= sysdev_class_register(&ioapic_sysdev_class
);
2416 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2417 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2418 * sizeof(struct IO_APIC_route_entry
);
2419 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2420 if (!mp_ioapic_data
[i
]) {
2421 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2424 memset(mp_ioapic_data
[i
], 0, size
);
2425 dev
= &mp_ioapic_data
[i
]->dev
;
2427 dev
->cls
= &ioapic_sysdev_class
;
2428 error
= sysdev_register(dev
);
2430 kfree(mp_ioapic_data
[i
]);
2431 mp_ioapic_data
[i
] = NULL
;
2432 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2440 device_initcall(ioapic_init_sysfs
);
2443 * Dynamic irq allocate and deallocation
2445 int create_irq(void)
2447 /* Allocate an unused irq */
2448 int irq
, new, vector
= 0;
2449 unsigned long flags
;
2452 spin_lock_irqsave(&vector_lock
, flags
);
2453 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2454 if (platform_legacy_irq(new))
2456 if (irq_vector
[new] != 0)
2458 vector
= __assign_irq_vector(new);
2459 if (likely(vector
> 0))
2463 spin_unlock_irqrestore(&vector_lock
, flags
);
2466 set_intr_gate(vector
, interrupt
[irq
]);
2467 dynamic_irq_init(irq
);
2472 void destroy_irq(unsigned int irq
)
2474 unsigned long flags
;
2476 dynamic_irq_cleanup(irq
);
2478 spin_lock_irqsave(&vector_lock
, flags
);
2479 irq_vector
[irq
] = 0;
2480 spin_unlock_irqrestore(&vector_lock
, flags
);
2484 * MSI message composition
2486 #ifdef CONFIG_PCI_MSI
2487 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2492 vector
= assign_irq_vector(irq
);
2494 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2496 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2499 ((INT_DEST_MODE
== 0) ?
2500 MSI_ADDR_DEST_MODE_PHYSICAL
:
2501 MSI_ADDR_DEST_MODE_LOGICAL
) |
2502 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2503 MSI_ADDR_REDIRECTION_CPU
:
2504 MSI_ADDR_REDIRECTION_LOWPRI
) |
2505 MSI_ADDR_DEST_ID(dest
);
2508 MSI_DATA_TRIGGER_EDGE
|
2509 MSI_DATA_LEVEL_ASSERT
|
2510 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2511 MSI_DATA_DELIVERY_FIXED
:
2512 MSI_DATA_DELIVERY_LOWPRI
) |
2513 MSI_DATA_VECTOR(vector
);
2519 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2526 cpus_and(tmp
, mask
, cpu_online_map
);
2527 if (cpus_empty(tmp
))
2530 vector
= assign_irq_vector(irq
);
2534 dest
= cpu_mask_to_apicid(mask
);
2536 read_msi_msg(irq
, &msg
);
2538 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2539 msg
.data
|= MSI_DATA_VECTOR(vector
);
2540 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2541 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2543 write_msi_msg(irq
, &msg
);
2544 irq_desc
[irq
].affinity
= mask
;
2546 #endif /* CONFIG_SMP */
2549 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2550 * which implement the MSI or MSI-X Capability Structure.
2552 static struct irq_chip msi_chip
= {
2554 .unmask
= unmask_msi_irq
,
2555 .mask
= mask_msi_irq
,
2556 .ack
= ack_ioapic_irq
,
2558 .set_affinity
= set_msi_irq_affinity
,
2560 .retrigger
= ioapic_retrigger_irq
,
2563 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2571 ret
= msi_compose_msg(dev
, irq
, &msg
);
2577 set_irq_msi(irq
, desc
);
2578 write_msi_msg(irq
, &msg
);
2580 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2586 void arch_teardown_msi_irq(unsigned int irq
)
2591 #endif /* CONFIG_PCI_MSI */
2594 * Hypertransport interrupt support
2596 #ifdef CONFIG_HT_IRQ
2600 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2602 struct ht_irq_msg msg
;
2603 fetch_ht_irq_msg(irq
, &msg
);
2605 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2606 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2608 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2609 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2611 write_ht_irq_msg(irq
, &msg
);
2614 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2619 cpus_and(tmp
, mask
, cpu_online_map
);
2620 if (cpus_empty(tmp
))
2623 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2625 dest
= cpu_mask_to_apicid(mask
);
2627 target_ht_irq(irq
, dest
);
2628 irq_desc
[irq
].affinity
= mask
;
2632 static struct irq_chip ht_irq_chip
= {
2634 .mask
= mask_ht_irq
,
2635 .unmask
= unmask_ht_irq
,
2636 .ack
= ack_ioapic_irq
,
2638 .set_affinity
= set_ht_irq_affinity
,
2640 .retrigger
= ioapic_retrigger_irq
,
2643 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2647 vector
= assign_irq_vector(irq
);
2649 struct ht_irq_msg msg
;
2654 cpu_set(vector
>> 8, tmp
);
2655 dest
= cpu_mask_to_apicid(tmp
);
2657 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2661 HT_IRQ_LOW_DEST_ID(dest
) |
2662 HT_IRQ_LOW_VECTOR(vector
) |
2663 ((INT_DEST_MODE
== 0) ?
2664 HT_IRQ_LOW_DM_PHYSICAL
:
2665 HT_IRQ_LOW_DM_LOGICAL
) |
2666 HT_IRQ_LOW_RQEOI_EDGE
|
2667 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2668 HT_IRQ_LOW_MT_FIXED
:
2669 HT_IRQ_LOW_MT_ARBITRATED
) |
2670 HT_IRQ_LOW_IRQ_MASKED
;
2672 write_ht_irq_msg(irq
, &msg
);
2674 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2675 handle_edge_irq
, "edge");
2679 #endif /* CONFIG_HT_IRQ */
2681 /* --------------------------------------------------------------------------
2682 ACPI-based IOAPIC Configuration
2683 -------------------------------------------------------------------------- */
2687 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2689 union IO_APIC_reg_00 reg_00
;
2690 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2692 unsigned long flags
;
2696 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2697 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2698 * supports up to 16 on one shared APIC bus.
2700 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2701 * advantage of new APIC bus architecture.
2704 if (physids_empty(apic_id_map
))
2705 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2707 spin_lock_irqsave(&ioapic_lock
, flags
);
2708 reg_00
.raw
= io_apic_read(ioapic
, 0);
2709 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2711 if (apic_id
>= get_physical_broadcast()) {
2712 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2713 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2714 apic_id
= reg_00
.bits
.ID
;
2718 * Every APIC in a system must have a unique ID or we get lots of nice
2719 * 'stuck on smp_invalidate_needed IPI wait' messages.
2721 if (check_apicid_used(apic_id_map
, apic_id
)) {
2723 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2724 if (!check_apicid_used(apic_id_map
, i
))
2728 if (i
== get_physical_broadcast())
2729 panic("Max apic_id exceeded!\n");
2731 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2732 "trying %d\n", ioapic
, apic_id
, i
);
2737 tmp
= apicid_to_cpu_present(apic_id
);
2738 physids_or(apic_id_map
, apic_id_map
, tmp
);
2740 if (reg_00
.bits
.ID
!= apic_id
) {
2741 reg_00
.bits
.ID
= apic_id
;
2743 spin_lock_irqsave(&ioapic_lock
, flags
);
2744 io_apic_write(ioapic
, 0, reg_00
.raw
);
2745 reg_00
.raw
= io_apic_read(ioapic
, 0);
2746 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2749 if (reg_00
.bits
.ID
!= apic_id
) {
2750 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2755 apic_printk(APIC_VERBOSE
, KERN_INFO
2756 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2762 int __init
io_apic_get_version (int ioapic
)
2764 union IO_APIC_reg_01 reg_01
;
2765 unsigned long flags
;
2767 spin_lock_irqsave(&ioapic_lock
, flags
);
2768 reg_01
.raw
= io_apic_read(ioapic
, 1);
2769 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2771 return reg_01
.bits
.version
;
2775 int __init
io_apic_get_redir_entries (int ioapic
)
2777 union IO_APIC_reg_01 reg_01
;
2778 unsigned long flags
;
2780 spin_lock_irqsave(&ioapic_lock
, flags
);
2781 reg_01
.raw
= io_apic_read(ioapic
, 1);
2782 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2784 return reg_01
.bits
.entries
;
2788 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2790 struct IO_APIC_route_entry entry
;
2791 unsigned long flags
;
2793 if (!IO_APIC_IRQ(irq
)) {
2794 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2800 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2801 * Note that we mask (disable) IRQs now -- these get enabled when the
2802 * corresponding device driver registers for this IRQ.
2805 memset(&entry
,0,sizeof(entry
));
2807 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2808 entry
.dest_mode
= INT_DEST_MODE
;
2809 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2810 entry
.trigger
= edge_level
;
2811 entry
.polarity
= active_high_low
;
2815 * IRQs < 16 are already in the irq_2_pin[] map
2818 add_pin_to_irq(irq
, ioapic
, pin
);
2820 entry
.vector
= assign_irq_vector(irq
);
2822 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2823 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2824 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2825 edge_level
, active_high_low
);
2827 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2829 if (!ioapic
&& (irq
< 16))
2830 disable_8259A_irq(irq
);
2832 spin_lock_irqsave(&ioapic_lock
, flags
);
2833 __ioapic_write_entry(ioapic
, pin
, entry
);
2834 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2839 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2843 if (skip_ioapic_setup
)
2846 for (i
= 0; i
< mp_irq_entries
; i
++)
2847 if (mp_irqs
[i
].mpc_irqtype
== mp_INT
&&
2848 mp_irqs
[i
].mpc_srcbusirq
== bus_irq
)
2850 if (i
>= mp_irq_entries
)
2853 *trigger
= irq_trigger(i
);
2854 *polarity
= irq_polarity(i
);
2858 #endif /* CONFIG_ACPI */
2860 static int __init
parse_disable_timer_pin_1(char *arg
)
2862 disable_timer_pin_1
= 1;
2865 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2867 static int __init
parse_enable_timer_pin_1(char *arg
)
2869 disable_timer_pin_1
= -1;
2872 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2874 static int __init
parse_noapic(char *arg
)
2876 /* disable IO-APIC */
2877 disable_ioapic_setup();
2880 early_param("noapic", parse_noapic
);