drivers/net/wireless/b43legacy/b43legacy.h

   1 #ifndef B43legacy_H_
   2 #define B43legacy_H_
   3
   4 #include <linux/hw_random.h>
   5 #include <linux/kernel.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/stringify.h>
   9 #include <linux/netdevice.h>
  10 #include <linux/pci.h>
  11 #include <asm/atomic.h>
  12 #include <linux/io.h>
  13
  14 #include <linux/ssb/ssb.h>
  15 #include <linux/ssb/ssb_driver_chipcommon.h>
  16
  17 #include <linux/wireless.h>
  18 #include <net/mac80211.h>
  19
  20 #include "debugfs.h"
  21 #include "leds.h"
  22 #include "phy.h"
  23
  24
  25 #define B43legacy_IRQWAIT_MAX_RETRIES   100
  26
  27 #define B43legacy_RX_MAX_SSI            60 /* best guess at max ssi */
  28
  29 /* MMIO offsets */
  30 #define B43legacy_MMIO_DMA0_REASON      0x20
  31 #define B43legacy_MMIO_DMA0_IRQ_MASK    0x24
  32 #define B43legacy_MMIO_DMA1_REASON      0x28
  33 #define B43legacy_MMIO_DMA1_IRQ_MASK    0x2C
  34 #define B43legacy_MMIO_DMA2_REASON      0x30
  35 #define B43legacy_MMIO_DMA2_IRQ_MASK    0x34
  36 #define B43legacy_MMIO_DMA3_REASON      0x38
  37 #define B43legacy_MMIO_DMA3_IRQ_MASK    0x3C
  38 #define B43legacy_MMIO_DMA4_REASON      0x40
  39 #define B43legacy_MMIO_DMA4_IRQ_MASK    0x44
  40 #define B43legacy_MMIO_DMA5_REASON      0x48
  41 #define B43legacy_MMIO_DMA5_IRQ_MASK    0x4C
  42 #define B43legacy_MMIO_MACCTL           0x120
  43 #define B43legacy_MMIO_STATUS_BITFIELD  0x120
  44 #define B43legacy_MMIO_STATUS2_BITFIELD 0x124
  45 #define B43legacy_MMIO_GEN_IRQ_REASON   0x128
  46 #define B43legacy_MMIO_GEN_IRQ_MASK     0x12C
  47 #define B43legacy_MMIO_RAM_CONTROL      0x130
  48 #define B43legacy_MMIO_RAM_DATA         0x134
  49 #define B43legacy_MMIO_PS_STATUS                0x140
  50 #define B43legacy_MMIO_RADIO_HWENABLED_HI       0x158
  51 #define B43legacy_MMIO_SHM_CONTROL      0x160
  52 #define B43legacy_MMIO_SHM_DATA         0x164
  53 #define B43legacy_MMIO_SHM_DATA_UNALIGNED       0x166
  54 #define B43legacy_MMIO_XMITSTAT_0               0x170
  55 #define B43legacy_MMIO_XMITSTAT_1               0x174
  56 #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
  57 #define B43legacy_MMIO_REV3PLUS_TSF_HIGH        0x184 /* core rev >= 3 only */
  58
  59 /* 32-bit DMA */
  60 #define B43legacy_MMIO_DMA32_BASE0      0x200
  61 #define B43legacy_MMIO_DMA32_BASE1      0x220
  62 #define B43legacy_MMIO_DMA32_BASE2      0x240
  63 #define B43legacy_MMIO_DMA32_BASE3      0x260
  64 #define B43legacy_MMIO_DMA32_BASE4      0x280
  65 #define B43legacy_MMIO_DMA32_BASE5      0x2A0
  66 /* 64-bit DMA */
  67 #define B43legacy_MMIO_DMA64_BASE0      0x200
  68 #define B43legacy_MMIO_DMA64_BASE1      0x240
  69 #define B43legacy_MMIO_DMA64_BASE2      0x280
  70 #define B43legacy_MMIO_DMA64_BASE3      0x2C0
  71 #define B43legacy_MMIO_DMA64_BASE4      0x300
  72 #define B43legacy_MMIO_DMA64_BASE5      0x340
  73 /* PIO */
  74 #define B43legacy_MMIO_PIO1_BASE                0x300
  75 #define B43legacy_MMIO_PIO2_BASE                0x310
  76 #define B43legacy_MMIO_PIO3_BASE                0x320
  77 #define B43legacy_MMIO_PIO4_BASE                0x330
  78
  79 #define B43legacy_MMIO_PHY_VER          0x3E0
  80 #define B43legacy_MMIO_PHY_RADIO                0x3E2
  81 #define B43legacy_MMIO_PHY0             0x3E6
  82 #define B43legacy_MMIO_ANTENNA          0x3E8
  83 #define B43legacy_MMIO_CHANNEL          0x3F0
  84 #define B43legacy_MMIO_CHANNEL_EXT      0x3F4
  85 #define B43legacy_MMIO_RADIO_CONTROL    0x3F6
  86 #define B43legacy_MMIO_RADIO_DATA_HIGH  0x3F8
  87 #define B43legacy_MMIO_RADIO_DATA_LOW   0x3FA
  88 #define B43legacy_MMIO_PHY_CONTROL      0x3FC
  89 #define B43legacy_MMIO_PHY_DATA         0x3FE
  90 #define B43legacy_MMIO_MACFILTER_CONTROL        0x420
  91 #define B43legacy_MMIO_MACFILTER_DATA   0x422
  92 #define B43legacy_MMIO_RCMTA_COUNT      0x43C /* Receive Match Transmitter Addr */
  93 #define B43legacy_MMIO_RADIO_HWENABLED_LO       0x49A
  94 #define B43legacy_MMIO_GPIO_CONTROL     0x49C
  95 #define B43legacy_MMIO_GPIO_MASK                0x49E
  96 #define B43legacy_MMIO_TSF_0            0x632 /* core rev < 3 only */
  97 #define B43legacy_MMIO_TSF_1            0x634 /* core rev < 3 only */
  98 #define B43legacy_MMIO_TSF_2            0x636 /* core rev < 3 only */
  99 #define B43legacy_MMIO_TSF_3            0x638 /* core rev < 3 only */
 100 #define B43legacy_MMIO_RNG              0x65A
 101 #define B43legacy_MMIO_POWERUP_DELAY    0x6A8
 102
 103 /* SPROM boardflags_lo values */
 104 #define B43legacy_BFL_PACTRL            0x0002
 105 #define B43legacy_BFL_RSSI              0x0008
 106 #define B43legacy_BFL_EXTLNA            0x1000
 107
 108 /* GPIO register offset, in both ChipCommon and PCI core. */
 109 #define B43legacy_GPIO_CONTROL          0x6c
 110
 111 /* SHM Routing */
 112 #define B43legacy_SHM_SHARED            0x0001
 113 #define B43legacy_SHM_WIRELESS          0x0002
 114 #define B43legacy_SHM_HW                0x0004
 115 #define B43legacy_SHM_UCODE             0x0300
 116
 117 /* SHM Routing modifiers */
 118 #define B43legacy_SHM_AUTOINC_R         0x0200 /* Read Auto-increment */
 119 #define B43legacy_SHM_AUTOINC_W         0x0100 /* Write Auto-increment */
 120 #define B43legacy_SHM_AUTOINC_RW        (B43legacy_SHM_AUTOINC_R | \
 121                                          B43legacy_SHM_AUTOINC_W)
 122
 123 /* Misc SHM_SHARED offsets */
 124 #define B43legacy_SHM_SH_WLCOREREV      0x0016 /* 802.11 core revision */
 125 #define B43legacy_SHM_SH_HOSTFLO        0x005E /* Hostflags ucode opts (low) */
 126 #define B43legacy_SHM_SH_HOSTFHI        0x0060 /* Hostflags ucode opts (high) */
 127 /* SHM_SHARED crypto engine */
 128 #define B43legacy_SHM_SH_KEYIDXBLOCK    0x05D4 /* Key index/algorithm block */
 129 /* SHM_SHARED beacon variables */
 130 #define B43legacy_SHM_SH_BEACPHYCTL     0x0054 /* Beacon PHY TX control word */
 131 /* SHM_SHARED ACK/CTS control */
 132 #define B43legacy_SHM_SH_ACKCTSPHYCTL   0x0022 /* ACK/CTS PHY control word */
 133 /* SHM_SHARED probe response variables */
 134 #define B43legacy_SHM_SH_PRPHYCTL       0x0188 /* Probe Resp PHY TX control */
 135 #define B43legacy_SHM_SH_PRMAXTIME      0x0074 /* Probe Response max time */
 136 /* SHM_SHARED rate tables */
 137 /* SHM_SHARED microcode soft registers */
 138 #define B43legacy_SHM_SH_UCODEREV       0x0000 /* Microcode revision */
 139 #define B43legacy_SHM_SH_UCODEPATCH     0x0002 /* Microcode patchlevel */
 140 #define B43legacy_SHM_SH_UCODEDATE      0x0004 /* Microcode date */
 141 #define B43legacy_SHM_SH_UCODETIME      0x0006 /* Microcode time */
 142
 143 #define B43legacy_UCODEFLAGS_OFFSET     0x005E
 144
 145 /* Hardware Radio Enable masks */
 146 #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
 147 #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
 148
 149 /* HostFlags. See b43legacy_hf_read/write() */
 150 #define B43legacy_HF_SYMW               0x00000002 /* G-PHY SYM workaround */
 151 #define B43legacy_HF_GDCW               0x00000020 /* G-PHY DV cancel filter */
 152 #define B43legacy_HF_OFDMPABOOST        0x00000040 /* Enable PA boost OFDM */
 153 #define B43legacy_HF_EDCF               0x00000100 /* on if WME/MAC suspended */
 154
 155 /* MacFilter offsets. */
 156 #define B43legacy_MACFILTER_SELF        0x0000
 157 #define B43legacy_MACFILTER_BSSID       0x0003
 158 #define B43legacy_MACFILTER_MAC         0x0010
 159
 160 /* PHYVersioning */
 161 #define B43legacy_PHYTYPE_B             0x01
 162 #define B43legacy_PHYTYPE_G             0x02
 163
 164 /* PHYRegisters */
 165 #define B43legacy_PHY_G_LO_CONTROL      0x0810
 166 #define B43legacy_PHY_ILT_G_CTRL        0x0472
 167 #define B43legacy_PHY_ILT_G_DATA1       0x0473
 168 #define B43legacy_PHY_ILT_G_DATA2       0x0474
 169 #define B43legacy_PHY_G_PCTL            0x0029
 170 #define B43legacy_PHY_RADIO_BITFIELD    0x0401
 171 #define B43legacy_PHY_G_CRS             0x0429
 172 #define B43legacy_PHY_NRSSILT_CTRL      0x0803
 173 #define B43legacy_PHY_NRSSILT_DATA      0x0804
 174
 175 /* RadioRegisters */
 176 #define B43legacy_RADIOCTL_ID           0x01
 177
 178 /* MAC Control bitfield */
 179 #define B43legacy_MACCTL_IHR_ENABLED    0x00000400 /* IHR Region Enabled */
 180 #define B43legacy_MACCTL_INFRA          0x00020000 /* Infrastructure mode */
 181 #define B43legacy_MACCTL_AP             0x00040000 /* AccessPoint mode */
 182 #define B43legacy_MACCTL_KEEP_BADPLCP   0x00200000 /* Keep bad PLCP frames */
 183 #define B43legacy_MACCTL_KEEP_CTL       0x00400000 /* Keep control frames */
 184 #define B43legacy_MACCTL_KEEP_BAD       0x00800000 /* Keep bad frames (FCS) */
 185 #define B43legacy_MACCTL_PROMISC        0x01000000 /* Promiscuous mode */
 186 #define B43legacy_MACCTL_GMODE          0x80000000 /* G Mode */
 187
 188 /* StatusBitField */
 189 #define B43legacy_SBF_MAC_ENABLED       0x00000001
 190 #define B43legacy_SBF_CORE_READY        0x00000004
 191 #define B43legacy_SBF_400               0x00000400 /*FIXME: fix name*/
 192 #define B43legacy_SBF_XFER_REG_BYTESWAP 0x00010000
 193 #define B43legacy_SBF_MODE_NOTADHOC     0x00020000
 194 #define B43legacy_SBF_MODE_AP           0x00040000
 195 #define B43legacy_SBF_RADIOREG_LOCK     0x00080000
 196 #define B43legacy_SBF_MODE_MONITOR      0x00400000
 197 #define B43legacy_SBF_MODE_PROMISC      0x01000000
 198 #define B43legacy_SBF_PS1               0x02000000
 199 #define B43legacy_SBF_PS2               0x04000000
 200 #define B43legacy_SBF_NO_SSID_BCAST     0x08000000
 201 #define B43legacy_SBF_TIME_UPDATE       0x10000000
 202
 203 /* 802.11 core specific TM State Low flags */
 204 #define B43legacy_TMSLOW_GMODE          0x20000000 /* G Mode Enable */
 205 #define B43legacy_TMSLOW_PLLREFSEL      0x00200000 /* PLL Freq Ref Select */
 206 #define B43legacy_TMSLOW_MACPHYCLKEN    0x00100000 /* MAC PHY Clock Ctrl Enbl */
 207 #define B43legacy_TMSLOW_PHYRESET       0x00080000 /* PHY Reset */
 208 #define B43legacy_TMSLOW_PHYCLKEN       0x00040000 /* PHY Clock Enable */
 209
 210 /* 802.11 core specific TM State High flags */
 211 #define B43legacy_TMSHIGH_FCLOCK        0x00040000 /* Fast Clock Available */
 212 #define B43legacy_TMSHIGH_GPHY          0x00010000 /* G-PHY avail (rev >= 5) */
 213
 214 #define B43legacy_UCODEFLAG_AUTODIV       0x0001
 215
 216 /* Generic-Interrupt reasons. */
 217 #define B43legacy_IRQ_MAC_SUSPENDED     0x00000001
 218 #define B43legacy_IRQ_BEACON            0x00000002
 219 #define B43legacy_IRQ_TBTT_INDI         0x00000004 /* Target Beacon Transmit Time */
 220 #define B43legacy_IRQ_BEACON_TX_OK      0x00000008
 221 #define B43legacy_IRQ_BEACON_CANCEL     0x00000010
 222 #define B43legacy_IRQ_ATIM_END          0x00000020
 223 #define B43legacy_IRQ_PMQ               0x00000040
 224 #define B43legacy_IRQ_PIO_WORKAROUND    0x00000100
 225 #define B43legacy_IRQ_MAC_TXERR         0x00000200
 226 #define B43legacy_IRQ_PHY_TXERR         0x00000800
 227 #define B43legacy_IRQ_PMEVENT           0x00001000
 228 #define B43legacy_IRQ_TIMER0            0x00002000
 229 #define B43legacy_IRQ_TIMER1            0x00004000
 230 #define B43legacy_IRQ_DMA               0x00008000
 231 #define B43legacy_IRQ_TXFIFO_FLUSH_OK   0x00010000
 232 #define B43legacy_IRQ_CCA_MEASURE_OK    0x00020000
 233 #define B43legacy_IRQ_NOISESAMPLE_OK    0x00040000
 234 #define B43legacy_IRQ_UCODE_DEBUG       0x08000000
 235 #define B43legacy_IRQ_RFKILL            0x10000000
 236 #define B43legacy_IRQ_TX_OK             0x20000000
 237 #define B43legacy_IRQ_PHY_G_CHANGED     0x40000000
 238 #define B43legacy_IRQ_TIMEOUT           0x80000000
 239
 240 #define B43legacy_IRQ_ALL               0xFFFFFFFF
 241 #define B43legacy_IRQ_MASKTEMPLATE      (B43legacy_IRQ_MAC_SUSPENDED |  \
 242                                          B43legacy_IRQ_BEACON |         \
 243                                          B43legacy_IRQ_TBTT_INDI |      \
 244                                          B43legacy_IRQ_ATIM_END |       \
 245                                          B43legacy_IRQ_PMQ |            \
 246                                          B43legacy_IRQ_MAC_TXERR |      \
 247                                          B43legacy_IRQ_PHY_TXERR |      \
 248                                          B43legacy_IRQ_DMA |            \
 249                                          B43legacy_IRQ_TXFIFO_FLUSH_OK | \
 250                                          B43legacy_IRQ_NOISESAMPLE_OK | \
 251                                          B43legacy_IRQ_UCODE_DEBUG |    \
 252                                          B43legacy_IRQ_RFKILL |         \
 253                                          B43legacy_IRQ_TX_OK)
 254
 255 /* Device specific rate values.
 256  * The actual values defined here are (rate_in_mbps * 2).
 257  * Some code depends on this. Don't change it. */
 258 #define B43legacy_CCK_RATE_1MB          2
 259 #define B43legacy_CCK_RATE_2MB          4
 260 #define B43legacy_CCK_RATE_5MB          11
 261 #define B43legacy_CCK_RATE_11MB         22
 262 #define B43legacy_OFDM_RATE_6MB         12
 263 #define B43legacy_OFDM_RATE_9MB         18
 264 #define B43legacy_OFDM_RATE_12MB        24
 265 #define B43legacy_OFDM_RATE_18MB        36
 266 #define B43legacy_OFDM_RATE_24MB        48
 267 #define B43legacy_OFDM_RATE_36MB        72
 268 #define B43legacy_OFDM_RATE_48MB        96
 269 #define B43legacy_OFDM_RATE_54MB        108
 270 /* Convert a b43legacy rate value to a rate in 100kbps */
 271 #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2)
 272
 273
 274 #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT     7
 275 #define B43legacy_DEFAULT_LONG_RETRY_LIMIT      4
 276
 277 /* Max size of a security key */
 278 #define B43legacy_SEC_KEYSIZE           16
 279 /* Security algorithms. */
 280 enum {
 281         B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
 282         B43legacy_SEC_ALGO_WEP40,
 283         B43legacy_SEC_ALGO_TKIP,
 284         B43legacy_SEC_ALGO_AES,
 285         B43legacy_SEC_ALGO_WEP104,
 286         B43legacy_SEC_ALGO_AES_LEGACY,
 287 };
 288
 289 /* Core Information Registers */
 290 #define B43legacy_CIR_BASE                0xf00
 291 #define B43legacy_CIR_SBTPSFLAG           (B43legacy_CIR_BASE + 0x18)
 292 #define B43legacy_CIR_SBIMSTATE           (B43legacy_CIR_BASE + 0x90)
 293 #define B43legacy_CIR_SBINTVEC            (B43legacy_CIR_BASE + 0x94)
 294 #define B43legacy_CIR_SBTMSTATELOW        (B43legacy_CIR_BASE + 0x98)
 295 #define B43legacy_CIR_SBTMSTATEHIGH       (B43legacy_CIR_BASE + 0x9c)
 296 #define B43legacy_CIR_SBIMCONFIGLOW       (B43legacy_CIR_BASE + 0xa8)
 297 #define B43legacy_CIR_SB_ID_HI            (B43legacy_CIR_BASE + 0xfc)
 298
 299 /* sbtmstatehigh state flags */
 300 #define B43legacy_SBTMSTATEHIGH_SERROR          0x00000001
 301 #define B43legacy_SBTMSTATEHIGH_BUSY            0x00000004
 302 #define B43legacy_SBTMSTATEHIGH_TIMEOUT         0x00000020
 303 #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL     0x00010000
 304 #define B43legacy_SBTMSTATEHIGH_COREFLAGS       0x1FFF0000
 305 #define B43legacy_SBTMSTATEHIGH_DMA64BIT        0x10000000
 306 #define B43legacy_SBTMSTATEHIGH_GATEDCLK        0x20000000
 307 #define B43legacy_SBTMSTATEHIGH_BISTFAILED      0x40000000
 308 #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE    0x80000000
 309
 310 /* sbimstate flags */
 311 #define B43legacy_SBIMSTATE_IB_ERROR            0x20000
 312 #define B43legacy_SBIMSTATE_TIMEOUT             0x40000
 313
 314 #define PFX             KBUILD_MODNAME ": "
 315 #ifdef assert
 316 # undef assert
 317 #endif
 318 #ifdef CONFIG_B43LEGACY_DEBUG
 319 # define B43legacy_WARN_ON(expr)                                        \
 320         do {                                                            \
 321                 if (unlikely((expr))) {                                 \
 322                         printk(KERN_INFO PFX "Test (%s) failed at:"     \
 323                                               " %s:%d:%s()\n",          \
 324                                               #expr, __FILE__,          \
 325                                               __LINE__, __FUNCTION__);  \
 326                 }                                                       \
 327         } while (0)
 328 # define B43legacy_BUG_ON(expr)                                         \
 329         do {                                                            \
 330                 if (unlikely((expr))) {                                 \
 331                         printk(KERN_INFO PFX "Test (%s) failed\n",      \
 332                                               #expr);                   \
 333                         BUG_ON(expr);                                   \
 334                 }                                                       \
 335         } while (0)
 336 # define B43legacy_DEBUG        1
 337 #else
 338 # define B43legacy_WARN_ON(x)   do { /* nothing */ } while (0)
 339 # define B43legacy_BUG_ON(x)    do { /* nothing */ } while (0)
 340 # define B43legacy_DEBUG        0
 341 #endif
 342
 343
 344 struct net_device;
 345 struct pci_dev;
 346 struct b43legacy_dmaring;
 347 struct b43legacy_pioqueue;
 348
 349 /* The firmware file header */
 350 #define B43legacy_FW_TYPE_UCODE 'u'
 351 #define B43legacy_FW_TYPE_PCM   'p'
 352 #define B43legacy_FW_TYPE_IV    'i'
 353 struct b43legacy_fw_header {
 354         /* File type */
 355         u8 type;
 356         /* File format version */
 357         u8 ver;
 358         u8 __padding[2];
 359         /* Size of the data. For ucode and PCM this is in bytes.
 360          * For IV this is number-of-ivs. */
 361         __be32 size;
 362 } __attribute__((__packed__));
 363
 364 /* Initial Value file format */
 365 #define B43legacy_IV_OFFSET_MASK        0x7FFF
 366 #define B43legacy_IV_32BIT              0x8000
 367 struct b43legacy_iv {
 368         __be16 offset_size;
 369         union {
 370                 __be16 d16;
 371                 __be32 d32;
 372         } data __attribute__((__packed__));
 373 } __attribute__((__packed__));
 374
 375 #define B43legacy_PHYMODE(phytype)      (1 << (phytype))
 376 #define B43legacy_PHYMODE_B             B43legacy_PHYMODE       \
 377                                         ((B43legacy_PHYTYPE_B))
 378 #define B43legacy_PHYMODE_G             B43legacy_PHYMODE       \
 379                                         ((B43legacy_PHYTYPE_G))
 380
 381 /* Value pair to measure the LocalOscillator. */
 382 struct b43legacy_lopair {
 383         s8 low;
 384         s8 high;
 385         u8 used:1;
 386 };
 387 #define B43legacy_LO_COUNT      (14*4)
 388
 389 struct b43legacy_phy {
 390         /* Possible PHYMODEs on this PHY */
 391         u8 possible_phymodes;
 392         /* GMODE bit enabled in MACCTL? */
 393         bool gmode;
 394         /* Possible ieee80211 subsystem hwmodes for this PHY.
 395          * Which mode is selected, depends on thr GMODE enabled bit */
 396 #define B43legacy_MAX_PHYHWMODES        2
 397         struct ieee80211_hw_mode hwmodes[B43legacy_MAX_PHYHWMODES];
 398
 399         /* Analog Type */
 400         u8 analog;
 401         /* B43legacy_PHYTYPE_ */
 402         u8 type;
 403         /* PHY revision number. */
 404         u8 rev;
 405
 406         u16 antenna_diversity;
 407         u16 savedpctlreg;
 408         /* Radio versioning */
 409         u16 radio_manuf;        /* Radio manufacturer */
 410         u16 radio_ver;          /* Radio version */
 411         u8 calibrated:1;
 412         u8 radio_rev;           /* Radio revision */
 413
 414         bool radio_on;          /* Radio switched on/off */
 415         bool locked;            /* Only used in b43legacy_phy_{un}lock() */
 416         bool dyn_tssi_tbl;      /* tssi2dbm is kmalloc()ed. */
 417
 418         /* ACI (adjacent channel interference) flags. */
 419         bool aci_enable;
 420         bool aci_wlan_automatic;
 421         bool aci_hw_rssi;
 422
 423         u16 minlowsig[2];
 424         u16 minlowsigpos[2];
 425
 426         /* LO Measurement Data.
 427          * Use b43legacy_get_lopair() to get a value.
 428          */
 429         struct b43legacy_lopair *_lo_pairs;
 430         /* TSSI to dBm table in use */
 431         const s8 *tssi2dbm;
 432         /* idle TSSI value */
 433         s8 idle_tssi;
 434         /* Target idle TSSI */
 435         int tgt_idle_tssi;
 436         /* Current idle TSSI */
 437         int cur_idle_tssi;
 438
 439         /* LocalOscillator control values. */
 440         struct b43legacy_txpower_lo_control *lo_control;
 441         /* Values from b43legacy_calc_loopback_gain() */
 442         s16 max_lb_gain;        /* Maximum Loopback gain in hdB */
 443         s16 trsw_rx_gain;       /* TRSW RX gain in hdB */
 444         s16 lna_lod_gain;       /* LNA lod */
 445         s16 lna_gain;           /* LNA */
 446         s16 pga_gain;           /* PGA */
 447
 448         /* PHY lock for core.rev < 3
 449          * This lock is only used by b43legacy_phy_{un}lock()
 450          */
 451         spinlock_t lock;
 452
 453         /* Desired TX power level (in dBm). This is set by the user and
 454          * adjusted in b43legacy_phy_xmitpower(). */
 455         u8 power_level;
 456
 457         /* Values from b43legacy_calc_loopback_gain() */
 458         u16 loopback_gain[2];
 459
 460         /* TX Power control values. */
 461         /* B/G PHY */
 462         struct {
 463                 /* Current Radio Attenuation for TXpower recalculation. */
 464                 u16 rfatt;
 465                 /* Current Baseband Attenuation for TXpower recalculation. */
 466                 u16 bbatt;
 467                 /* Current TXpower control value for TXpower recalculation. */
 468                 u16 txctl1;
 469                 u16 txctl2;
 470         };
 471         /* A PHY */
 472         struct {
 473                 u16 txpwr_offset;
 474         };
 475
 476 #ifdef CONFIG_B43LEGACY_DEBUG
 477         bool manual_txpower_control; /* Manual TX-power control enabled? */
 478 #endif
 479         /* Current Interference Mitigation mode */
 480         int interfmode;
 481         /* Stack of saved values from the Interference Mitigation code.
 482          * Each value in the stack is layed out as follows:
 483          * bit 0-11:  offset
 484          * bit 12-15: register ID
 485          * bit 16-32: value
 486          * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
 487          */
 488 #define B43legacy_INTERFSTACK_SIZE      26
 489         u32 interfstack[B43legacy_INTERFSTACK_SIZE];
 490
 491         /* Saved values from the NRSSI Slope calculation */
 492         s16 nrssi[2];
 493         s32 nrssislope;
 494         /* In memory nrssi lookup table. */
 495         s8 nrssi_lt[64];
 496
 497         /* current channel */
 498         u8 channel;
 499
 500         u16 lofcal;
 501
 502         u16 initval;
 503 };
 504
 505 /* Data structures for DMA transmission, per 80211 core. */
 506 struct b43legacy_dma {
 507         struct b43legacy_dmaring *tx_ring0;
 508         struct b43legacy_dmaring *tx_ring1;
 509         struct b43legacy_dmaring *tx_ring2;
 510         struct b43legacy_dmaring *tx_ring3;
 511         struct b43legacy_dmaring *tx_ring4;
 512         struct b43legacy_dmaring *tx_ring5;
 513
 514         struct b43legacy_dmaring *rx_ring0;
 515         struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
 516 };
 517
 518 /* Data structures for PIO transmission, per 80211 core. */
 519 struct b43legacy_pio {
 520         struct b43legacy_pioqueue *queue0;
 521         struct b43legacy_pioqueue *queue1;
 522         struct b43legacy_pioqueue *queue2;
 523         struct b43legacy_pioqueue *queue3;
 524 };
 525
 526 /* Context information for a noise calculation (Link Quality). */
 527 struct b43legacy_noise_calculation {
 528         u8 channel_at_start;
 529         bool calculation_running;
 530         u8 nr_samples;
 531         s8 samples[8][4];
 532 };
 533
 534 struct b43legacy_stats {
 535         u8 link_noise;
 536         /* Store the last TX/RX times here for updating the leds. */
 537         unsigned long last_tx;
 538         unsigned long last_rx;
 539 };
 540
 541 struct b43legacy_key {
 542         void *keyconf;
 543         bool enabled;
 544         u8 algorithm;
 545 };
 546
 547 struct b43legacy_wldev;
 548
 549 /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */
 550 struct b43legacy_wl {
 551         /* Pointer to the active wireless device on this chip */
 552         struct b43legacy_wldev *current_dev;
 553         /* Pointer to the ieee80211 hardware data structure */
 554         struct ieee80211_hw *hw;
 555
 556         spinlock_t irq_lock;            /* locks IRQ */
 557         struct mutex mutex;             /* locks wireless core state */
 558         spinlock_t leds_lock;           /* lock for leds */
 559
 560         /* We can only have one operating interface (802.11 core)
 561          * at a time. General information about this interface follows.
 562          */
 563
 564         /* Opaque ID of the operating interface (!= monitor
 565          * interface) from the ieee80211 subsystem.
 566          * Do not modify.
 567          */
 568         int if_id;
 569         /* MAC address (can be NULL). */
 570         const u8 *mac_addr;
 571         /* Current BSSID (can be NULL). */
 572         const u8 *bssid;
 573         /* Interface type. (IEEE80211_IF_TYPE_XXX) */
 574         int if_type;
 575         /* Counter of active monitor interfaces. */
 576         int monitor;
 577         /* Is the card operating in AP, STA or IBSS mode? */
 578         bool operating;
 579         /* Promisc mode active?
 580          * Note that (monitor != 0) implies promisc.
 581          */
 582         bool promisc;
 583         /* Stats about the wireless interface */
 584         struct ieee80211_low_level_stats ieee_stats;
 585
 586         struct hwrng rng;
 587         u8 rng_initialized;
 588         char rng_name[30 + 1];
 589
 590         /* List of all wireless devices on this chip */
 591         struct list_head devlist;
 592         u8 nr_devs;
 593 };
 594
 595 /* Pointers to the firmware data and meta information about it. */
 596 struct b43legacy_firmware {
 597         /* Microcode */
 598         const struct firmware *ucode;
 599         /* PCM code */
 600         const struct firmware *pcm;
 601         /* Initial MMIO values for the firmware */
 602         const struct firmware *initvals;
 603         /* Initial MMIO values for the firmware, band-specific */
 604         const struct firmware *initvals_band;
 605         /* Firmware revision */
 606         u16 rev;
 607         /* Firmware patchlevel */
 608         u16 patch;
 609 };
 610
 611 /* Device (802.11 core) initialization status. */
 612 enum {
 613         B43legacy_STAT_UNINIT           = 0, /* Uninitialized. */
 614         B43legacy_STAT_INITIALIZED      = 1, /* Initialized, not yet started. */
 615         B43legacy_STAT_STARTED  = 2, /* Up and running. */
 616 };
 617 #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status)
 618 #define b43legacy_set_status(wldev, stat)       do {            \
 619                 atomic_set(&(wldev)->__init_status, (stat));    \
 620                 smp_wmb();                                      \
 621                                         } while (0)
 622
 623 /* *** ---   HOW LOCKING WORKS IN B43legacy   --- ***
 624  *
 625  * You should always acquire both, wl->mutex and wl->irq_lock unless:
 626  * - You don't need to acquire wl->irq_lock, if the interface is stopped.
 627  * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
 628  *   and packet TX path (and _ONLY_ there.)
 629  */
 630
 631 /* Data structure for one wireless device (802.11 core) */
 632 struct b43legacy_wldev {
 633         struct ssb_device *dev;
 634         struct b43legacy_wl *wl;
 635
 636         /* The device initialization status.
 637          * Use b43legacy_status() to query. */
 638         atomic_t __init_status;
 639         /* Saved init status for handling suspend. */
 640         int suspend_init_status;
 641
 642         bool __using_pio;       /* Using pio rather than dma. */
 643         bool bad_frames_preempt;/* Use "Bad Frames Preemption". */
 644         bool reg124_set_0x4;    /* Variable to keep track of IRQ. */
 645         bool short_preamble;    /* TRUE if using short preamble. */
 646         bool short_slot;        /* TRUE if using short slot timing. */
 647         bool radio_hw_enable;   /* State of radio hardware enable bit. */
 648
 649         /* PHY/Radio device. */
 650         struct b43legacy_phy phy;
 651         union {
 652                 /* DMA engines. */
 653                 struct b43legacy_dma dma;
 654                 /* PIO engines. */
 655                 struct b43legacy_pio pio;
 656         };
 657
 658         /* Various statistics about the physical device. */
 659         struct b43legacy_stats stats;
 660
 661 #define B43legacy_NR_LEDS               4
 662         struct b43legacy_led leds[B43legacy_NR_LEDS];
 663
 664         /* Reason code of the last interrupt. */
 665         u32 irq_reason;
 666         u32 dma_reason[6];
 667         /* saved irq enable/disable state bitfield. */
 668         u32 irq_savedstate;
 669         /* Link Quality calculation context. */
 670         struct b43legacy_noise_calculation noisecalc;
 671         /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
 672         int mac_suspended;
 673
 674         /* Interrupt Service Routine tasklet (bottom-half) */
 675         struct tasklet_struct isr_tasklet;
 676
 677         /* Periodic tasks */
 678         struct delayed_work periodic_work;
 679         unsigned int periodic_state;
 680
 681         struct work_struct restart_work;
 682
 683         /* encryption/decryption */
 684         u16 ktp; /* Key table pointer */
 685         u8 max_nr_keys;
 686         struct b43legacy_key key[58];
 687
 688         /* Cached beacon template while uploading the template. */
 689         struct sk_buff *cached_beacon;
 690
 691         /* Firmware data */
 692         struct b43legacy_firmware fw;
 693
 694         /* Devicelist in struct b43legacy_wl (all 802.11 cores) */
 695         struct list_head list;
 696
 697         /* Debugging stuff follows. */
 698 #ifdef CONFIG_B43LEGACY_DEBUG
 699         struct b43legacy_dfsentry *dfsentry;
 700 #endif
 701 };
 702
 703
 704 static inline
 705 struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw)
 706 {
 707         return hw->priv;
 708 }
 709
 710 /* Helper function, which returns a boolean.
 711  * TRUE, if PIO is used; FALSE, if DMA is used.
 712  */
 713 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
 714 static inline
 715 int b43legacy_using_pio(struct b43legacy_wldev *dev)
 716 {
 717         return dev->__using_pio;
 718 }
 719 #elif defined(CONFIG_B43LEGACY_DMA)
 720 static inline
 721 int b43legacy_using_pio(struct b43legacy_wldev *dev)
 722 {
 723         return 0;
 724 }
 725 #elif defined(CONFIG_B43LEGACY_PIO)
 726 static inline
 727 int b43legacy_using_pio(struct b43legacy_wldev *dev)
 728 {
 729         return 1;
 730 }
 731 #else
 732 # error "Using neither DMA nor PIO? Confused..."
 733 #endif
 734
 735
 736 static inline
 737 struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev)
 738 {
 739         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 740         return ssb_get_drvdata(ssb_dev);
 741 }
 742
 743 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
 744 static inline
 745 int b43legacy_is_mode(struct b43legacy_wl *wl, int type)
 746 {
 747         if (type == IEEE80211_IF_TYPE_MNTR)
 748                 return !!(wl->monitor);
 749         return (wl->operating &&
 750                 wl->if_type == type);
 751 }
 752
 753 static inline
 754 bool is_bcm_board_vendor(struct b43legacy_wldev *dev)
 755 {
 756         return  (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM);
 757 }
 758
 759 static inline
 760 u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset)
 761 {
 762         return ssb_read16(dev->dev, offset);
 763 }
 764
 765 static inline
 766 void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value)
 767 {
 768         ssb_write16(dev->dev, offset, value);
 769 }
 770
 771 static inline
 772 u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset)
 773 {
 774         return ssb_read32(dev->dev, offset);
 775 }
 776
 777 static inline
 778 void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value)
 779 {
 780         ssb_write32(dev->dev, offset, value);
 781 }
 782
 783 static inline
 784 struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy,
 785                                               u16 radio_attenuation,
 786                                               u16 baseband_attenuation)
 787 {
 788         return phy->_lo_pairs + (radio_attenuation
 789                         + 14 * (baseband_attenuation / 2));
 790 }
 791
 792
 793
 794 /* Message printing */
 795 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
 796                 __attribute__((format(printf, 2, 3)));
 797 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
 798                 __attribute__((format(printf, 2, 3)));
 799 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
 800                 __attribute__((format(printf, 2, 3)));
 801 #if B43legacy_DEBUG
 802 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
 803                 __attribute__((format(printf, 2, 3)));
 804 #else /* DEBUG */
 805 # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
 806 #endif /* DEBUG */
 807
 808
 809 /** Limit a value between two limits */
 810 #ifdef limit_value
 811 # undef limit_value
 812 #endif
 813 #define limit_value(value, min, max)  \
 814         ({                                              \
 815                 typeof(value) __value = (value);        \
 816                 typeof(value) __min = (min);            \
 817                 typeof(value) __max = (max);            \
 818                 if (__value < __min)                    \
 819                         __value = __min;                \
 820                 else if (__value > __max)               \
 821                         __value = __max;                \
 822                 __value;                                \
 823         })
 824
 825 /* Macros for printing a value in Q5.2 format */
 826 #define Q52_FMT         "%u.%u"
 827 #define Q52_ARG(q52)    ((q52) / 4), (((q52) & 3) * 100 / 4)
 828
 829 #endif /* B43legacy_H_ */