arch/powerpc/platforms/8xx/m8xx_setup.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  *  Adapted from 'alpha' version by Gary Thomas
   4  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   5  *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
   6  *  Further modified for generic 8xx by Dan.
   7  */
   8
   9 /*
  10  * bootup setup stuff..
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/init.h>
  17 #include <linux/time.h>
  18 #include <linux/rtc.h>
  19 #include <linux/fsl_devices.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/mpc8xx.h>
  23 #include <asm/8xx_immap.h>
  24 #include <asm/prom.h>
  25 #include <asm/fs_pd.h>
  26 #include <mm/mmu_decl.h>
  27
  28 #include <sysdev/mpc8xx_pic.h>
  29
  30 #include "mpc8xx.h"
  31
  32 struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
  33
  34 extern int cpm_pic_init(void);
  35 extern int cpm_get_irq(void);
  36
  37 /* A place holder for time base interrupts, if they are ever enabled. */
  38 static irqreturn_t timebase_interrupt(int irq, void *dev)
  39 {
  40         printk ("timebase_interrupt()\n");
  41
  42         return IRQ_HANDLED;
  43 }
  44
  45 static struct irqaction tbint_irqaction = {
  46         .handler = timebase_interrupt,
  47         .name = "tbint",
  48 };
  49
  50 /* per-board overridable init_internal_rtc() function. */
  51 void __init __attribute__ ((weak))
  52 init_internal_rtc(void)
  53 {
  54         sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
  55
  56         /* Disable the RTC one second and alarm interrupts. */
  57         clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
  58
  59         /* Enable the RTC */
  60         setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
  61         immr_unmap(sys_tmr);
  62 }
  63
  64 static int __init get_freq(char *name, unsigned long *val)
  65 {
  66         struct device_node *cpu;
  67         const unsigned int *fp;
  68         int found = 0;
  69
  70         /* The cpu node should have timebase and clock frequency properties */
  71         cpu = of_find_node_by_type(NULL, "cpu");
  72
  73         if (cpu) {
  74                 fp = of_get_property(cpu, name, NULL);
  75                 if (fp) {
  76                         found = 1;
  77                         *val = *fp;
  78                 }
  79
  80                 of_node_put(cpu);
  81         }
  82
  83         return found;
  84 }
  85
  86 /* The decrementer counts at the system (internal) clock frequency divided by
  87  * sixteen, or external oscillator divided by four.  We force the processor
  88  * to use system clock divided by sixteen.
  89  */
  90 void __init mpc8xx_calibrate_decr(void)
  91 {
  92         struct device_node *cpu;
  93         cark8xx_t __iomem *clk_r1;
  94         car8xx_t __iomem *clk_r2;
  95         sitk8xx_t __iomem *sys_tmr1;
  96         sit8xx_t __iomem *sys_tmr2;
  97         int irq, virq;
  98
  99         clk_r1 = immr_map(im_clkrstk);
 100
 101         /* Unlock the SCCR. */
 102         out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
 103         out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
 104         immr_unmap(clk_r1);
 105
 106         /* Force all 8xx processors to use divide by 16 processor clock. */
 107         clk_r2 = immr_map(im_clkrst);
 108         setbits32(&clk_r2->car_sccr, 0x02000000);
 109         immr_unmap(clk_r2);
 110
 111         /* Processor frequency is MHz.
 112          */
 113         ppc_proc_freq = 50000000;
 114         if (!get_freq("clock-frequency", &ppc_proc_freq))
 115                 printk(KERN_ERR "WARNING: Estimating processor frequency "
 116                                 "(not found)\n");
 117
 118         ppc_tb_freq = ppc_proc_freq / 16;
 119         printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
 120
 121         /* Perform some more timer/timebase initialization.  This used
 122          * to be done elsewhere, but other changes caused it to get
 123          * called more than once....that is a bad thing.
 124          *
 125          * First, unlock all of the registers we are going to modify.
 126          * To protect them from corruption during power down, registers
 127          * that are maintained by keep alive power are "locked".  To
 128          * modify these registers we have to write the key value to
 129          * the key location associated with the register.
 130          * Some boards power up with these unlocked, while others
 131          * are locked.  Writing anything (including the unlock code?)
 132          * to the unlocked registers will lock them again.  So, here
 133          * we guarantee the registers are locked, then we unlock them
 134          * for our use.
 135          */
 136         sys_tmr1 = immr_map(im_sitk);
 137         out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
 138         out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
 139         out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
 140         out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
 141         out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
 142         out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
 143         immr_unmap(sys_tmr1);
 144
 145         init_internal_rtc();
 146
 147         /* Enabling the decrementer also enables the timebase interrupts
 148          * (or from the other point of view, to get decrementer interrupts
 149          * we have to enable the timebase).  The decrementer interrupt
 150          * is wired into the vector table, nothing to do here for that.
 151          */
 152         cpu = of_find_node_by_type(NULL, "cpu");
 153         virq= irq_of_parse_and_map(cpu, 0);
 154         irq = irq_map[virq].hwirq;
 155
 156         sys_tmr2 = immr_map(im_sit);
 157         out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
 158                                         (TBSCR_TBF | TBSCR_TBE));
 159         immr_unmap(sys_tmr2);
 160
 161         if (setup_irq(virq, &tbint_irqaction))
 162                 panic("Could not allocate timer IRQ!");
 163 }
 164
 165 /* The RTC on the MPC8xx is an internal register.
 166  * We want to protect this during power down, so we need to unlock,
 167  * modify, and re-lock.
 168  */
 169
 170 int mpc8xx_set_rtc_time(struct rtc_time *tm)
 171 {
 172         sitk8xx_t __iomem *sys_tmr1;
 173         sit8xx_t __iomem *sys_tmr2;
 174         int time;
 175
 176         sys_tmr1 = immr_map(im_sitk);
 177         sys_tmr2 = immr_map(im_sit);
 178         time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
 179                       tm->tm_hour, tm->tm_min, tm->tm_sec);
 180
 181         out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
 182         out_be32(&sys_tmr2->sit_rtc, time);
 183         out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);
 184
 185         immr_unmap(sys_tmr2);
 186         immr_unmap(sys_tmr1);
 187         return 0;
 188 }
 189
 190 void mpc8xx_get_rtc_time(struct rtc_time *tm)
 191 {
 192         unsigned long data;
 193         sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
 194
 195         /* Get time from the RTC. */
 196         data = in_be32(&sys_tmr->sit_rtc);
 197         to_tm(data, tm);
 198         tm->tm_year -= 1900;
 199         tm->tm_mon -= 1;
 200         immr_unmap(sys_tmr);
 201         return;
 202 }
 203
 204 void mpc8xx_restart(char *cmd)
 205 {
 206         car8xx_t __iomem *clk_r = immr_map(im_clkrst);
 207
 208
 209         local_irq_disable();
 210
 211         setbits32(&clk_r->car_plprcr, 0x00000080);
 212         /* Clear the ME bit in MSR to cause checkstop on machine check
 213         */
 214         mtmsr(mfmsr() & ~0x1000);
 215
 216         in_8(&clk_r->res[0]);
 217         panic("Restart failed\n");
 218 }
 219
 220 static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
 221 {
 222         int cascade_irq;
 223
 224         if ((cascade_irq = cpm_get_irq()) >= 0) {
 225                 struct irq_desc *cdesc = irq_desc + cascade_irq;
 226
 227                 generic_handle_irq(cascade_irq);
 228                 cdesc->chip->eoi(cascade_irq);
 229         }
 230         desc->chip->eoi(irq);
 231 }
 232
 233 /* Initialize the internal interrupt controllers.  The number of
 234  * interrupts supported can vary with the processor type, and the
 235  * 82xx family can have up to 64.
 236  * External interrupts can be either edge or level triggered, and
 237  * need to be initialized by the appropriate driver.
 238  */
 239 void __init mpc8xx_pics_init(void)
 240 {
 241         int irq;
 242
 243         if (mpc8xx_pic_init()) {
 244                 printk(KERN_ERR "Failed interrupt 8xx controller  initialization\n");
 245                 return;
 246         }
 247
 248         irq = cpm_pic_init();
 249         if (irq != NO_IRQ)
 250                 set_irq_chained_handler(irq, cpm_cascade);
 251 }