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[ARM] 3618/1: add defconfig for logicpd pxa270 card engine
[linux-2.6/mini2440.git] / drivers / scsi / sata_nv.c
blob9f553081b5e832525c8fde6fd33cea2c9058004e
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
32 */
33
34 #include <linux/config.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "sata_nv"
47 #define DRV_VERSION "0.8"
48
49 enum {
50 NV_PORTS = 2,
51 NV_PIO_MASK = 0x1f,
52 NV_MWDMA_MASK = 0x07,
53 NV_UDMA_MASK = 0x7f,
54 NV_PORT0_SCR_REG_OFFSET = 0x00,
55 NV_PORT1_SCR_REG_OFFSET = 0x40,
56
57 NV_INT_STATUS = 0x10,
58 NV_INT_STATUS_CK804 = 0x440,
59 NV_INT_STATUS_PDEV_INT = 0x01,
60 NV_INT_STATUS_PDEV_PM = 0x02,
61 NV_INT_STATUS_PDEV_ADDED = 0x04,
62 NV_INT_STATUS_PDEV_REMOVED = 0x08,
63 NV_INT_STATUS_SDEV_INT = 0x10,
64 NV_INT_STATUS_SDEV_PM = 0x20,
65 NV_INT_STATUS_SDEV_ADDED = 0x40,
66 NV_INT_STATUS_SDEV_REMOVED = 0x80,
67 NV_INT_STATUS_PDEV_HOTPLUG = (NV_INT_STATUS_PDEV_ADDED |
68 NV_INT_STATUS_PDEV_REMOVED),
69 NV_INT_STATUS_SDEV_HOTPLUG = (NV_INT_STATUS_SDEV_ADDED |
70 NV_INT_STATUS_SDEV_REMOVED),
71 NV_INT_STATUS_HOTPLUG = (NV_INT_STATUS_PDEV_HOTPLUG |
72 NV_INT_STATUS_SDEV_HOTPLUG),
73
74 NV_INT_ENABLE = 0x11,
75 NV_INT_ENABLE_CK804 = 0x441,
76 NV_INT_ENABLE_PDEV_MASK = 0x01,
77 NV_INT_ENABLE_PDEV_PM = 0x02,
78 NV_INT_ENABLE_PDEV_ADDED = 0x04,
79 NV_INT_ENABLE_PDEV_REMOVED = 0x08,
80 NV_INT_ENABLE_SDEV_MASK = 0x10,
81 NV_INT_ENABLE_SDEV_PM = 0x20,
82 NV_INT_ENABLE_SDEV_ADDED = 0x40,
83 NV_INT_ENABLE_SDEV_REMOVED = 0x80,
84 NV_INT_ENABLE_PDEV_HOTPLUG = (NV_INT_ENABLE_PDEV_ADDED |
85 NV_INT_ENABLE_PDEV_REMOVED),
86 NV_INT_ENABLE_SDEV_HOTPLUG = (NV_INT_ENABLE_SDEV_ADDED |
87 NV_INT_ENABLE_SDEV_REMOVED),
88 NV_INT_ENABLE_HOTPLUG = (NV_INT_ENABLE_PDEV_HOTPLUG |
89 NV_INT_ENABLE_SDEV_HOTPLUG),
90
91 NV_INT_CONFIG = 0x12,
92 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
93
94 // For PCI config register 20
95 NV_MCP_SATA_CFG_20 = 0x50,
96 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
97 };
98
99 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
100 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
101 struct pt_regs *regs);
102 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
103 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
104 static void nv_host_stop (struct ata_host_set *host_set);
105 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
106 static void nv_disable_hotplug(struct ata_host_set *host_set);
107 static int nv_check_hotplug(struct ata_host_set *host_set);
108 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
109 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
110 static int nv_check_hotplug_ck804(struct ata_host_set *host_set);
111
112 enum nv_host_type
113 {
114 GENERIC,
115 NFORCE2,
116 NFORCE3,
117 CK804
118 };
119
120 static const struct pci_device_id nv_pci_tbl[] = {
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
143 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
144 PCI_ANY_ID, PCI_ANY_ID,
145 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
146 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
147 PCI_ANY_ID, PCI_ANY_ID,
148 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
149 { 0, } /* terminate list */
150 };
151
152 struct nv_host_desc
153 {
154 enum nv_host_type host_type;
155 void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
156 void (*disable_hotplug)(struct ata_host_set *host_set);
157 int (*check_hotplug)(struct ata_host_set *host_set);
158
159 };
160 static struct nv_host_desc nv_device_tbl[] = {
161 {
162 .host_type = GENERIC,
163 .enable_hotplug = NULL,
164 .disable_hotplug= NULL,
165 .check_hotplug = NULL,
166 },
167 {
168 .host_type = NFORCE2,
169 .enable_hotplug = nv_enable_hotplug,
170 .disable_hotplug= nv_disable_hotplug,
171 .check_hotplug = nv_check_hotplug,
172 },
173 {
174 .host_type = NFORCE3,
175 .enable_hotplug = nv_enable_hotplug,
176 .disable_hotplug= nv_disable_hotplug,
177 .check_hotplug = nv_check_hotplug,
178 },
179 { .host_type = CK804,
180 .enable_hotplug = nv_enable_hotplug_ck804,
181 .disable_hotplug= nv_disable_hotplug_ck804,
182 .check_hotplug = nv_check_hotplug_ck804,
183 },
184 };
185
186 struct nv_host
187 {
188 struct nv_host_desc *host_desc;
189 unsigned long host_flags;
190 };
191
192 static struct pci_driver nv_pci_driver = {
193 .name = DRV_NAME,
194 .id_table = nv_pci_tbl,
195 .probe = nv_init_one,
196 .remove = ata_pci_remove_one,
197 };
198
199 static struct scsi_host_template nv_sht = {
200 .module = THIS_MODULE,
201 .name = DRV_NAME,
202 .ioctl = ata_scsi_ioctl,
203 .queuecommand = ata_scsi_queuecmd,
204 .can_queue = ATA_DEF_QUEUE,
205 .this_id = ATA_SHT_THIS_ID,
206 .sg_tablesize = LIBATA_MAX_PRD,
207 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
208 .emulated = ATA_SHT_EMULATED,
209 .use_clustering = ATA_SHT_USE_CLUSTERING,
210 .proc_name = DRV_NAME,
211 .dma_boundary = ATA_DMA_BOUNDARY,
212 .slave_configure = ata_scsi_slave_config,
213 .bios_param = ata_std_bios_param,
214 };
215
216 static const struct ata_port_operations nv_ops = {
217 .port_disable = ata_port_disable,
218 .tf_load = ata_tf_load,
219 .tf_read = ata_tf_read,
220 .exec_command = ata_exec_command,
221 .check_status = ata_check_status,
222 .dev_select = ata_std_dev_select,
223 .phy_reset = sata_phy_reset,
224 .bmdma_setup = ata_bmdma_setup,
225 .bmdma_start = ata_bmdma_start,
226 .bmdma_stop = ata_bmdma_stop,
227 .bmdma_status = ata_bmdma_status,
228 .qc_prep = ata_qc_prep,
229 .qc_issue = ata_qc_issue_prot,
230 .eng_timeout = ata_eng_timeout,
231 .irq_handler = nv_interrupt,
232 .irq_clear = ata_bmdma_irq_clear,
233 .scr_read = nv_scr_read,
234 .scr_write = nv_scr_write,
235 .port_start = ata_port_start,
236 .port_stop = ata_port_stop,
237 .host_stop = nv_host_stop,
238 };
239
240 /* FIXME: The hardware provides the necessary SATA PHY controls
241 * to support ATA_FLAG_SATA_RESET. However, it is currently
242 * necessary to disable that flag, to solve misdetection problems.
243 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
244 *
245 * This problem really needs to be investigated further. But in the
246 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
247 */
248 static struct ata_port_info nv_port_info = {
249 .sht = &nv_sht,
250 .host_flags = ATA_FLAG_SATA |
251 /* ATA_FLAG_SATA_RESET | */
252 ATA_FLAG_SRST |
253 ATA_FLAG_NO_LEGACY,
254 .pio_mask = NV_PIO_MASK,
255 .mwdma_mask = NV_MWDMA_MASK,
256 .udma_mask = NV_UDMA_MASK,
257 .port_ops = &nv_ops,
258 };
259
260 MODULE_AUTHOR("NVIDIA");
261 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
262 MODULE_LICENSE("GPL");
263 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
264 MODULE_VERSION(DRV_VERSION);
265
266 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
267 struct pt_regs *regs)
268 {
269 struct ata_host_set *host_set = dev_instance;
270 struct nv_host *host = host_set->private_data;
271 unsigned int i;
272 unsigned int handled = 0;
273 unsigned long flags;
274
275 spin_lock_irqsave(&host_set->lock, flags);
276
277 for (i = 0; i < host_set->n_ports; i++) {
278 struct ata_port *ap;
279
280 ap = host_set->ports[i];
281 if (ap &&
282 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
283 struct ata_queued_cmd *qc;
284
285 qc = ata_qc_from_tag(ap, ap->active_tag);
286 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
287 handled += ata_host_intr(ap, qc);
288 else
289 // No request pending? Clear interrupt status
290 // anyway, in case there's one pending.
291 ap->ops->check_status(ap);
292 }
293
294 }
295
296 if (host->host_desc->check_hotplug)
297 handled += host->host_desc->check_hotplug(host_set);
298
299 spin_unlock_irqrestore(&host_set->lock, flags);
300
301 return IRQ_RETVAL(handled);
302 }
303
304 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
305 {
306 if (sc_reg > SCR_CONTROL)
307 return 0xffffffffU;
308
309 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
310 }
311
312 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
313 {
314 if (sc_reg > SCR_CONTROL)
315 return;
316
317 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
318 }
319
320 static void nv_host_stop (struct ata_host_set *host_set)
321 {
322 struct nv_host *host = host_set->private_data;
323
324 // Disable hotplug event interrupts.
325 if (host->host_desc->disable_hotplug)
326 host->host_desc->disable_hotplug(host_set);
327
328 kfree(host);
329
330 ata_pci_host_stop(host_set);
331 }
332
333 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
334 {
335 static int printed_version = 0;
336 struct nv_host *host;
337 struct ata_port_info *ppi;
338 struct ata_probe_ent *probe_ent;
339 int pci_dev_busy = 0;
340 int rc;
341 u32 bar;
342 unsigned long base;
343
344 // Make sure this is a SATA controller by counting the number of bars
345 // (NVIDIA SATA controllers will always have six bars). Otherwise,
346 // it's an IDE controller and we ignore it.
347 for (bar=0; bar<6; bar++)
348 if (pci_resource_start(pdev, bar) == 0)
349 return -ENODEV;
350
351 if (!printed_version++)
352 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
353
354 rc = pci_enable_device(pdev);
355 if (rc)
356 goto err_out;
357
358 rc = pci_request_regions(pdev, DRV_NAME);
359 if (rc) {
360 pci_dev_busy = 1;
361 goto err_out_disable;
362 }
363
364 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
365 if (rc)
366 goto err_out_regions;
367 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
368 if (rc)
369 goto err_out_regions;
370
371 rc = -ENOMEM;
372
373 ppi = &nv_port_info;
374 probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
375 if (!probe_ent)
376 goto err_out_regions;
377
378 host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
379 if (!host)
380 goto err_out_free_ent;
381
382 memset(host, 0, sizeof(struct nv_host));
383 host->host_desc = &nv_device_tbl[ent->driver_data];
384
385 probe_ent->private_data = host;
386
387 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
388 if (!probe_ent->mmio_base) {
389 rc = -EIO;
390 goto err_out_free_host;
391 }
392
393 base = (unsigned long)probe_ent->mmio_base;
394
395 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
396 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
397
398 pci_set_master(pdev);
399
400 rc = ata_device_add(probe_ent);
401 if (rc != NV_PORTS)
402 goto err_out_iounmap;
403
404 // Enable hotplug event interrupts.
405 if (host->host_desc->enable_hotplug)
406 host->host_desc->enable_hotplug(probe_ent);
407
408 kfree(probe_ent);
409
410 return 0;
411
412 err_out_iounmap:
413 pci_iounmap(pdev, probe_ent->mmio_base);
414 err_out_free_host:
415 kfree(host);
416 err_out_free_ent:
417 kfree(probe_ent);
418 err_out_regions:
419 pci_release_regions(pdev);
420 err_out_disable:
421 if (!pci_dev_busy)
422 pci_disable_device(pdev);
423 err_out:
424 return rc;
425 }
426
427 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
428 {
429 u8 intr_mask;
430
431 outb(NV_INT_STATUS_HOTPLUG,
432 probe_ent->port[0].scr_addr + NV_INT_STATUS);
433
434 intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
435 intr_mask |= NV_INT_ENABLE_HOTPLUG;
436
437 outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
438 }
439
440 static void nv_disable_hotplug(struct ata_host_set *host_set)
441 {
442 u8 intr_mask;
443
444 intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
445
446 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
447
448 outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
449 }
450
451 static int nv_check_hotplug(struct ata_host_set *host_set)
452 {
453 u8 intr_status;
454
455 intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
456
457 // Clear interrupt status.
458 outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
459
460 if (intr_status & NV_INT_STATUS_HOTPLUG) {
461 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
462 printk(KERN_WARNING "nv_sata: "
463 "Primary device added\n");
464
465 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
466 printk(KERN_WARNING "nv_sata: "
467 "Primary device removed\n");
468
469 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
470 printk(KERN_WARNING "nv_sata: "
471 "Secondary device added\n");
472
473 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
474 printk(KERN_WARNING "nv_sata: "
475 "Secondary device removed\n");
476
477 return 1;
478 }
479
480 return 0;
481 }
482
483 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
484 {
485 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
486 u8 intr_mask;
487 u8 regval;
488
489 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
490 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
491 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
492
493 writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
494
495 intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
496 intr_mask |= NV_INT_ENABLE_HOTPLUG;
497
498 writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
499 }
500
501 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
502 {
503 struct pci_dev *pdev = to_pci_dev(host_set->dev);
504 u8 intr_mask;
505 u8 regval;
506
507 intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
508
509 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
510
511 writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
512
513 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
514 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
515 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
516 }
517
518 static int nv_check_hotplug_ck804(struct ata_host_set *host_set)
519 {
520 u8 intr_status;
521
522 intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
523
524 // Clear interrupt status.
525 writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
526
527 if (intr_status & NV_INT_STATUS_HOTPLUG) {
528 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
529 printk(KERN_WARNING "nv_sata: "
530 "Primary device added\n");
531
532 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
533 printk(KERN_WARNING "nv_sata: "
534 "Primary device removed\n");
535
536 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
537 printk(KERN_WARNING "nv_sata: "
538 "Secondary device added\n");
539
540 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
541 printk(KERN_WARNING "nv_sata: "
542 "Secondary device removed\n");
543
544 return 1;
545 }
546
547 return 0;
548 }
549
550 static int __init nv_init(void)
551 {
552 return pci_module_init(&nv_pci_driver);
553 }
554
555 static void __exit nv_exit(void)
556 {
557 pci_unregister_driver(&nv_pci_driver);
558 }
559
560 module_init(nv_init);
561 module_exit(nv_exit);
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