?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sb1250-mac.c: De-typedef, de-volatile, de-etc...
[linux-2.6/mini2440.git] / drivers / net / sb1250-mac.c
blob0cffd46724dfc8a5e93a6ee54ec4c75d10fe0427
1 /*
2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 *
19 * This driver is designed for the Broadcom SiByte SOC built-in
20 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
21 */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <asm/processor.h> /* Processor type for cache alignment. */
36 #include <asm/io.h>
37 #include <asm/cache.h>
38
39 /* This is only here until the firmware is ready. In that case,
40 the firmware leaves the ethernet address in the register for us. */
41 #ifdef CONFIG_SIBYTE_STANDALONE
42 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
43 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
44 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
45 #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
46 #endif
47
48
49 /* These identify the driver base version and may not be removed. */
50 #if 0
51 static char version1[] __devinitdata =
52 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
53 #endif
54
55
56 /* Operational parameters that usually are not changed. */
57
58 #define CONFIG_SBMAC_COALESCE
59
60 #define MAX_UNITS 4 /* More are supported, limit only on options */
61
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (2*HZ)
64
65
66 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
67 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
68
69 /* A few user-configurable values which may be modified when a driver
70 module is loaded. */
71
72 /* 1 normal messages, 0 quiet .. 7 verbose. */
73 static int debug = 1;
74 module_param(debug, int, S_IRUGO);
75 MODULE_PARM_DESC(debug, "Debug messages");
76
77 /* mii status msgs */
78 static int noisy_mii = 1;
79 module_param(noisy_mii, int, S_IRUGO);
80 MODULE_PARM_DESC(noisy_mii, "MII status messages");
81
82 /* Used to pass the media type, etc.
83 Both 'options[]' and 'full_duplex[]' should exist for driver
84 interoperability.
85 The media type is usually passed in 'options[]'.
86 */
87 #ifdef MODULE
88 static int options[MAX_UNITS] = {-1, -1, -1, -1};
89 module_param_array(options, int, NULL, S_IRUGO);
90 MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
91
92 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1};
93 module_param_array(full_duplex, int, NULL, S_IRUGO);
94 MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
95 #endif
96
97 #ifdef CONFIG_SBMAC_COALESCE
98 static int int_pktcnt_tx = 255;
99 module_param(int_pktcnt_tx, int, S_IRUGO);
100 MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
101
102 static int int_timeout_tx = 255;
103 module_param(int_timeout_tx, int, S_IRUGO);
104 MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
105
106 static int int_pktcnt_rx = 64;
107 module_param(int_pktcnt_rx, int, S_IRUGO);
108 MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
109
110 static int int_timeout_rx = 64;
111 module_param(int_timeout_rx, int, S_IRUGO);
112 MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
113 #endif
114
115 #include <asm/sibyte/sb1250.h>
116 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
117 #include <asm/sibyte/bcm1480_regs.h>
118 #include <asm/sibyte/bcm1480_int.h>
119 #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
120 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
121 #include <asm/sibyte/sb1250_regs.h>
122 #include <asm/sibyte/sb1250_int.h>
123 #else
124 #error invalid SiByte MAC configuation
125 #endif
126 #include <asm/sibyte/sb1250_scd.h>
127 #include <asm/sibyte/sb1250_mac.h>
128 #include <asm/sibyte/sb1250_dma.h>
129
130 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
131 #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
132 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
133 #define UNIT_INT(n) (K_INT_MAC_0 + (n))
134 #else
135 #error invalid SiByte MAC configuation
136 #endif
137
138 /**********************************************************************
139 * Simple types
140 ********************************************************************* */
141
142
143 enum sbmac_speed { sbmac_speed_auto, sbmac_speed_10,
144 sbmac_speed_100, sbmac_speed_1000 };
145
146 enum sbmac_duplex { sbmac_duplex_auto, sbmac_duplex_half,
147 sbmac_duplex_full };
148
149 enum sbmac_fc { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
150 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
151
152 enum sbmac_state { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
153 sbmac_state_broken };
154
155
156 /**********************************************************************
157 * Macros
158 ********************************************************************* */
159
160
161 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
162 (d)->sbdma_dscrtable : (d)->f+1)
163
164
165 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
166
167 #define SBMAC_MAX_TXDESCR 256
168 #define SBMAC_MAX_RXDESCR 256
169
170 #define ETHER_ALIGN 2
171 #define ETHER_ADDR_LEN 6
172 #define ENET_PACKET_SIZE 1518
173 /*#define ENET_PACKET_SIZE 9216 */
174
175 /**********************************************************************
176 * DMA Descriptor structure
177 ********************************************************************* */
178
179 struct sbdmadscr {
180 uint64_t dscr_a;
181 uint64_t dscr_b;
182 };
183
184 /**********************************************************************
185 * DMA Controller structure
186 ********************************************************************* */
187
188 struct sbmacdma {
189
190 /*
191 * This stuff is used to identify the channel and the registers
192 * associated with it.
193 */
194 struct sbmac_softc *sbdma_eth; /* back pointer to associated
195 MAC */
196 int sbdma_channel; /* channel number */
197 int sbdma_txdir; /* direction (1=transmit) */
198 int sbdma_maxdescr; /* total # of descriptors
199 in ring */
200 #ifdef CONFIG_SBMAC_COALESCE
201 int sbdma_int_pktcnt;
202 /* # descriptors rx/tx
203 before interrupt */
204 int sbdma_int_timeout;
205 /* # usec rx/tx interrupt */
206 #endif
207 void __iomem *sbdma_config0; /* DMA config register 0 */
208 void __iomem *sbdma_config1; /* DMA config register 1 */
209 void __iomem *sbdma_dscrbase;
210 /* descriptor base address */
211 void __iomem *sbdma_dscrcnt; /* descriptor count register */
212 void __iomem *sbdma_curdscr; /* current descriptor
213 address */
214 void __iomem *sbdma_oodpktlost;
215 /* pkt drop (rx only) */
216
217 /*
218 * This stuff is for maintenance of the ring
219 */
220 void *sbdma_dscrtable_unaligned;
221 struct sbdmadscr *sbdma_dscrtable;
222 /* base of descriptor table */
223 struct sbdmadscr *sbdma_dscrtable_end;
224 /* end of descriptor table */
225 struct sk_buff **sbdma_ctxtable;
226 /* context table, one
227 per descr */
228 dma_addr_t sbdma_dscrtable_phys;
229 /* and also the phys addr */
230 struct sbdmadscr *sbdma_addptr; /* next dscr for sw to add */
231 struct sbdmadscr *sbdma_remptr; /* next dscr for sw
232 to remove */
233 };
234
235
236 /**********************************************************************
237 * Ethernet softc structure
238 ********************************************************************* */
239
240 struct sbmac_softc {
241
242 /*
243 * Linux-specific things
244 */
245 struct net_device *sbm_dev; /* pointer to linux device */
246 struct napi_struct napi;
247 spinlock_t sbm_lock; /* spin lock */
248 struct timer_list sbm_timer; /* for monitoring MII */
249 int sbm_devflags; /* current device flags */
250
251 int sbm_phy_oldbmsr;
252 int sbm_phy_oldanlpar;
253 int sbm_phy_oldk1stsr;
254 int sbm_phy_oldlinkstat;
255 int sbm_buffersize;
256
257 unsigned char sbm_phys[2];
258
259 /*
260 * Controller-specific things
261 */
262 void __iomem *sbm_base; /* MAC's base address */
263 enum sbmac_state sbm_state; /* current state */
264
265 void __iomem *sbm_macenable; /* MAC Enable Register */
266 void __iomem *sbm_maccfg; /* MAC Config Register */
267 void __iomem *sbm_fifocfg; /* FIFO Config Register */
268 void __iomem *sbm_framecfg; /* Frame Config Register */
269 void __iomem *sbm_rxfilter; /* Receive Filter Register */
270 void __iomem *sbm_isr; /* Interrupt Status Register */
271 void __iomem *sbm_imr; /* Interrupt Mask Register */
272 void __iomem *sbm_mdio; /* MDIO Register */
273
274 enum sbmac_speed sbm_speed; /* current speed */
275 enum sbmac_duplex sbm_duplex; /* current duplex */
276 enum sbmac_fc sbm_fc; /* cur. flow control setting */
277
278 unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
279
280 struct sbmacdma sbm_txdma; /* only channel 0 for now */
281 struct sbmacdma sbm_rxdma;
282 int rx_hw_checksum;
283 int sbe_idx;
284 };
285
286
287 /**********************************************************************
288 * Externs
289 ********************************************************************* */
290
291 /**********************************************************************
292 * Prototypes
293 ********************************************************************* */
294
295 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
296 int txrx, int maxdescr);
297 static void sbdma_channel_start(struct sbmacdma *d, int rxtx);
298 static int sbdma_add_rcvbuffer(struct sbmacdma *d, struct sk_buff *m);
299 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m);
300 static void sbdma_emptyring(struct sbmacdma *d);
301 static void sbdma_fillring(struct sbmacdma *d);
302 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
303 int work_to_do, int poll);
304 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
305 int poll);
306 static int sbmac_initctx(struct sbmac_softc *s);
307 static void sbmac_channel_start(struct sbmac_softc *s);
308 static void sbmac_channel_stop(struct sbmac_softc *s);
309 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *,
310 enum sbmac_state);
311 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff);
312 static uint64_t sbmac_addr2reg(unsigned char *ptr);
313 static irqreturn_t sbmac_intr(int irq, void *dev_instance);
314 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
315 static void sbmac_setmulti(struct sbmac_softc *sc);
316 static int sbmac_init(struct net_device *dev, int idx);
317 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed);
318 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
319 enum sbmac_fc fc);
320
321 static int sbmac_open(struct net_device *dev);
322 static void sbmac_timer(unsigned long data);
323 static void sbmac_tx_timeout (struct net_device *dev);
324 static void sbmac_set_rx_mode(struct net_device *dev);
325 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
326 static int sbmac_close(struct net_device *dev);
327 static int sbmac_poll(struct napi_struct *napi, int budget);
328
329 static int sbmac_mii_poll(struct sbmac_softc *s, int noisy);
330 static int sbmac_mii_probe(struct net_device *dev);
331
332 static void sbmac_mii_sync(struct sbmac_softc *s);
333 static void sbmac_mii_senddata(struct sbmac_softc *s, unsigned int data,
334 int bitcnt);
335 static unsigned int sbmac_mii_read(struct sbmac_softc *s, int phyaddr,
336 int regidx);
337 static void sbmac_mii_write(struct sbmac_softc *s, int phyaddr, int regidx,
338 unsigned int regval);
339
340
341 /**********************************************************************
342 * Globals
343 ********************************************************************* */
344
345 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
346
347
348 /**********************************************************************
349 * MDIO constants
350 ********************************************************************* */
351
352 #define MII_COMMAND_START 0x01
353 #define MII_COMMAND_READ 0x02
354 #define MII_COMMAND_WRITE 0x01
355 #define MII_COMMAND_ACK 0x02
356
357 #define BMCR_RESET 0x8000
358 #define BMCR_LOOPBACK 0x4000
359 #define BMCR_SPEED0 0x2000
360 #define BMCR_ANENABLE 0x1000
361 #define BMCR_POWERDOWN 0x0800
362 #define BMCR_ISOLATE 0x0400
363 #define BMCR_RESTARTAN 0x0200
364 #define BMCR_DUPLEX 0x0100
365 #define BMCR_COLTEST 0x0080
366 #define BMCR_SPEED1 0x0040
367 #define BMCR_SPEED1000 BMCR_SPEED1
368 #define BMCR_SPEED100 BMCR_SPEED0
369 #define BMCR_SPEED10 0
370
371 #define BMSR_100BT4 0x8000
372 #define BMSR_100BT_FDX 0x4000
373 #define BMSR_100BT_HDX 0x2000
374 #define BMSR_10BT_FDX 0x1000
375 #define BMSR_10BT_HDX 0x0800
376 #define BMSR_100BT2_FDX 0x0400
377 #define BMSR_100BT2_HDX 0x0200
378 #define BMSR_1000BT_XSR 0x0100
379 #define BMSR_PRESUP 0x0040
380 #define BMSR_ANCOMPLT 0x0020
381 #define BMSR_REMFAULT 0x0010
382 #define BMSR_AUTONEG 0x0008
383 #define BMSR_LINKSTAT 0x0004
384 #define BMSR_JABDETECT 0x0002
385 #define BMSR_EXTCAPAB 0x0001
386
387 #define PHYIDR1 0x2000
388 #define PHYIDR2 0x5C60
389
390 #define ANAR_NP 0x8000
391 #define ANAR_RF 0x2000
392 #define ANAR_ASYPAUSE 0x0800
393 #define ANAR_PAUSE 0x0400
394 #define ANAR_T4 0x0200
395 #define ANAR_TXFD 0x0100
396 #define ANAR_TXHD 0x0080
397 #define ANAR_10FD 0x0040
398 #define ANAR_10HD 0x0020
399 #define ANAR_PSB 0x0001
400
401 #define ANLPAR_NP 0x8000
402 #define ANLPAR_ACK 0x4000
403 #define ANLPAR_RF 0x2000
404 #define ANLPAR_ASYPAUSE 0x0800
405 #define ANLPAR_PAUSE 0x0400
406 #define ANLPAR_T4 0x0200
407 #define ANLPAR_TXFD 0x0100
408 #define ANLPAR_TXHD 0x0080
409 #define ANLPAR_10FD 0x0040
410 #define ANLPAR_10HD 0x0020
411 #define ANLPAR_PSB 0x0001 /* 802.3 */
412
413 #define ANER_PDF 0x0010
414 #define ANER_LPNPABLE 0x0008
415 #define ANER_NPABLE 0x0004
416 #define ANER_PAGERX 0x0002
417 #define ANER_LPANABLE 0x0001
418
419 #define ANNPTR_NP 0x8000
420 #define ANNPTR_MP 0x2000
421 #define ANNPTR_ACK2 0x1000
422 #define ANNPTR_TOGTX 0x0800
423 #define ANNPTR_CODE 0x0008
424
425 #define ANNPRR_NP 0x8000
426 #define ANNPRR_MP 0x2000
427 #define ANNPRR_ACK3 0x1000
428 #define ANNPRR_TOGTX 0x0800
429 #define ANNPRR_CODE 0x0008
430
431 #define K1TCR_TESTMODE 0x0000
432 #define K1TCR_MSMCE 0x1000
433 #define K1TCR_MSCV 0x0800
434 #define K1TCR_RPTR 0x0400
435 #define K1TCR_1000BT_FDX 0x200
436 #define K1TCR_1000BT_HDX 0x100
437
438 #define K1STSR_MSMCFLT 0x8000
439 #define K1STSR_MSCFGRES 0x4000
440 #define K1STSR_LRSTAT 0x2000
441 #define K1STSR_RRSTAT 0x1000
442 #define K1STSR_LP1KFD 0x0800
443 #define K1STSR_LP1KHD 0x0400
444 #define K1STSR_LPASMDIR 0x0200
445
446 #define K1SCR_1KX_FDX 0x8000
447 #define K1SCR_1KX_HDX 0x4000
448 #define K1SCR_1KT_FDX 0x2000
449 #define K1SCR_1KT_HDX 0x1000
450
451 #define STRAP_PHY1 0x0800
452 #define STRAP_NCMODE 0x0400
453 #define STRAP_MANMSCFG 0x0200
454 #define STRAP_ANENABLE 0x0100
455 #define STRAP_MSVAL 0x0080
456 #define STRAP_1KHDXADV 0x0010
457 #define STRAP_1KFDXADV 0x0008
458 #define STRAP_100ADV 0x0004
459 #define STRAP_SPEEDSEL 0x0000
460 #define STRAP_SPEED100 0x0001
461
462 #define PHYSUP_SPEED1000 0x10
463 #define PHYSUP_SPEED100 0x08
464 #define PHYSUP_SPEED10 0x00
465 #define PHYSUP_LINKUP 0x04
466 #define PHYSUP_FDX 0x02
467
468 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
469 #define MII_BMSR 0x01 /* Basic mode status register (ro) */
470 #define MII_PHYIDR1 0x02
471 #define MII_PHYIDR2 0x03
472
473 #define MII_K1STSR 0x0A /* 1K Status Register (ro) */
474 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
475
476
477 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
478
479 #define ENABLE 1
480 #define DISABLE 0
481
482 /**********************************************************************
483 * SBMAC_MII_SYNC(s)
484 *
485 * Synchronize with the MII - send a pattern of bits to the MII
486 * that will guarantee that it is ready to accept a command.
487 *
488 * Input parameters:
489 * s - sbmac structure
490 *
491 * Return value:
492 * nothing
493 ********************************************************************* */
494
495 static void sbmac_mii_sync(struct sbmac_softc *s)
496 {
497 int cnt;
498 uint64_t bits;
499 int mac_mdio_genc;
500
501 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
502
503 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
504
505 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
506
507 for (cnt = 0; cnt < 32; cnt++) {
508 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
509 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
510 }
511 }
512
513 /**********************************************************************
514 * SBMAC_MII_SENDDATA(s,data,bitcnt)
515 *
516 * Send some bits to the MII. The bits to be sent are right-
517 * justified in the 'data' parameter.
518 *
519 * Input parameters:
520 * s - sbmac structure
521 * data - data to send
522 * bitcnt - number of bits to send
523 ********************************************************************* */
524
525 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
526 {
527 int i;
528 uint64_t bits;
529 unsigned int curmask;
530 int mac_mdio_genc;
531
532 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
533
534 bits = M_MAC_MDIO_DIR_OUTPUT;
535 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
536
537 curmask = 1 << (bitcnt - 1);
538
539 for (i = 0; i < bitcnt; i++) {
540 if (data & curmask)
541 bits |= M_MAC_MDIO_OUT;
542 else bits &= ~M_MAC_MDIO_OUT;
543 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
544 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
545 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
546 curmask >>= 1;
547 }
548 }
549
550
551
552 /**********************************************************************
553 * SBMAC_MII_READ(s,phyaddr,regidx)
554 *
555 * Read a PHY register.
556 *
557 * Input parameters:
558 * s - sbmac structure
559 * phyaddr - PHY's address
560 * regidx = index of register to read
561 *
562 * Return value:
563 * value read, or 0 if an error occurred.
564 ********************************************************************* */
565
566 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
567 {
568 int idx;
569 int error;
570 int regval;
571 int mac_mdio_genc;
572
573 /*
574 * Synchronize ourselves so that the PHY knows the next
575 * thing coming down is a command
576 */
577
578 sbmac_mii_sync(s);
579
580 /*
581 * Send the data to the PHY. The sequence is
582 * a "start" command (2 bits)
583 * a "read" command (2 bits)
584 * the PHY addr (5 bits)
585 * the register index (5 bits)
586 */
587
588 sbmac_mii_senddata(s,MII_COMMAND_START, 2);
589 sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
590 sbmac_mii_senddata(s,phyaddr, 5);
591 sbmac_mii_senddata(s,regidx, 5);
592
593 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
594
595 /*
596 * Switch the port around without a clock transition.
597 */
598 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
599
600 /*
601 * Send out a clock pulse to signal we want the status
602 */
603
604 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
605 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
606
607 /*
608 * If an error occurred, the PHY will signal '1' back
609 */
610 error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN;
611
612 /*
613 * Issue an 'idle' clock pulse, but keep the direction
614 * the same.
615 */
616 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
617 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
618
619 regval = 0;
620
621 for (idx = 0; idx < 16; idx++) {
622 regval <<= 1;
623
624 if (error == 0) {
625 if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN)
626 regval |= 1;
627 }
628
629 __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
630 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
631 }
632
633 /* Switch back to output */
634 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
635
636 if (error == 0)
637 return regval;
638 return 0;
639 }
640
641
642 /**********************************************************************
643 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
644 *
645 * Write a value to a PHY register.
646 *
647 * Input parameters:
648 * s - sbmac structure
649 * phyaddr - PHY to use
650 * regidx - register within the PHY
651 * regval - data to write to register
652 *
653 * Return value:
654 * nothing
655 ********************************************************************* */
656
657 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
658 unsigned int regval)
659 {
660 int mac_mdio_genc;
661
662 sbmac_mii_sync(s);
663
664 sbmac_mii_senddata(s,MII_COMMAND_START,2);
665 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
666 sbmac_mii_senddata(s,phyaddr, 5);
667 sbmac_mii_senddata(s,regidx, 5);
668 sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
669 sbmac_mii_senddata(s,regval,16);
670
671 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
672
673 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
674 }
675
676
677
678 /**********************************************************************
679 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
680 *
681 * Initialize a DMA channel context. Since there are potentially
682 * eight DMA channels per MAC, it's nice to do this in a standard
683 * way.
684 *
685 * Input parameters:
686 * d - struct sbmacdma (DMA channel context)
687 * s - struct sbmac_softc (pointer to a MAC)
688 * chan - channel number (0..1 right now)
689 * txrx - Identifies DMA_TX or DMA_RX for channel direction
690 * maxdescr - number of descriptors
691 *
692 * Return value:
693 * nothing
694 ********************************************************************* */
695
696 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
697 int txrx, int maxdescr)
698 {
699 #ifdef CONFIG_SBMAC_COALESCE
700 int int_pktcnt, int_timeout;
701 #endif
702
703 /*
704 * Save away interesting stuff in the structure
705 */
706
707 d->sbdma_eth = s;
708 d->sbdma_channel = chan;
709 d->sbdma_txdir = txrx;
710
711 #if 0
712 /* RMON clearing */
713 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
714 #endif
715
716 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
717 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
718 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
719 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
720 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
721 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
722 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
723 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
724 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
725 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
726 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
727 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
728 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
729 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
730 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
731 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
732 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
733 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
734 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
735 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
736 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
737
738 /*
739 * initialize register pointers
740 */
741
742 d->sbdma_config0 =
743 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
744 d->sbdma_config1 =
745 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
746 d->sbdma_dscrbase =
747 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
748 d->sbdma_dscrcnt =
749 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
750 d->sbdma_curdscr =
751 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
752 if (d->sbdma_txdir)
753 d->sbdma_oodpktlost = NULL;
754 else
755 d->sbdma_oodpktlost =
756 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
757
758 /*
759 * Allocate memory for the ring
760 */
761
762 d->sbdma_maxdescr = maxdescr;
763
764 d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1,
765 sizeof(*d->sbdma_dscrtable),
766 GFP_KERNEL);
767
768 /*
769 * The descriptor table must be aligned to at least 16 bytes or the
770 * MAC will corrupt it.
771 */
772 d->sbdma_dscrtable = (struct sbdmadscr *)
773 ALIGN((unsigned long)d->sbdma_dscrtable_unaligned,
774 sizeof(*d->sbdma_dscrtable));
775
776 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
777
778 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
779
780 /*
781 * And context table
782 */
783
784 d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,
785 sizeof(*d->sbdma_ctxtable), GFP_KERNEL);
786
787 #ifdef CONFIG_SBMAC_COALESCE
788 /*
789 * Setup Rx/Tx DMA coalescing defaults
790 */
791
792 int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
793 if ( int_pktcnt ) {
794 d->sbdma_int_pktcnt = int_pktcnt;
795 } else {
796 d->sbdma_int_pktcnt = 1;
797 }
798
799 int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
800 if ( int_timeout ) {
801 d->sbdma_int_timeout = int_timeout;
802 } else {
803 d->sbdma_int_timeout = 0;
804 }
805 #endif
806
807 }
808
809 /**********************************************************************
810 * SBDMA_CHANNEL_START(d)
811 *
812 * Initialize the hardware registers for a DMA channel.
813 *
814 * Input parameters:
815 * d - DMA channel to init (context must be previously init'd
816 * rxtx - DMA_RX or DMA_TX depending on what type of channel
817 *
818 * Return value:
819 * nothing
820 ********************************************************************* */
821
822 static void sbdma_channel_start(struct sbmacdma *d, int rxtx)
823 {
824 /*
825 * Turn on the DMA channel
826 */
827
828 #ifdef CONFIG_SBMAC_COALESCE
829 __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
830 0, d->sbdma_config1);
831 __raw_writeq(M_DMA_EOP_INT_EN |
832 V_DMA_RINGSZ(d->sbdma_maxdescr) |
833 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
834 0, d->sbdma_config0);
835 #else
836 __raw_writeq(0, d->sbdma_config1);
837 __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
838 0, d->sbdma_config0);
839 #endif
840
841 __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
842
843 /*
844 * Initialize ring pointers
845 */
846
847 d->sbdma_addptr = d->sbdma_dscrtable;
848 d->sbdma_remptr = d->sbdma_dscrtable;
849 }
850
851 /**********************************************************************
852 * SBDMA_CHANNEL_STOP(d)
853 *
854 * Initialize the hardware registers for a DMA channel.
855 *
856 * Input parameters:
857 * d - DMA channel to init (context must be previously init'd
858 *
859 * Return value:
860 * nothing
861 ********************************************************************* */
862
863 static void sbdma_channel_stop(struct sbmacdma *d)
864 {
865 /*
866 * Turn off the DMA channel
867 */
868
869 __raw_writeq(0, d->sbdma_config1);
870
871 __raw_writeq(0, d->sbdma_dscrbase);
872
873 __raw_writeq(0, d->sbdma_config0);
874
875 /*
876 * Zero ring pointers
877 */
878
879 d->sbdma_addptr = NULL;
880 d->sbdma_remptr = NULL;
881 }
882
883 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
884 {
885 unsigned long addr;
886 unsigned long newaddr;
887
888 addr = (unsigned long) skb->data;
889
890 newaddr = (addr + power2 - 1) & ~(power2 - 1);
891
892 skb_reserve(skb,newaddr-addr+offset);
893 }
894
895
896 /**********************************************************************
897 * SBDMA_ADD_RCVBUFFER(d,sb)
898 *
899 * Add a buffer to the specified DMA channel. For receive channels,
900 * this queues a buffer for inbound packets.
901 *
902 * Input parameters:
903 * d - DMA channel descriptor
904 * sb - sk_buff to add, or NULL if we should allocate one
905 *
906 * Return value:
907 * 0 if buffer could not be added (ring is full)
908 * 1 if buffer added successfully
909 ********************************************************************* */
910
911
912 static int sbdma_add_rcvbuffer(struct sbmacdma *d, struct sk_buff *sb)
913 {
914 struct sbdmadscr *dsc;
915 struct sbdmadscr *nextdsc;
916 struct sk_buff *sb_new = NULL;
917 int pktsize = ENET_PACKET_SIZE;
918
919 /* get pointer to our current place in the ring */
920
921 dsc = d->sbdma_addptr;
922 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
923
924 /*
925 * figure out if the ring is full - if the next descriptor
926 * is the same as the one that we're going to remove from
927 * the ring, the ring is full
928 */
929
930 if (nextdsc == d->sbdma_remptr) {
931 return -ENOSPC;
932 }
933
934 /*
935 * Allocate a sk_buff if we don't already have one.
936 * If we do have an sk_buff, reset it so that it's empty.
937 *
938 * Note: sk_buffs don't seem to be guaranteed to have any sort
939 * of alignment when they are allocated. Therefore, allocate enough
940 * extra space to make sure that:
941 *
942 * 1. the data does not start in the middle of a cache line.
943 * 2. The data does not end in the middle of a cache line
944 * 3. The buffer can be aligned such that the IP addresses are
945 * naturally aligned.
946 *
947 * Remember, the SOCs MAC writes whole cache lines at a time,
948 * without reading the old contents first. So, if the sk_buff's
949 * data portion starts in the middle of a cache line, the SOC
950 * DMA will trash the beginning (and ending) portions.
951 */
952
953 if (sb == NULL) {
954 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
955 if (sb_new == NULL) {
956 printk(KERN_INFO "%s: sk_buff allocation failed\n",
957 d->sbdma_eth->sbm_dev->name);
958 return -ENOBUFS;
959 }
960
961 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
962 }
963 else {
964 sb_new = sb;
965 /*
966 * nothing special to reinit buffer, it's already aligned
967 * and sb->data already points to a good place.
968 */
969 }
970
971 /*
972 * fill in the descriptor
973 */
974
975 #ifdef CONFIG_SBMAC_COALESCE
976 /*
977 * Do not interrupt per DMA transfer.
978 */
979 dsc->dscr_a = virt_to_phys(sb_new->data) |
980 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
981 #else
982 dsc->dscr_a = virt_to_phys(sb_new->data) |
983 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
984 M_DMA_DSCRA_INTERRUPT;
985 #endif
986
987 /* receiving: no options */
988 dsc->dscr_b = 0;
989
990 /*
991 * fill in the context
992 */
993
994 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
995
996 /*
997 * point at next packet
998 */
999
1000 d->sbdma_addptr = nextdsc;
1001
1002 /*
1003 * Give the buffer to the DMA engine.
1004 */
1005
1006 __raw_writeq(1, d->sbdma_dscrcnt);
1007
1008 return 0; /* we did it */
1009 }
1010
1011 /**********************************************************************
1012 * SBDMA_ADD_TXBUFFER(d,sb)
1013 *
1014 * Add a transmit buffer to the specified DMA channel, causing a
1015 * transmit to start.
1016 *
1017 * Input parameters:
1018 * d - DMA channel descriptor
1019 * sb - sk_buff to add
1020 *
1021 * Return value:
1022 * 0 transmit queued successfully
1023 * otherwise error code
1024 ********************************************************************* */
1025
1026
1027 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb)
1028 {
1029 struct sbdmadscr *dsc;
1030 struct sbdmadscr *nextdsc;
1031 uint64_t phys;
1032 uint64_t ncb;
1033 int length;
1034
1035 /* get pointer to our current place in the ring */
1036
1037 dsc = d->sbdma_addptr;
1038 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1039
1040 /*
1041 * figure out if the ring is full - if the next descriptor
1042 * is the same as the one that we're going to remove from
1043 * the ring, the ring is full
1044 */
1045
1046 if (nextdsc == d->sbdma_remptr) {
1047 return -ENOSPC;
1048 }
1049
1050 /*
1051 * Under Linux, it's not necessary to copy/coalesce buffers
1052 * like it is on NetBSD. We think they're all contiguous,
1053 * but that may not be true for GBE.
1054 */
1055
1056 length = sb->len;
1057
1058 /*
1059 * fill in the descriptor. Note that the number of cache
1060 * blocks in the descriptor is the number of blocks
1061 * *spanned*, so we need to add in the offset (if any)
1062 * while doing the calculation.
1063 */
1064
1065 phys = virt_to_phys(sb->data);
1066 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1067
1068 dsc->dscr_a = phys |
1069 V_DMA_DSCRA_A_SIZE(ncb) |
1070 #ifndef CONFIG_SBMAC_COALESCE
1071 M_DMA_DSCRA_INTERRUPT |
1072 #endif
1073 M_DMA_ETHTX_SOP;
1074
1075 /* transmitting: set outbound options and length */
1076
1077 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1078 V_DMA_DSCRB_PKT_SIZE(length);
1079
1080 /*
1081 * fill in the context
1082 */
1083
1084 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1085
1086 /*
1087 * point at next packet
1088 */
1089
1090 d->sbdma_addptr = nextdsc;
1091
1092 /*
1093 * Give the buffer to the DMA engine.
1094 */
1095
1096 __raw_writeq(1, d->sbdma_dscrcnt);
1097
1098 return 0; /* we did it */
1099 }
1100
1101
1102
1103
1104 /**********************************************************************
1105 * SBDMA_EMPTYRING(d)
1106 *
1107 * Free all allocated sk_buffs on the specified DMA channel;
1108 *
1109 * Input parameters:
1110 * d - DMA channel
1111 *
1112 * Return value:
1113 * nothing
1114 ********************************************************************* */
1115
1116 static void sbdma_emptyring(struct sbmacdma *d)
1117 {
1118 int idx;
1119 struct sk_buff *sb;
1120
1121 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1122 sb = d->sbdma_ctxtable[idx];
1123 if (sb) {
1124 dev_kfree_skb(sb);
1125 d->sbdma_ctxtable[idx] = NULL;
1126 }
1127 }
1128 }
1129
1130
1131 /**********************************************************************
1132 * SBDMA_FILLRING(d)
1133 *
1134 * Fill the specified DMA channel (must be receive channel)
1135 * with sk_buffs
1136 *
1137 * Input parameters:
1138 * d - DMA channel
1139 *
1140 * Return value:
1141 * nothing
1142 ********************************************************************* */
1143
1144 static void sbdma_fillring(struct sbmacdma *d)
1145 {
1146 int idx;
1147
1148 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1149 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1150 break;
1151 }
1152 }
1153
1154 #ifdef CONFIG_NET_POLL_CONTROLLER
1155 static void sbmac_netpoll(struct net_device *netdev)
1156 {
1157 struct sbmac_softc *sc = netdev_priv(netdev);
1158 int irq = sc->sbm_dev->irq;
1159
1160 __raw_writeq(0, sc->sbm_imr);
1161
1162 sbmac_intr(irq, netdev);
1163
1164 #ifdef CONFIG_SBMAC_COALESCE
1165 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1166 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1167 sc->sbm_imr);
1168 #else
1169 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1170 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1171 #endif
1172 }
1173 #endif
1174
1175 /**********************************************************************
1176 * SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1177 *
1178 * Process "completed" receive buffers on the specified DMA channel.
1179 *
1180 * Input parameters:
1181 * sc - softc structure
1182 * d - DMA channel context
1183 * work_to_do - no. of packets to process before enabling interrupt
1184 * again (for NAPI)
1185 * poll - 1: using polling (for NAPI)
1186 *
1187 * Return value:
1188 * nothing
1189 ********************************************************************* */
1190
1191 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1192 int work_to_do, int poll)
1193 {
1194 struct net_device *dev = sc->sbm_dev;
1195 int curidx;
1196 int hwidx;
1197 struct sbdmadscr *dsc;
1198 struct sk_buff *sb;
1199 int len;
1200 int work_done = 0;
1201 int dropped = 0;
1202
1203 prefetch(d);
1204
1205 again:
1206 /* Check if the HW dropped any frames */
1207 dev->stats.rx_fifo_errors
1208 += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1209 __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1210
1211 while (work_to_do-- > 0) {
1212 /*
1213 * figure out where we are (as an index) and where
1214 * the hardware is (also as an index)
1215 *
1216 * This could be done faster if (for example) the
1217 * descriptor table was page-aligned and contiguous in
1218 * both virtual and physical memory -- you could then
1219 * just compare the low-order bits of the virtual address
1220 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1221 */
1222
1223 dsc = d->sbdma_remptr;
1224 curidx = dsc - d->sbdma_dscrtable;
1225
1226 prefetch(dsc);
1227 prefetch(&d->sbdma_ctxtable[curidx]);
1228
1229 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1230 d->sbdma_dscrtable_phys) /
1231 sizeof(*d->sbdma_dscrtable);
1232
1233 /*
1234 * If they're the same, that means we've processed all
1235 * of the descriptors up to (but not including) the one that
1236 * the hardware is working on right now.
1237 */
1238
1239 if (curidx == hwidx)
1240 goto done;
1241
1242 /*
1243 * Otherwise, get the packet's sk_buff ptr back
1244 */
1245
1246 sb = d->sbdma_ctxtable[curidx];
1247 d->sbdma_ctxtable[curidx] = NULL;
1248
1249 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1250
1251 /*
1252 * Check packet status. If good, process it.
1253 * If not, silently drop it and put it back on the
1254 * receive ring.
1255 */
1256
1257 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1258
1259 /*
1260 * Add a new buffer to replace the old one. If we fail
1261 * to allocate a buffer, we're going to drop this
1262 * packet and put it right back on the receive ring.
1263 */
1264
1265 if (unlikely (sbdma_add_rcvbuffer(d,NULL) ==
1266 -ENOBUFS)) {
1267 dev->stats.rx_dropped++;
1268 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1269 /* No point in continuing at the moment */
1270 printk(KERN_ERR "dropped packet (1)\n");
1271 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1272 goto done;
1273 } else {
1274 /*
1275 * Set length into the packet
1276 */
1277 skb_put(sb,len);
1278
1279 /*
1280 * Buffer has been replaced on the
1281 * receive ring. Pass the buffer to
1282 * the kernel
1283 */
1284 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1285 /* Check hw IPv4/TCP checksum if supported */
1286 if (sc->rx_hw_checksum == ENABLE) {
1287 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1288 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1289 sb->ip_summed = CHECKSUM_UNNECESSARY;
1290 /* don't need to set sb->csum */
1291 } else {
1292 sb->ip_summed = CHECKSUM_NONE;
1293 }
1294 }
1295 prefetch(sb->data);
1296 prefetch((const void *)(((char *)sb->data)+32));
1297 if (poll)
1298 dropped = netif_receive_skb(sb);
1299 else
1300 dropped = netif_rx(sb);
1301
1302 if (dropped == NET_RX_DROP) {
1303 dev->stats.rx_dropped++;
1304 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1305 goto done;
1306 }
1307 else {
1308 dev->stats.rx_bytes += len;
1309 dev->stats.rx_packets++;
1310 }
1311 }
1312 } else {
1313 /*
1314 * Packet was mangled somehow. Just drop it and
1315 * put it back on the receive ring.
1316 */
1317 dev->stats.rx_errors++;
1318 sbdma_add_rcvbuffer(d,sb);
1319 }
1320
1321
1322 /*
1323 * .. and advance to the next buffer.
1324 */
1325
1326 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1327 work_done++;
1328 }
1329 if (!poll) {
1330 work_to_do = 32;
1331 goto again; /* collect fifo drop statistics again */
1332 }
1333 done:
1334 return work_done;
1335 }
1336
1337 /**********************************************************************
1338 * SBDMA_TX_PROCESS(sc,d)
1339 *
1340 * Process "completed" transmit buffers on the specified DMA channel.
1341 * This is normally called within the interrupt service routine.
1342 * Note that this isn't really ideal for priority channels, since
1343 * it processes all of the packets on a given channel before
1344 * returning.
1345 *
1346 * Input parameters:
1347 * sc - softc structure
1348 * d - DMA channel context
1349 * poll - 1: using polling (for NAPI)
1350 *
1351 * Return value:
1352 * nothing
1353 ********************************************************************* */
1354
1355 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1356 int poll)
1357 {
1358 struct net_device *dev = sc->sbm_dev;
1359 int curidx;
1360 int hwidx;
1361 struct sbdmadscr *dsc;
1362 struct sk_buff *sb;
1363 unsigned long flags;
1364 int packets_handled = 0;
1365
1366 spin_lock_irqsave(&(sc->sbm_lock), flags);
1367
1368 if (d->sbdma_remptr == d->sbdma_addptr)
1369 goto end_unlock;
1370
1371 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1372 d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable);
1373
1374 for (;;) {
1375 /*
1376 * figure out where we are (as an index) and where
1377 * the hardware is (also as an index)
1378 *
1379 * This could be done faster if (for example) the
1380 * descriptor table was page-aligned and contiguous in
1381 * both virtual and physical memory -- you could then
1382 * just compare the low-order bits of the virtual address
1383 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1384 */
1385
1386 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1387
1388 /*
1389 * If they're the same, that means we've processed all
1390 * of the descriptors up to (but not including) the one that
1391 * the hardware is working on right now.
1392 */
1393
1394 if (curidx == hwidx)
1395 break;
1396
1397 /*
1398 * Otherwise, get the packet's sk_buff ptr back
1399 */
1400
1401 dsc = &(d->sbdma_dscrtable[curidx]);
1402 sb = d->sbdma_ctxtable[curidx];
1403 d->sbdma_ctxtable[curidx] = NULL;
1404
1405 /*
1406 * Stats
1407 */
1408
1409 dev->stats.tx_bytes += sb->len;
1410 dev->stats.tx_packets++;
1411
1412 /*
1413 * for transmits, we just free buffers.
1414 */
1415
1416 dev_kfree_skb_irq(sb);
1417
1418 /*
1419 * .. and advance to the next buffer.
1420 */
1421
1422 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1423
1424 packets_handled++;
1425
1426 }
1427
1428 /*
1429 * Decide if we should wake up the protocol or not.
1430 * Other drivers seem to do this when we reach a low
1431 * watermark on the transmit queue.
1432 */
1433
1434 if (packets_handled)
1435 netif_wake_queue(d->sbdma_eth->sbm_dev);
1436
1437 end_unlock:
1438 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1439
1440 }
1441
1442
1443
1444 /**********************************************************************
1445 * SBMAC_INITCTX(s)
1446 *
1447 * Initialize an Ethernet context structure - this is called
1448 * once per MAC on the 1250. Memory is allocated here, so don't
1449 * call it again from inside the ioctl routines that bring the
1450 * interface up/down
1451 *
1452 * Input parameters:
1453 * s - sbmac context structure
1454 *
1455 * Return value:
1456 * 0
1457 ********************************************************************* */
1458
1459 static int sbmac_initctx(struct sbmac_softc *s)
1460 {
1461
1462 /*
1463 * figure out the addresses of some ports
1464 */
1465
1466 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1467 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1468 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1469 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1470 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1471 s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1472 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1473 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1474
1475 s->sbm_phys[0] = 1;
1476 s->sbm_phys[1] = 0;
1477
1478 s->sbm_phy_oldbmsr = 0;
1479 s->sbm_phy_oldanlpar = 0;
1480 s->sbm_phy_oldk1stsr = 0;
1481 s->sbm_phy_oldlinkstat = 0;
1482
1483 /*
1484 * Initialize the DMA channels. Right now, only one per MAC is used
1485 * Note: Only do this _once_, as it allocates memory from the kernel!
1486 */
1487
1488 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1489 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1490
1491 /*
1492 * initial state is OFF
1493 */
1494
1495 s->sbm_state = sbmac_state_off;
1496
1497 /*
1498 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1499 */
1500
1501 s->sbm_speed = sbmac_speed_10;
1502 s->sbm_duplex = sbmac_duplex_half;
1503 s->sbm_fc = sbmac_fc_disabled;
1504
1505 return 0;
1506 }
1507
1508
1509 static void sbdma_uninitctx(struct sbmacdma *d)
1510 {
1511 if (d->sbdma_dscrtable_unaligned) {
1512 kfree(d->sbdma_dscrtable_unaligned);
1513 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1514 }
1515
1516 if (d->sbdma_ctxtable) {
1517 kfree(d->sbdma_ctxtable);
1518 d->sbdma_ctxtable = NULL;
1519 }
1520 }
1521
1522
1523 static void sbmac_uninitctx(struct sbmac_softc *sc)
1524 {
1525 sbdma_uninitctx(&(sc->sbm_txdma));
1526 sbdma_uninitctx(&(sc->sbm_rxdma));
1527 }
1528
1529
1530 /**********************************************************************
1531 * SBMAC_CHANNEL_START(s)
1532 *
1533 * Start packet processing on this MAC.
1534 *
1535 * Input parameters:
1536 * s - sbmac structure
1537 *
1538 * Return value:
1539 * nothing
1540 ********************************************************************* */
1541
1542 static void sbmac_channel_start(struct sbmac_softc *s)
1543 {
1544 uint64_t reg;
1545 void __iomem *port;
1546 uint64_t cfg,fifo,framecfg;
1547 int idx, th_value;
1548
1549 /*
1550 * Don't do this if running
1551 */
1552
1553 if (s->sbm_state == sbmac_state_on)
1554 return;
1555
1556 /*
1557 * Bring the controller out of reset, but leave it off.
1558 */
1559
1560 __raw_writeq(0, s->sbm_macenable);
1561
1562 /*
1563 * Ignore all received packets
1564 */
1565
1566 __raw_writeq(0, s->sbm_rxfilter);
1567
1568 /*
1569 * Calculate values for various control registers.
1570 */
1571
1572 cfg = M_MAC_RETRY_EN |
1573 M_MAC_TX_HOLD_SOP_EN |
1574 V_MAC_TX_PAUSE_CNT_16K |
1575 M_MAC_AP_STAT_EN |
1576 M_MAC_FAST_SYNC |
1577 M_MAC_SS_EN |
1578 0;
1579
1580 /*
1581 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1582 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1583 * Use a larger RD_THRSH for gigabit
1584 */
1585 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1586 th_value = 28;
1587 else
1588 th_value = 64;
1589
1590 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1591 ((s->sbm_speed == sbmac_speed_1000)
1592 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1593 V_MAC_TX_RL_THRSH(4) |
1594 V_MAC_RX_PL_THRSH(4) |
1595 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1596 V_MAC_RX_PL_THRSH(4) |
1597 V_MAC_RX_RL_THRSH(8) |
1598 0;
1599
1600 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1601 V_MAC_MAX_FRAMESZ_DEFAULT |
1602 V_MAC_BACKOFF_SEL(1);
1603
1604 /*
1605 * Clear out the hash address map
1606 */
1607
1608 port = s->sbm_base + R_MAC_HASH_BASE;
1609 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1610 __raw_writeq(0, port);
1611 port += sizeof(uint64_t);
1612 }
1613
1614 /*
1615 * Clear out the exact-match table
1616 */
1617
1618 port = s->sbm_base + R_MAC_ADDR_BASE;
1619 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1620 __raw_writeq(0, port);
1621 port += sizeof(uint64_t);
1622 }
1623
1624 /*
1625 * Clear out the DMA Channel mapping table registers
1626 */
1627
1628 port = s->sbm_base + R_MAC_CHUP0_BASE;
1629 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1630 __raw_writeq(0, port);
1631 port += sizeof(uint64_t);
1632 }
1633
1634
1635 port = s->sbm_base + R_MAC_CHLO0_BASE;
1636 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1637 __raw_writeq(0, port);
1638 port += sizeof(uint64_t);
1639 }
1640
1641 /*
1642 * Program the hardware address. It goes into the hardware-address
1643 * register as well as the first filter register.
1644 */
1645
1646 reg = sbmac_addr2reg(s->sbm_hwaddr);
1647
1648 port = s->sbm_base + R_MAC_ADDR_BASE;
1649 __raw_writeq(reg, port);
1650 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1651
1652 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1653 /*
1654 * Pass1 SOCs do not receive packets addressed to the
1655 * destination address in the R_MAC_ETHERNET_ADDR register.
1656 * Set the value to zero.
1657 */
1658 __raw_writeq(0, port);
1659 #else
1660 __raw_writeq(reg, port);
1661 #endif
1662
1663 /*
1664 * Set the receive filter for no packets, and write values
1665 * to the various config registers
1666 */
1667
1668 __raw_writeq(0, s->sbm_rxfilter);
1669 __raw_writeq(0, s->sbm_imr);
1670 __raw_writeq(framecfg, s->sbm_framecfg);
1671 __raw_writeq(fifo, s->sbm_fifocfg);
1672 __raw_writeq(cfg, s->sbm_maccfg);
1673
1674 /*
1675 * Initialize DMA channels (rings should be ok now)
1676 */
1677
1678 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1679 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1680
1681 /*
1682 * Configure the speed, duplex, and flow control
1683 */
1684
1685 sbmac_set_speed(s,s->sbm_speed);
1686 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1687
1688 /*
1689 * Fill the receive ring
1690 */
1691
1692 sbdma_fillring(&(s->sbm_rxdma));
1693
1694 /*
1695 * Turn on the rest of the bits in the enable register
1696 */
1697
1698 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1699 __raw_writeq(M_MAC_RXDMA_EN0 |
1700 M_MAC_TXDMA_EN0, s->sbm_macenable);
1701 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1702 __raw_writeq(M_MAC_RXDMA_EN0 |
1703 M_MAC_TXDMA_EN0 |
1704 M_MAC_RX_ENABLE |
1705 M_MAC_TX_ENABLE, s->sbm_macenable);
1706 #else
1707 #error invalid SiByte MAC configuation
1708 #endif
1709
1710 #ifdef CONFIG_SBMAC_COALESCE
1711 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1712 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1713 #else
1714 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1715 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1716 #endif
1717
1718 /*
1719 * Enable receiving unicasts and broadcasts
1720 */
1721
1722 __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1723
1724 /*
1725 * we're running now.
1726 */
1727
1728 s->sbm_state = sbmac_state_on;
1729
1730 /*
1731 * Program multicast addresses
1732 */
1733
1734 sbmac_setmulti(s);
1735
1736 /*
1737 * If channel was in promiscuous mode before, turn that on
1738 */
1739
1740 if (s->sbm_devflags & IFF_PROMISC) {
1741 sbmac_promiscuous_mode(s,1);
1742 }
1743
1744 }
1745
1746
1747 /**********************************************************************
1748 * SBMAC_CHANNEL_STOP(s)
1749 *
1750 * Stop packet processing on this MAC.
1751 *
1752 * Input parameters:
1753 * s - sbmac structure
1754 *
1755 * Return value:
1756 * nothing
1757 ********************************************************************* */
1758
1759 static void sbmac_channel_stop(struct sbmac_softc *s)
1760 {
1761 /* don't do this if already stopped */
1762
1763 if (s->sbm_state == sbmac_state_off)
1764 return;
1765
1766 /* don't accept any packets, disable all interrupts */
1767
1768 __raw_writeq(0, s->sbm_rxfilter);
1769 __raw_writeq(0, s->sbm_imr);
1770
1771 /* Turn off ticker */
1772
1773 /* XXX */
1774
1775 /* turn off receiver and transmitter */
1776
1777 __raw_writeq(0, s->sbm_macenable);
1778
1779 /* We're stopped now. */
1780
1781 s->sbm_state = sbmac_state_off;
1782
1783 /*
1784 * Stop DMA channels (rings should be ok now)
1785 */
1786
1787 sbdma_channel_stop(&(s->sbm_rxdma));
1788 sbdma_channel_stop(&(s->sbm_txdma));
1789
1790 /* Empty the receive and transmit rings */
1791
1792 sbdma_emptyring(&(s->sbm_rxdma));
1793 sbdma_emptyring(&(s->sbm_txdma));
1794
1795 }
1796
1797 /**********************************************************************
1798 * SBMAC_SET_CHANNEL_STATE(state)
1799 *
1800 * Set the channel's state ON or OFF
1801 *
1802 * Input parameters:
1803 * state - new state
1804 *
1805 * Return value:
1806 * old state
1807 ********************************************************************* */
1808 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc,
1809 enum sbmac_state state)
1810 {
1811 enum sbmac_state oldstate = sc->sbm_state;
1812
1813 /*
1814 * If same as previous state, return
1815 */
1816
1817 if (state == oldstate) {
1818 return oldstate;
1819 }
1820
1821 /*
1822 * If new state is ON, turn channel on
1823 */
1824
1825 if (state == sbmac_state_on) {
1826 sbmac_channel_start(sc);
1827 }
1828 else {
1829 sbmac_channel_stop(sc);
1830 }
1831
1832 /*
1833 * Return previous state
1834 */
1835
1836 return oldstate;
1837 }
1838
1839
1840 /**********************************************************************
1841 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1842 *
1843 * Turn on or off promiscuous mode
1844 *
1845 * Input parameters:
1846 * sc - softc
1847 * onoff - 1 to turn on, 0 to turn off
1848 *
1849 * Return value:
1850 * nothing
1851 ********************************************************************* */
1852
1853 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1854 {
1855 uint64_t reg;
1856
1857 if (sc->sbm_state != sbmac_state_on)
1858 return;
1859
1860 if (onoff) {
1861 reg = __raw_readq(sc->sbm_rxfilter);
1862 reg |= M_MAC_ALLPKT_EN;
1863 __raw_writeq(reg, sc->sbm_rxfilter);
1864 }
1865 else {
1866 reg = __raw_readq(sc->sbm_rxfilter);
1867 reg &= ~M_MAC_ALLPKT_EN;
1868 __raw_writeq(reg, sc->sbm_rxfilter);
1869 }
1870 }
1871
1872 /**********************************************************************
1873 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1874 *
1875 * Set the iphdr offset as 15 assuming ethernet encapsulation
1876 *
1877 * Input parameters:
1878 * sc - softc
1879 *
1880 * Return value:
1881 * nothing
1882 ********************************************************************* */
1883
1884 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1885 {
1886 uint64_t reg;
1887
1888 /* Hard code the off set to 15 for now */
1889 reg = __raw_readq(sc->sbm_rxfilter);
1890 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1891 __raw_writeq(reg, sc->sbm_rxfilter);
1892
1893 /* BCM1250 pass1 didn't have hardware checksum. Everything
1894 later does. */
1895 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1896 sc->rx_hw_checksum = DISABLE;
1897 } else {
1898 sc->rx_hw_checksum = ENABLE;
1899 }
1900 }
1901
1902
1903 /**********************************************************************
1904 * SBMAC_ADDR2REG(ptr)
1905 *
1906 * Convert six bytes into the 64-bit register value that
1907 * we typically write into the SBMAC's address/mcast registers
1908 *
1909 * Input parameters:
1910 * ptr - pointer to 6 bytes
1911 *
1912 * Return value:
1913 * register value
1914 ********************************************************************* */
1915
1916 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1917 {
1918 uint64_t reg = 0;
1919
1920 ptr += 6;
1921
1922 reg |= (uint64_t) *(--ptr);
1923 reg <<= 8;
1924 reg |= (uint64_t) *(--ptr);
1925 reg <<= 8;
1926 reg |= (uint64_t) *(--ptr);
1927 reg <<= 8;
1928 reg |= (uint64_t) *(--ptr);
1929 reg <<= 8;
1930 reg |= (uint64_t) *(--ptr);
1931 reg <<= 8;
1932 reg |= (uint64_t) *(--ptr);
1933
1934 return reg;
1935 }
1936
1937
1938 /**********************************************************************
1939 * SBMAC_SET_SPEED(s,speed)
1940 *
1941 * Configure LAN speed for the specified MAC.
1942 * Warning: must be called when MAC is off!
1943 *
1944 * Input parameters:
1945 * s - sbmac structure
1946 * speed - speed to set MAC to (see enum sbmac_speed)
1947 *
1948 * Return value:
1949 * 1 if successful
1950 * 0 indicates invalid parameters
1951 ********************************************************************* */
1952
1953 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed)
1954 {
1955 uint64_t cfg;
1956 uint64_t framecfg;
1957
1958 /*
1959 * Save new current values
1960 */
1961
1962 s->sbm_speed = speed;
1963
1964 if (s->sbm_state == sbmac_state_on)
1965 return 0; /* save for next restart */
1966
1967 /*
1968 * Read current register values
1969 */
1970
1971 cfg = __raw_readq(s->sbm_maccfg);
1972 framecfg = __raw_readq(s->sbm_framecfg);
1973
1974 /*
1975 * Mask out the stuff we want to change
1976 */
1977
1978 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1979 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1980 M_MAC_SLOT_SIZE);
1981
1982 /*
1983 * Now add in the new bits
1984 */
1985
1986 switch (speed) {
1987 case sbmac_speed_10:
1988 framecfg |= V_MAC_IFG_RX_10 |
1989 V_MAC_IFG_TX_10 |
1990 K_MAC_IFG_THRSH_10 |
1991 V_MAC_SLOT_SIZE_10;
1992 cfg |= V_MAC_SPEED_SEL_10MBPS;
1993 break;
1994
1995 case sbmac_speed_100:
1996 framecfg |= V_MAC_IFG_RX_100 |
1997 V_MAC_IFG_TX_100 |
1998 V_MAC_IFG_THRSH_100 |
1999 V_MAC_SLOT_SIZE_100;
2000 cfg |= V_MAC_SPEED_SEL_100MBPS ;
2001 break;
2002
2003 case sbmac_speed_1000:
2004 framecfg |= V_MAC_IFG_RX_1000 |
2005 V_MAC_IFG_TX_1000 |
2006 V_MAC_IFG_THRSH_1000 |
2007 V_MAC_SLOT_SIZE_1000;
2008 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
2009 break;
2010
2011 case sbmac_speed_auto: /* XXX not implemented */
2012 /* fall through */
2013 default:
2014 return 0;
2015 }
2016
2017 /*
2018 * Send the bits back to the hardware
2019 */
2020
2021 __raw_writeq(framecfg, s->sbm_framecfg);
2022 __raw_writeq(cfg, s->sbm_maccfg);
2023
2024 return 1;
2025 }
2026
2027 /**********************************************************************
2028 * SBMAC_SET_DUPLEX(s,duplex,fc)
2029 *
2030 * Set Ethernet duplex and flow control options for this MAC
2031 * Warning: must be called when MAC is off!
2032 *
2033 * Input parameters:
2034 * s - sbmac structure
2035 * duplex - duplex setting (see enum sbmac_duplex)
2036 * fc - flow control setting (see enum sbmac_fc)
2037 *
2038 * Return value:
2039 * 1 if ok
2040 * 0 if an invalid parameter combination was specified
2041 ********************************************************************* */
2042
2043 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
2044 enum sbmac_fc fc)
2045 {
2046 uint64_t cfg;
2047
2048 /*
2049 * Save new current values
2050 */
2051
2052 s->sbm_duplex = duplex;
2053 s->sbm_fc = fc;
2054
2055 if (s->sbm_state == sbmac_state_on)
2056 return 0; /* save for next restart */
2057
2058 /*
2059 * Read current register values
2060 */
2061
2062 cfg = __raw_readq(s->sbm_maccfg);
2063
2064 /*
2065 * Mask off the stuff we're about to change
2066 */
2067
2068 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
2069
2070
2071 switch (duplex) {
2072 case sbmac_duplex_half:
2073 switch (fc) {
2074 case sbmac_fc_disabled:
2075 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
2076 break;
2077
2078 case sbmac_fc_collision:
2079 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2080 break;
2081
2082 case sbmac_fc_carrier:
2083 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2084 break;
2085
2086 case sbmac_fc_auto: /* XXX not implemented */
2087 /* fall through */
2088 case sbmac_fc_frame: /* not valid in half duplex */
2089 default: /* invalid selection */
2090 return 0;
2091 }
2092 break;
2093
2094 case sbmac_duplex_full:
2095 switch (fc) {
2096 case sbmac_fc_disabled:
2097 cfg |= V_MAC_FC_CMD_DISABLED;
2098 break;
2099
2100 case sbmac_fc_frame:
2101 cfg |= V_MAC_FC_CMD_ENABLED;
2102 break;
2103
2104 case sbmac_fc_collision: /* not valid in full duplex */
2105 case sbmac_fc_carrier: /* not valid in full duplex */
2106 case sbmac_fc_auto: /* XXX not implemented */
2107 /* fall through */
2108 default:
2109 return 0;
2110 }
2111 break;
2112 case sbmac_duplex_auto:
2113 /* XXX not implemented */
2114 break;
2115 }
2116
2117 /*
2118 * Send the bits back to the hardware
2119 */
2120
2121 __raw_writeq(cfg, s->sbm_maccfg);
2122
2123 return 1;
2124 }
2125
2126
2127
2128
2129 /**********************************************************************
2130 * SBMAC_INTR()
2131 *
2132 * Interrupt handler for MAC interrupts
2133 *
2134 * Input parameters:
2135 * MAC structure
2136 *
2137 * Return value:
2138 * nothing
2139 ********************************************************************* */
2140 static irqreturn_t sbmac_intr(int irq,void *dev_instance)
2141 {
2142 struct net_device *dev = (struct net_device *) dev_instance;
2143 struct sbmac_softc *sc = netdev_priv(dev);
2144 uint64_t isr;
2145 int handled = 0;
2146
2147 /*
2148 * Read the ISR (this clears the bits in the real
2149 * register, except for counter addr)
2150 */
2151
2152 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2153
2154 if (isr == 0)
2155 return IRQ_RETVAL(0);
2156 handled = 1;
2157
2158 /*
2159 * Transmits on channel 0
2160 */
2161
2162 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0))
2163 sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2164
2165 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2166 if (netif_rx_schedule_prep(dev, &sc->napi)) {
2167 __raw_writeq(0, sc->sbm_imr);
2168 __netif_rx_schedule(dev, &sc->napi);
2169 /* Depend on the exit from poll to reenable intr */
2170 }
2171 else {
2172 /* may leave some packets behind */
2173 sbdma_rx_process(sc,&(sc->sbm_rxdma),
2174 SBMAC_MAX_RXDESCR * 2, 0);
2175 }
2176 }
2177 return IRQ_RETVAL(handled);
2178 }
2179
2180 /**********************************************************************
2181 * SBMAC_START_TX(skb,dev)
2182 *
2183 * Start output on the specified interface. Basically, we
2184 * queue as many buffers as we can until the ring fills up, or
2185 * we run off the end of the queue, whichever comes first.
2186 *
2187 * Input parameters:
2188 *
2189 *
2190 * Return value:
2191 * nothing
2192 ********************************************************************* */
2193 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2194 {
2195 struct sbmac_softc *sc = netdev_priv(dev);
2196
2197 /* lock eth irq */
2198 spin_lock_irq (&sc->sbm_lock);
2199
2200 /*
2201 * Put the buffer on the transmit ring. If we
2202 * don't have room, stop the queue.
2203 */
2204
2205 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2206 /* XXX save skb that we could not send */
2207 netif_stop_queue(dev);
2208 spin_unlock_irq(&sc->sbm_lock);
2209
2210 return 1;
2211 }
2212
2213 dev->trans_start = jiffies;
2214
2215 spin_unlock_irq (&sc->sbm_lock);
2216
2217 return 0;
2218 }
2219
2220 /**********************************************************************
2221 * SBMAC_SETMULTI(sc)
2222 *
2223 * Reprogram the multicast table into the hardware, given
2224 * the list of multicasts associated with the interface
2225 * structure.
2226 *
2227 * Input parameters:
2228 * sc - softc
2229 *
2230 * Return value:
2231 * nothing
2232 ********************************************************************* */
2233
2234 static void sbmac_setmulti(struct sbmac_softc *sc)
2235 {
2236 uint64_t reg;
2237 void __iomem *port;
2238 int idx;
2239 struct dev_mc_list *mclist;
2240 struct net_device *dev = sc->sbm_dev;
2241
2242 /*
2243 * Clear out entire multicast table. We do this by nuking
2244 * the entire hash table and all the direct matches except
2245 * the first one, which is used for our station address
2246 */
2247
2248 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2249 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2250 __raw_writeq(0, port);
2251 }
2252
2253 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2254 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2255 __raw_writeq(0, port);
2256 }
2257
2258 /*
2259 * Clear the filter to say we don't want any multicasts.
2260 */
2261
2262 reg = __raw_readq(sc->sbm_rxfilter);
2263 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2264 __raw_writeq(reg, sc->sbm_rxfilter);
2265
2266 if (dev->flags & IFF_ALLMULTI) {
2267 /*
2268 * Enable ALL multicasts. Do this by inverting the
2269 * multicast enable bit.
2270 */
2271 reg = __raw_readq(sc->sbm_rxfilter);
2272 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2273 __raw_writeq(reg, sc->sbm_rxfilter);
2274 return;
2275 }
2276
2277
2278 /*
2279 * Progam new multicast entries. For now, only use the
2280 * perfect filter. In the future we'll need to use the
2281 * hash filter if the perfect filter overflows
2282 */
2283
2284 /* XXX only using perfect filter for now, need to use hash
2285 * XXX if the table overflows */
2286
2287 idx = 1; /* skip station address */
2288 mclist = dev->mc_list;
2289 while (mclist && (idx < MAC_ADDR_COUNT)) {
2290 reg = sbmac_addr2reg(mclist->dmi_addr);
2291 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2292 __raw_writeq(reg, port);
2293 idx++;
2294 mclist = mclist->next;
2295 }
2296
2297 /*
2298 * Enable the "accept multicast bits" if we programmed at least one
2299 * multicast.
2300 */
2301
2302 if (idx > 1) {
2303 reg = __raw_readq(sc->sbm_rxfilter);
2304 reg |= M_MAC_MCAST_EN;
2305 __raw_writeq(reg, sc->sbm_rxfilter);
2306 }
2307 }
2308
2309 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2310 /**********************************************************************
2311 * SBMAC_PARSE_XDIGIT(str)
2312 *
2313 * Parse a hex digit, returning its value
2314 *
2315 * Input parameters:
2316 * str - character
2317 *
2318 * Return value:
2319 * hex value, or -1 if invalid
2320 ********************************************************************* */
2321
2322 static int sbmac_parse_xdigit(char str)
2323 {
2324 int digit;
2325
2326 if ((str >= '0') && (str <= '9'))
2327 digit = str - '0';
2328 else if ((str >= 'a') && (str <= 'f'))
2329 digit = str - 'a' + 10;
2330 else if ((str >= 'A') && (str <= 'F'))
2331 digit = str - 'A' + 10;
2332 else
2333 return -1;
2334
2335 return digit;
2336 }
2337
2338 /**********************************************************************
2339 * SBMAC_PARSE_HWADDR(str,hwaddr)
2340 *
2341 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2342 * Ethernet address.
2343 *
2344 * Input parameters:
2345 * str - string
2346 * hwaddr - pointer to hardware address
2347 *
2348 * Return value:
2349 * 0 if ok, else -1
2350 ********************************************************************* */
2351
2352 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2353 {
2354 int digit1,digit2;
2355 int idx = 6;
2356
2357 while (*str && (idx > 0)) {
2358 digit1 = sbmac_parse_xdigit(*str);
2359 if (digit1 < 0)
2360 return -1;
2361 str++;
2362 if (!*str)
2363 return -1;
2364
2365 if ((*str == ':') || (*str == '-')) {
2366 digit2 = digit1;
2367 digit1 = 0;
2368 }
2369 else {
2370 digit2 = sbmac_parse_xdigit(*str);
2371 if (digit2 < 0)
2372 return -1;
2373 str++;
2374 }
2375
2376 *hwaddr++ = (digit1 << 4) | digit2;
2377 idx--;
2378
2379 if (*str == '-')
2380 str++;
2381 if (*str == ':')
2382 str++;
2383 }
2384 return 0;
2385 }
2386 #endif
2387
2388 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2389 {
2390 if (new_mtu > ENET_PACKET_SIZE)
2391 return -EINVAL;
2392 _dev->mtu = new_mtu;
2393 printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2394 return 0;
2395 }
2396
2397 /**********************************************************************
2398 * SBMAC_INIT(dev)
2399 *
2400 * Attach routine - init hardware and hook ourselves into linux
2401 *
2402 * Input parameters:
2403 * dev - net_device structure
2404 *
2405 * Return value:
2406 * status
2407 ********************************************************************* */
2408
2409 static int sbmac_init(struct net_device *dev, int idx)
2410 {
2411 struct sbmac_softc *sc;
2412 unsigned char *eaddr;
2413 uint64_t ea_reg;
2414 int i;
2415 int err;
2416 DECLARE_MAC_BUF(mac);
2417
2418 sc = netdev_priv(dev);
2419
2420 /* Determine controller base address */
2421
2422 sc->sbm_base = IOADDR(dev->base_addr);
2423 sc->sbm_dev = dev;
2424 sc->sbe_idx = idx;
2425
2426 eaddr = sc->sbm_hwaddr;
2427
2428 /*
2429 * Read the ethernet address. The firwmare left this programmed
2430 * for us in the ethernet address register for each mac.
2431 */
2432
2433 ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2434 __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2435 for (i = 0; i < 6; i++) {
2436 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2437 ea_reg >>= 8;
2438 }
2439
2440 for (i = 0; i < 6; i++) {
2441 dev->dev_addr[i] = eaddr[i];
2442 }
2443
2444
2445 /*
2446 * Init packet size
2447 */
2448
2449 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2450
2451 /*
2452 * Initialize context (get pointers to registers and stuff), then
2453 * allocate the memory for the descriptor tables.
2454 */
2455
2456 sbmac_initctx(sc);
2457
2458 /*
2459 * Set up Linux device callins
2460 */
2461
2462 spin_lock_init(&(sc->sbm_lock));
2463
2464 dev->open = sbmac_open;
2465 dev->hard_start_xmit = sbmac_start_tx;
2466 dev->stop = sbmac_close;
2467 dev->set_multicast_list = sbmac_set_rx_mode;
2468 dev->do_ioctl = sbmac_mii_ioctl;
2469 dev->tx_timeout = sbmac_tx_timeout;
2470 dev->watchdog_timeo = TX_TIMEOUT;
2471
2472 netif_napi_add(dev, &sc->napi, sbmac_poll, 16);
2473
2474 dev->change_mtu = sb1250_change_mtu;
2475 #ifdef CONFIG_NET_POLL_CONTROLLER
2476 dev->poll_controller = sbmac_netpoll;
2477 #endif
2478
2479 /* This is needed for PASS2 for Rx H/W checksum feature */
2480 sbmac_set_iphdr_offset(sc);
2481
2482 err = register_netdev(dev);
2483 if (err)
2484 goto out_uninit;
2485
2486 if (sc->rx_hw_checksum == ENABLE) {
2487 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
2488 sc->sbm_dev->name);
2489 }
2490
2491 /*
2492 * Display Ethernet address (this is called during the config
2493 * process so we need to finish off the config message that
2494 * was being displayed)
2495 */
2496 printk(KERN_INFO
2497 "%s: SiByte Ethernet at 0x%08lX, address: %s\n",
2498 dev->name, dev->base_addr, print_mac(mac, eaddr));
2499
2500 return 0;
2501
2502 out_uninit:
2503 sbmac_uninitctx(sc);
2504
2505 return err;
2506 }
2507
2508
2509 static int sbmac_open(struct net_device *dev)
2510 {
2511 struct sbmac_softc *sc = netdev_priv(dev);
2512
2513 if (debug > 1) {
2514 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2515 }
2516
2517 /*
2518 * map/route interrupt (clear status first, in case something
2519 * weird is pending; we haven't initialized the mac registers
2520 * yet)
2521 */
2522
2523 __raw_readq(sc->sbm_isr);
2524 if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev))
2525 return -EBUSY;
2526
2527 /*
2528 * Probe phy address
2529 */
2530
2531 if(sbmac_mii_probe(dev) == -1) {
2532 printk("%s: failed to probe PHY.\n", dev->name);
2533 return -EINVAL;
2534 }
2535
2536 napi_enable(&sc->napi);
2537
2538 /*
2539 * Configure default speed
2540 */
2541
2542 sbmac_mii_poll(sc,noisy_mii);
2543
2544 /*
2545 * Turn on the channel
2546 */
2547
2548 sbmac_set_channel_state(sc,sbmac_state_on);
2549
2550 /*
2551 * XXX Station address is in dev->dev_addr
2552 */
2553
2554 if (dev->if_port == 0)
2555 dev->if_port = 0;
2556
2557 netif_start_queue(dev);
2558
2559 sbmac_set_rx_mode(dev);
2560
2561 /* Set the timer to check for link beat. */
2562 init_timer(&sc->sbm_timer);
2563 sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2564 sc->sbm_timer.data = (unsigned long)dev;
2565 sc->sbm_timer.function = &sbmac_timer;
2566 add_timer(&sc->sbm_timer);
2567
2568 return 0;
2569 }
2570
2571 static int sbmac_mii_probe(struct net_device *dev)
2572 {
2573 int i;
2574 struct sbmac_softc *s = netdev_priv(dev);
2575 u16 bmsr, id1, id2;
2576 u32 vendor, device;
2577
2578 for (i=1; i<31; i++) {
2579 bmsr = sbmac_mii_read(s, i, MII_BMSR);
2580 if (bmsr != 0) {
2581 s->sbm_phys[0] = i;
2582 id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
2583 id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
2584 vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
2585 device = (id2 >> 4) & 0x3f;
2586
2587 printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
2588 dev->name, i, vendor, device);
2589 return i;
2590 }
2591 }
2592 return -1;
2593 }
2594
2595
2596 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2597 {
2598 int bmsr,bmcr,k1stsr,anlpar;
2599 int chg;
2600 char buffer[100];
2601 char *p = buffer;
2602
2603 /* Read the mode status and mode control registers. */
2604 bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2605 bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2606
2607 /* get the link partner status */
2608 anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2609
2610 /* if supported, read the 1000baseT register */
2611 if (bmsr & BMSR_1000BT_XSR) {
2612 k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2613 }
2614 else {
2615 k1stsr = 0;
2616 }
2617
2618 chg = 0;
2619
2620 if ((bmsr & BMSR_LINKSTAT) == 0) {
2621 /*
2622 * If link status is down, clear out old info so that when
2623 * it comes back up it will force us to reconfigure speed
2624 */
2625 s->sbm_phy_oldbmsr = 0;
2626 s->sbm_phy_oldanlpar = 0;
2627 s->sbm_phy_oldk1stsr = 0;
2628 return 0;
2629 }
2630
2631 if ((s->sbm_phy_oldbmsr != bmsr) ||
2632 (s->sbm_phy_oldanlpar != anlpar) ||
2633 (s->sbm_phy_oldk1stsr != k1stsr)) {
2634 if (debug > 1) {
2635 printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n",
2636 s->sbm_dev->name,
2637 s->sbm_phy_oldbmsr,bmsr,
2638 s->sbm_phy_oldanlpar,anlpar,
2639 s->sbm_phy_oldk1stsr,k1stsr);
2640 }
2641 s->sbm_phy_oldbmsr = bmsr;
2642 s->sbm_phy_oldanlpar = anlpar;
2643 s->sbm_phy_oldk1stsr = k1stsr;
2644 chg = 1;
2645 }
2646
2647 if (chg == 0)
2648 return 0;
2649
2650 p += sprintf(p,"Link speed: ");
2651
2652 if (k1stsr & K1STSR_LP1KFD) {
2653 s->sbm_speed = sbmac_speed_1000;
2654 s->sbm_duplex = sbmac_duplex_full;
2655 s->sbm_fc = sbmac_fc_frame;
2656 p += sprintf(p,"1000BaseT FDX");
2657 }
2658 else if (k1stsr & K1STSR_LP1KHD) {
2659 s->sbm_speed = sbmac_speed_1000;
2660 s->sbm_duplex = sbmac_duplex_half;
2661 s->sbm_fc = sbmac_fc_disabled;
2662 p += sprintf(p,"1000BaseT HDX");
2663 }
2664 else if (anlpar & ANLPAR_TXFD) {
2665 s->sbm_speed = sbmac_speed_100;
2666 s->sbm_duplex = sbmac_duplex_full;
2667 s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2668 p += sprintf(p,"100BaseT FDX");
2669 }
2670 else if (anlpar & ANLPAR_TXHD) {
2671 s->sbm_speed = sbmac_speed_100;
2672 s->sbm_duplex = sbmac_duplex_half;
2673 s->sbm_fc = sbmac_fc_disabled;
2674 p += sprintf(p,"100BaseT HDX");
2675 }
2676 else if (anlpar & ANLPAR_10FD) {
2677 s->sbm_speed = sbmac_speed_10;
2678 s->sbm_duplex = sbmac_duplex_full;
2679 s->sbm_fc = sbmac_fc_frame;
2680 p += sprintf(p,"10BaseT FDX");
2681 }
2682 else if (anlpar & ANLPAR_10HD) {
2683 s->sbm_speed = sbmac_speed_10;
2684 s->sbm_duplex = sbmac_duplex_half;
2685 s->sbm_fc = sbmac_fc_collision;
2686 p += sprintf(p,"10BaseT HDX");
2687 }
2688 else {
2689 p += sprintf(p,"Unknown");
2690 }
2691
2692 if (noisy) {
2693 printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2694 }
2695
2696 return 1;
2697 }
2698
2699
2700 static void sbmac_timer(unsigned long data)
2701 {
2702 struct net_device *dev = (struct net_device *)data;
2703 struct sbmac_softc *sc = netdev_priv(dev);
2704 int next_tick = HZ;
2705 int mii_status;
2706
2707 spin_lock_irq (&sc->sbm_lock);
2708
2709 /* make IFF_RUNNING follow the MII status bit "Link established" */
2710 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2711
2712 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2713 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2714 if (mii_status & BMSR_LINKSTAT) {
2715 netif_carrier_on(dev);
2716 }
2717 else {
2718 netif_carrier_off(dev);
2719 }
2720 }
2721
2722 /*
2723 * Poll the PHY to see what speed we should be running at
2724 */
2725
2726 if (sbmac_mii_poll(sc,noisy_mii)) {
2727 if (sc->sbm_state != sbmac_state_off) {
2728 /*
2729 * something changed, restart the channel
2730 */
2731 if (debug > 1) {
2732 printk("%s: restarting channel because speed changed\n",
2733 sc->sbm_dev->name);
2734 }
2735 sbmac_channel_stop(sc);
2736 sbmac_channel_start(sc);
2737 }
2738 }
2739
2740 spin_unlock_irq (&sc->sbm_lock);
2741
2742 sc->sbm_timer.expires = jiffies + next_tick;
2743 add_timer(&sc->sbm_timer);
2744 }
2745
2746
2747 static void sbmac_tx_timeout (struct net_device *dev)
2748 {
2749 struct sbmac_softc *sc = netdev_priv(dev);
2750
2751 spin_lock_irq (&sc->sbm_lock);
2752
2753
2754 dev->trans_start = jiffies;
2755 dev->stats.tx_errors++;
2756
2757 spin_unlock_irq (&sc->sbm_lock);
2758
2759 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2760 }
2761
2762
2763
2764
2765 static void sbmac_set_rx_mode(struct net_device *dev)
2766 {
2767 unsigned long flags;
2768 struct sbmac_softc *sc = netdev_priv(dev);
2769
2770 spin_lock_irqsave(&sc->sbm_lock, flags);
2771 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2772 /*
2773 * Promiscuous changed.
2774 */
2775
2776 if (dev->flags & IFF_PROMISC) {
2777 sbmac_promiscuous_mode(sc,1);
2778 }
2779 else {
2780 sbmac_promiscuous_mode(sc,0);
2781 }
2782 }
2783 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2784
2785 /*
2786 * Program the multicasts. Do this every time.
2787 */
2788
2789 sbmac_setmulti(sc);
2790
2791 }
2792
2793 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2794 {
2795 struct sbmac_softc *sc = netdev_priv(dev);
2796 u16 *data = (u16 *)&rq->ifr_ifru;
2797 unsigned long flags;
2798 int retval;
2799
2800 spin_lock_irqsave(&sc->sbm_lock, flags);
2801 retval = 0;
2802
2803 switch(cmd) {
2804 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2805 data[0] = sc->sbm_phys[0] & 0x1f;
2806 /* Fall Through */
2807 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2808 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2809 break;
2810 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2811 if (!capable(CAP_NET_ADMIN)) {
2812 retval = -EPERM;
2813 break;
2814 }
2815 if (debug > 1) {
2816 printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2817 data[0],data[1],data[2]);
2818 }
2819 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2820 break;
2821 default:
2822 retval = -EOPNOTSUPP;
2823 }
2824
2825 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2826 return retval;
2827 }
2828
2829 static int sbmac_close(struct net_device *dev)
2830 {
2831 struct sbmac_softc *sc = netdev_priv(dev);
2832 unsigned long flags;
2833 int irq;
2834
2835 napi_disable(&sc->napi);
2836
2837 sbmac_set_channel_state(sc,sbmac_state_off);
2838
2839 del_timer_sync(&sc->sbm_timer);
2840
2841 spin_lock_irqsave(&sc->sbm_lock, flags);
2842
2843 netif_stop_queue(dev);
2844
2845 if (debug > 1) {
2846 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2847 }
2848
2849 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2850
2851 irq = dev->irq;
2852 synchronize_irq(irq);
2853 free_irq(irq, dev);
2854
2855 sbdma_emptyring(&(sc->sbm_txdma));
2856 sbdma_emptyring(&(sc->sbm_rxdma));
2857
2858 return 0;
2859 }
2860
2861 static int sbmac_poll(struct napi_struct *napi, int budget)
2862 {
2863 struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi);
2864 struct net_device *dev = sc->sbm_dev;
2865 int work_done;
2866
2867 work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1);
2868 sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2869
2870 if (work_done < budget) {
2871 netif_rx_complete(dev, napi);
2872
2873 #ifdef CONFIG_SBMAC_COALESCE
2874 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
2875 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2876 sc->sbm_imr);
2877 #else
2878 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
2879 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2880 #endif
2881 }
2882
2883 return work_done;
2884 }
2885
2886 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2887 static void
2888 sbmac_setup_hwaddr(int chan,char *addr)
2889 {
2890 uint8_t eaddr[6];
2891 uint64_t val;
2892 unsigned long port;
2893
2894 port = A_MAC_CHANNEL_BASE(chan);
2895 sbmac_parse_hwaddr(addr,eaddr);
2896 val = sbmac_addr2reg(eaddr);
2897 __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR));
2898 val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2899 }
2900 #endif
2901
2902 static struct net_device *dev_sbmac[MAX_UNITS];
2903
2904 static int __init
2905 sbmac_init_module(void)
2906 {
2907 int idx;
2908 struct net_device *dev;
2909 unsigned long port;
2910 int chip_max_units;
2911
2912 /* Set the number of available units based on the SOC type. */
2913 switch (soc_type) {
2914 case K_SYS_SOC_TYPE_BCM1250:
2915 case K_SYS_SOC_TYPE_BCM1250_ALT:
2916 chip_max_units = 3;
2917 break;
2918 case K_SYS_SOC_TYPE_BCM1120:
2919 case K_SYS_SOC_TYPE_BCM1125:
2920 case K_SYS_SOC_TYPE_BCM1125H:
2921 case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2922 chip_max_units = 2;
2923 break;
2924 case K_SYS_SOC_TYPE_BCM1x55:
2925 case K_SYS_SOC_TYPE_BCM1x80:
2926 chip_max_units = 4;
2927 break;
2928 default:
2929 chip_max_units = 0;
2930 break;
2931 }
2932 if (chip_max_units > MAX_UNITS)
2933 chip_max_units = MAX_UNITS;
2934
2935 /*
2936 * For bringup when not using the firmware, we can pre-fill
2937 * the MAC addresses using the environment variables
2938 * specified in this file (or maybe from the config file?)
2939 */
2940 #ifdef SBMAC_ETH0_HWADDR
2941 if (chip_max_units > 0)
2942 sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2943 #endif
2944 #ifdef SBMAC_ETH1_HWADDR
2945 if (chip_max_units > 1)
2946 sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2947 #endif
2948 #ifdef SBMAC_ETH2_HWADDR
2949 if (chip_max_units > 2)
2950 sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2951 #endif
2952 #ifdef SBMAC_ETH3_HWADDR
2953 if (chip_max_units > 3)
2954 sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR);
2955 #endif
2956
2957 /*
2958 * Walk through the Ethernet controllers and find
2959 * those who have their MAC addresses set.
2960 */
2961 for (idx = 0; idx < chip_max_units; idx++) {
2962
2963 /*
2964 * This is the base address of the MAC.
2965 */
2966
2967 port = A_MAC_CHANNEL_BASE(idx);
2968
2969 /*
2970 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2971 * value for us by the firmware if we are going to use this MAC.
2972 * If we find a zero, skip this MAC.
2973 */
2974
2975 sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2976 if (sbmac_orig_hwaddr[idx] == 0) {
2977 printk(KERN_DEBUG "sbmac: not configuring MAC at "
2978 "%lx\n", port);
2979 continue;
2980 }
2981
2982 /*
2983 * Okay, cool. Initialize this MAC.
2984 */
2985
2986 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2987 if (!dev)
2988 return -ENOMEM;
2989
2990 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2991
2992 dev->irq = UNIT_INT(idx);
2993 dev->base_addr = port;
2994 dev->mem_end = 0;
2995 if (sbmac_init(dev, idx)) {
2996 port = A_MAC_CHANNEL_BASE(idx);
2997 __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
2998 free_netdev(dev);
2999 continue;
3000 }
3001 dev_sbmac[idx] = dev;
3002 }
3003 return 0;
3004 }
3005
3006
3007 static void __exit
3008 sbmac_cleanup_module(void)
3009 {
3010 struct net_device *dev;
3011 int idx;
3012
3013 for (idx = 0; idx < MAX_UNITS; idx++) {
3014 struct sbmac_softc *sc;
3015 dev = dev_sbmac[idx];
3016 if (!dev)
3017 continue;
3018
3019 sc = netdev_priv(dev);
3020 unregister_netdev(dev);
3021 sbmac_uninitctx(sc);
3022 free_netdev(dev);
3023 }
3024 }
3025
3026 module_init(sbmac_init_module);
3027 module_exit(sbmac_cleanup_module);
Support for the Chinese Samsung S3C2440 based development boards