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md: Fix unfortunate interaction with evms
[linux-2.6/mini2440.git] / drivers / scsi / gdth.c
blob9e8fce0f0c1b3f1022b5658a2ad503fcc810abf6
1 /************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
8 * Copyright (C) 2002-04 Intel Corporation *
9 * Copyright (C) 2003-06 Adaptec Inc. *
10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
30 * Linux kernel 2.6.x supported *
31 * *
32 ************************************************************************/
33
34 /* All GDT Disk Array Controllers are fully supported by this driver.
35 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
36 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
37 * list of all controller types.
38 *
39 * If you have one or more GDT3000/3020 EISA controllers with
40 * controller BIOS disabled, you have to set the IRQ values with the
41 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
42 * the IRQ values for the EISA controllers.
43 *
44 * After the optional list of IRQ values, other possible
45 * command line options are:
46 * disable:Y disable driver
47 * disable:N enable driver
48 * reserve_mode:0 reserve no drives for the raw service
49 * reserve_mode:1 reserve all not init., removable drives
50 * reserve_mode:2 reserve all not init. drives
51 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
52 * h- controller no., b- channel no.,
53 * t- target ID, l- LUN
54 * reverse_scan:Y reverse scan order for PCI controllers
55 * reverse_scan:N scan PCI controllers like BIOS
56 * max_ids:x x - target ID count per channel (1..MAXID)
57 * rescan:Y rescan all channels/IDs
58 * rescan:N use all devices found until now
59 * hdr_channel:x x - number of virtual bus for host drives
60 * shared_access:Y disable driver reserve/release protocol to
61 * access a shared resource from several nodes,
62 * appropriate controller firmware required
63 * shared_access:N enable driver reserve/release protocol
64 * probe_eisa_isa:Y scan for EISA/ISA controllers
65 * probe_eisa_isa:N do not scan for EISA/ISA controllers
66 * force_dma32:Y use only 32 bit DMA mode
67 * force_dma32:N use 64 bit DMA mode, if supported
68 *
69 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
70 * max_ids:127,rescan:N,hdr_channel:0,
71 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
72 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
73 *
74 * When loading the gdth driver as a module, the same options are available.
75 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
76 * options changes slightly. You must replace all ',' between options
77 * with ' ' and all ':' with '=' and you must use
78 * '1' in place of 'Y' and '0' in place of 'N'.
79 *
80 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
81 * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
82 * probe_eisa_isa=0 force_dma32=0"
83 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
84 */
85
86 /* The meaning of the Scsi_Pointer members in this driver is as follows:
87 * ptr: Chaining
88 * this_residual: unused
89 * buffer: unused
90 * dma_handle: unused
91 * buffers_residual: unused
92 * Status: unused
93 * Message: unused
94 * have_data_in: unused
95 * sent_command: unused
96 * phase: unused
97 */
98
99
100 /* interrupt coalescing */
101 /* #define INT_COAL */
102
103 /* statistics */
104 #define GDTH_STATISTICS
105
106 #include <linux/module.h>
107
108 #include <linux/version.h>
109 #include <linux/kernel.h>
110 #include <linux/types.h>
111 #include <linux/pci.h>
112 #include <linux/string.h>
113 #include <linux/ctype.h>
114 #include <linux/ioport.h>
115 #include <linux/delay.h>
116 #include <linux/interrupt.h>
117 #include <linux/in.h>
118 #include <linux/proc_fs.h>
119 #include <linux/time.h>
120 #include <linux/timer.h>
121 #include <linux/dma-mapping.h>
122 #include <linux/list.h>
123 #include <linux/smp_lock.h>
124
125 #ifdef GDTH_RTC
126 #include <linux/mc146818rtc.h>
127 #endif
128 #include <linux/reboot.h>
129
130 #include <asm/dma.h>
131 #include <asm/system.h>
132 #include <asm/io.h>
133 #include <asm/uaccess.h>
134 #include <linux/spinlock.h>
135 #include <linux/blkdev.h>
136 #include <linux/scatterlist.h>
137
138 #include "scsi.h"
139 #include <scsi/scsi_host.h>
140 #include "gdth.h"
141
142 static void gdth_delay(int milliseconds);
143 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
144 static irqreturn_t gdth_interrupt(int irq, void *dev_id);
145 static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
146 int gdth_from_wait, int* pIndex);
147 static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
148 Scsi_Cmnd *scp);
149 static int gdth_async_event(gdth_ha_str *ha);
150 static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
151
152 static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
153 static void gdth_next(gdth_ha_str *ha);
154 static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
155 static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
156 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
157 ushort idx, gdth_evt_data *evt);
158 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
159 static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
160 gdth_evt_str *estr);
161 static void gdth_clear_events(void);
162
163 static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
164 char *buffer, ushort count);
165 static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
166 static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
167
168 static void gdth_enable_int(gdth_ha_str *ha);
169 static int gdth_test_busy(gdth_ha_str *ha);
170 static int gdth_get_cmd_index(gdth_ha_str *ha);
171 static void gdth_release_event(gdth_ha_str *ha);
172 static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
173 static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
174 ulong32 p1, ulong64 p2,ulong64 p3);
175 static int gdth_search_drives(gdth_ha_str *ha);
176 static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
177
178 static const char *gdth_ctr_name(gdth_ha_str *ha);
179
180 static int gdth_open(struct inode *inode, struct file *filep);
181 static int gdth_close(struct inode *inode, struct file *filep);
182 static int gdth_ioctl(struct inode *inode, struct file *filep,
183 unsigned int cmd, unsigned long arg);
184
185 static void gdth_flush(gdth_ha_str *ha);
186 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
187 static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
188 struct gdth_cmndinfo *cmndinfo);
189 static void gdth_scsi_done(struct scsi_cmnd *scp);
190
191 #ifdef DEBUG_GDTH
192 static unchar DebugState = DEBUG_GDTH;
193
194 #ifdef __SERIAL__
195 #define MAX_SERBUF 160
196 static void ser_init(void);
197 static void ser_puts(char *str);
198 static void ser_putc(char c);
199 static int ser_printk(const char *fmt, ...);
200 static char strbuf[MAX_SERBUF+1];
201 #ifdef __COM2__
202 #define COM_BASE 0x2f8
203 #else
204 #define COM_BASE 0x3f8
205 #endif
206 static void ser_init()
207 {
208 unsigned port=COM_BASE;
209
210 outb(0x80,port+3);
211 outb(0,port+1);
212 /* 19200 Baud, if 9600: outb(12,port) */
213 outb(6, port);
214 outb(3,port+3);
215 outb(0,port+1);
216 /*
217 ser_putc('I');
218 ser_putc(' ');
219 */
220 }
221
222 static void ser_puts(char *str)
223 {
224 char *ptr;
225
226 ser_init();
227 for (ptr=str;*ptr;++ptr)
228 ser_putc(*ptr);
229 }
230
231 static void ser_putc(char c)
232 {
233 unsigned port=COM_BASE;
234
235 while ((inb(port+5) & 0x20)==0);
236 outb(c,port);
237 if (c==0x0a)
238 {
239 while ((inb(port+5) & 0x20)==0);
240 outb(0x0d,port);
241 }
242 }
243
244 static int ser_printk(const char *fmt, ...)
245 {
246 va_list args;
247 int i;
248
249 va_start(args,fmt);
250 i = vsprintf(strbuf,fmt,args);
251 ser_puts(strbuf);
252 va_end(args);
253 return i;
254 }
255
256 #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
257 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
258 #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
259
260 #else /* !__SERIAL__ */
261 #define TRACE(a) {if (DebugState==1) {printk a;}}
262 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
263 #define TRACE3(a) {if (DebugState!=0) {printk a;}}
264 #endif
265
266 #else /* !DEBUG */
267 #define TRACE(a)
268 #define TRACE2(a)
269 #define TRACE3(a)
270 #endif
271
272 #ifdef GDTH_STATISTICS
273 static ulong32 max_rq=0, max_index=0, max_sg=0;
274 #ifdef INT_COAL
275 static ulong32 max_int_coal=0;
276 #endif
277 static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
278 static struct timer_list gdth_timer;
279 #endif
280
281 #define PTR2USHORT(a) (ushort)(ulong)(a)
282 #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
283 #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
284
285 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
286
287 #ifdef CONFIG_ISA
288 static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
289 #endif
290 #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
291 static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
292 #endif
293 static unchar gdth_polling; /* polling if TRUE */
294 static int gdth_ctr_count = 0; /* controller count */
295 static LIST_HEAD(gdth_instances); /* controller list */
296 static unchar gdth_write_through = FALSE; /* write through */
297 static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
298 static int elastidx;
299 static int eoldidx;
300 static int major;
301
302 #define DIN 1 /* IN data direction */
303 #define DOU 2 /* OUT data direction */
304 #define DNO DIN /* no data transfer */
305 #define DUN DIN /* unknown data direction */
306 static unchar gdth_direction_tab[0x100] = {
307 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
308 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
309 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
310 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
311 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
312 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
313 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
314 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
315 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
316 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
317 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
318 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
319 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
320 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
321 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
322 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
323 };
324
325 /* LILO and modprobe/insmod parameters */
326 /* IRQ list for GDT3000/3020 EISA controllers */
327 static int irq[MAXHA] __initdata =
328 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
329 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
330 /* disable driver flag */
331 static int disable __initdata = 0;
332 /* reserve flag */
333 static int reserve_mode = 1;
334 /* reserve list */
335 static int reserve_list[MAX_RES_ARGS] =
336 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
337 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
338 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
339 /* scan order for PCI controllers */
340 static int reverse_scan = 0;
341 /* virtual channel for the host drives */
342 static int hdr_channel = 0;
343 /* max. IDs per channel */
344 static int max_ids = MAXID;
345 /* rescan all IDs */
346 static int rescan = 0;
347 /* shared access */
348 static int shared_access = 1;
349 /* enable support for EISA and ISA controllers */
350 static int probe_eisa_isa = 0;
351 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
352 static int force_dma32 = 0;
353
354 /* parameters for modprobe/insmod */
355 module_param_array(irq, int, NULL, 0);
356 module_param(disable, int, 0);
357 module_param(reserve_mode, int, 0);
358 module_param_array(reserve_list, int, NULL, 0);
359 module_param(reverse_scan, int, 0);
360 module_param(hdr_channel, int, 0);
361 module_param(max_ids, int, 0);
362 module_param(rescan, int, 0);
363 module_param(shared_access, int, 0);
364 module_param(probe_eisa_isa, int, 0);
365 module_param(force_dma32, int, 0);
366 MODULE_AUTHOR("Achim Leubner");
367 MODULE_LICENSE("GPL");
368
369 /* ioctl interface */
370 static const struct file_operations gdth_fops = {
371 .ioctl = gdth_ioctl,
372 .open = gdth_open,
373 .release = gdth_close,
374 };
375
376 #include "gdth_proc.h"
377 #include "gdth_proc.c"
378
379 static gdth_ha_str *gdth_find_ha(int hanum)
380 {
381 gdth_ha_str *ha;
382
383 list_for_each_entry(ha, &gdth_instances, list)
384 if (hanum == ha->hanum)
385 return ha;
386
387 return NULL;
388 }
389
390 static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
391 {
392 struct gdth_cmndinfo *priv = NULL;
393 ulong flags;
394 int i;
395
396 spin_lock_irqsave(&ha->smp_lock, flags);
397
398 for (i=0; i<GDTH_MAXCMDS; ++i) {
399 if (ha->cmndinfo[i].index == 0) {
400 priv = &ha->cmndinfo[i];
401 memset(priv, 0, sizeof(*priv));
402 priv->index = i+1;
403 break;
404 }
405 }
406
407 spin_unlock_irqrestore(&ha->smp_lock, flags);
408
409 return priv;
410 }
411
412 static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
413 {
414 BUG_ON(!priv);
415 priv->index = 0;
416 }
417
418 static void gdth_delay(int milliseconds)
419 {
420 if (milliseconds == 0) {
421 udelay(1);
422 } else {
423 mdelay(milliseconds);
424 }
425 }
426
427 static void gdth_scsi_done(struct scsi_cmnd *scp)
428 {
429 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
430 int internal_command = cmndinfo->internal_command;
431
432 TRACE2(("gdth_scsi_done()\n"));
433
434 gdth_put_cmndinfo(cmndinfo);
435 scp->host_scribble = NULL;
436
437 if (internal_command)
438 complete((struct completion *)scp->request);
439 else
440 scp->scsi_done(scp);
441 }
442
443 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
444 int timeout, u32 *info)
445 {
446 gdth_ha_str *ha = shost_priv(sdev->host);
447 Scsi_Cmnd *scp;
448 struct gdth_cmndinfo cmndinfo;
449 DECLARE_COMPLETION_ONSTACK(wait);
450 int rval;
451
452 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
453 if (!scp)
454 return -ENOMEM;
455
456 scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
457 if (!scp->sense_buffer) {
458 kfree(scp);
459 return -ENOMEM;
460 }
461
462 scp->device = sdev;
463 memset(&cmndinfo, 0, sizeof(cmndinfo));
464
465 /* use request field to save the ptr. to completion struct. */
466 scp->request = (struct request *)&wait;
467 scp->cmd_len = 12;
468 scp->cmnd = cmnd;
469 cmndinfo.priority = IOCTL_PRI;
470 cmndinfo.internal_cmd_str = gdtcmd;
471 cmndinfo.internal_command = 1;
472
473 TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
474 __gdth_queuecommand(ha, scp, &cmndinfo);
475
476 wait_for_completion(&wait);
477
478 rval = cmndinfo.status;
479 if (info)
480 *info = cmndinfo.info;
481 kfree(scp->sense_buffer);
482 kfree(scp);
483 return rval;
484 }
485
486 int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
487 int timeout, u32 *info)
488 {
489 struct scsi_device *sdev = scsi_get_host_dev(shost);
490 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
491
492 scsi_free_host_dev(sdev);
493 return rval;
494 }
495
496 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
497 {
498 *cyls = size /HEADS/SECS;
499 if (*cyls <= MAXCYLS) {
500 *heads = HEADS;
501 *secs = SECS;
502 } else { /* too high for 64*32 */
503 *cyls = size /MEDHEADS/MEDSECS;
504 if (*cyls <= MAXCYLS) {
505 *heads = MEDHEADS;
506 *secs = MEDSECS;
507 } else { /* too high for 127*63 */
508 *cyls = size /BIGHEADS/BIGSECS;
509 *heads = BIGHEADS;
510 *secs = BIGSECS;
511 }
512 }
513 }
514
515 /* controller search and initialization functions */
516 #ifdef CONFIG_EISA
517 static int __init gdth_search_eisa(ushort eisa_adr)
518 {
519 ulong32 id;
520
521 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
522 id = inl(eisa_adr+ID0REG);
523 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
524 if ((inb(eisa_adr+EISAREG) & 8) == 0)
525 return 0; /* not EISA configured */
526 return 1;
527 }
528 if (id == GDT3_ID) /* GDT3000 */
529 return 1;
530
531 return 0;
532 }
533 #endif /* CONFIG_EISA */
534
535 #ifdef CONFIG_ISA
536 static int __init gdth_search_isa(ulong32 bios_adr)
537 {
538 void __iomem *addr;
539 ulong32 id;
540
541 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
542 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
543 id = readl(addr);
544 iounmap(addr);
545 if (id == GDT2_ID) /* GDT2000 */
546 return 1;
547 }
548 return 0;
549 }
550 #endif /* CONFIG_ISA */
551
552 #ifdef CONFIG_PCI
553
554 static bool gdth_search_vortex(ushort device)
555 {
556 if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
557 return true;
558 if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
559 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
560 return true;
561 if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
562 device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
563 return true;
564 return false;
565 }
566
567 static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
568 static int gdth_pci_init_one(struct pci_dev *pdev,
569 const struct pci_device_id *ent);
570 static void gdth_pci_remove_one(struct pci_dev *pdev);
571 static void gdth_remove_one(gdth_ha_str *ha);
572
573 /* Vortex only makes RAID controllers.
574 * We do not really want to specify all 550 ids here, so wildcard match.
575 */
576 static const struct pci_device_id gdthtable[] = {
577 { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
578 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
579 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
580 { } /* terminate list */
581 };
582 MODULE_DEVICE_TABLE(pci, gdthtable);
583
584 static struct pci_driver gdth_pci_driver = {
585 .name = "gdth",
586 .id_table = gdthtable,
587 .probe = gdth_pci_init_one,
588 .remove = gdth_pci_remove_one,
589 };
590
591 static void __devexit gdth_pci_remove_one(struct pci_dev *pdev)
592 {
593 gdth_ha_str *ha = pci_get_drvdata(pdev);
594
595 pci_set_drvdata(pdev, NULL);
596
597 list_del(&ha->list);
598 gdth_remove_one(ha);
599
600 pci_disable_device(pdev);
601 }
602
603 static int __devinit gdth_pci_init_one(struct pci_dev *pdev,
604 const struct pci_device_id *ent)
605 {
606 ushort vendor = pdev->vendor;
607 ushort device = pdev->device;
608 ulong base0, base1, base2;
609 int rc;
610 gdth_pci_str gdth_pcistr;
611 gdth_ha_str *ha = NULL;
612
613 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
614 gdth_ctr_count, vendor, device));
615
616 memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
617
618 if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
619 return -ENODEV;
620
621 rc = pci_enable_device(pdev);
622 if (rc)
623 return rc;
624
625 if (gdth_ctr_count >= MAXHA)
626 return -EBUSY;
627
628 /* GDT PCI controller found, resources are already in pdev */
629 gdth_pcistr.pdev = pdev;
630 base0 = pci_resource_flags(pdev, 0);
631 base1 = pci_resource_flags(pdev, 1);
632 base2 = pci_resource_flags(pdev, 2);
633 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
634 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
635 if (!(base0 & IORESOURCE_MEM))
636 return -ENODEV;
637 gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
638 } else { /* GDT6110, GDT6120, .. */
639 if (!(base0 & IORESOURCE_MEM) ||
640 !(base2 & IORESOURCE_MEM) ||
641 !(base1 & IORESOURCE_IO))
642 return -ENODEV;
643 gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
644 gdth_pcistr.io = pci_resource_start(pdev, 1);
645 }
646 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
647 gdth_pcistr.pdev->bus->number,
648 PCI_SLOT(gdth_pcistr.pdev->devfn),
649 gdth_pcistr.irq,
650 gdth_pcistr.dpmem));
651
652 rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
653 if (rc)
654 return rc;
655
656 return 0;
657 }
658 #endif /* CONFIG_PCI */
659
660 #ifdef CONFIG_EISA
661 static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
662 {
663 ulong32 retries,id;
664 unchar prot_ver,eisacf,i,irq_found;
665
666 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
667
668 /* disable board interrupts, deinitialize services */
669 outb(0xff,eisa_adr+EDOORREG);
670 outb(0x00,eisa_adr+EDENABREG);
671 outb(0x00,eisa_adr+EINTENABREG);
672
673 outb(0xff,eisa_adr+LDOORREG);
674 retries = INIT_RETRIES;
675 gdth_delay(20);
676 while (inb(eisa_adr+EDOORREG) != 0xff) {
677 if (--retries == 0) {
678 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
679 return 0;
680 }
681 gdth_delay(1);
682 TRACE2(("wait for DEINIT: retries=%d\n",retries));
683 }
684 prot_ver = inb(eisa_adr+MAILBOXREG);
685 outb(0xff,eisa_adr+EDOORREG);
686 if (prot_ver != PROTOCOL_VERSION) {
687 printk("GDT-EISA: Illegal protocol version\n");
688 return 0;
689 }
690 ha->bmic = eisa_adr;
691 ha->brd_phys = (ulong32)eisa_adr >> 12;
692
693 outl(0,eisa_adr+MAILBOXREG);
694 outl(0,eisa_adr+MAILBOXREG+4);
695 outl(0,eisa_adr+MAILBOXREG+8);
696 outl(0,eisa_adr+MAILBOXREG+12);
697
698 /* detect IRQ */
699 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
700 ha->oem_id = OEM_ID_ICP;
701 ha->type = GDT_EISA;
702 ha->stype = id;
703 outl(1,eisa_adr+MAILBOXREG+8);
704 outb(0xfe,eisa_adr+LDOORREG);
705 retries = INIT_RETRIES;
706 gdth_delay(20);
707 while (inb(eisa_adr+EDOORREG) != 0xfe) {
708 if (--retries == 0) {
709 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
710 return 0;
711 }
712 gdth_delay(1);
713 }
714 ha->irq = inb(eisa_adr+MAILBOXREG);
715 outb(0xff,eisa_adr+EDOORREG);
716 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
717 /* check the result */
718 if (ha->irq == 0) {
719 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
720 for (i = 0, irq_found = FALSE;
721 i < MAXHA && irq[i] != 0xff; ++i) {
722 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
723 irq_found = TRUE;
724 break;
725 }
726 }
727 if (irq_found) {
728 ha->irq = irq[i];
729 irq[i] = 0;
730 printk("GDT-EISA: Can not detect controller IRQ,\n");
731 printk("Use IRQ setting from command line (IRQ = %d)\n",
732 ha->irq);
733 } else {
734 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
735 printk("the controller BIOS or use command line parameters\n");
736 return 0;
737 }
738 }
739 } else {
740 eisacf = inb(eisa_adr+EISAREG) & 7;
741 if (eisacf > 4) /* level triggered */
742 eisacf -= 4;
743 ha->irq = gdth_irq_tab[eisacf];
744 ha->oem_id = OEM_ID_ICP;
745 ha->type = GDT_EISA;
746 ha->stype = id;
747 }
748
749 ha->dma64_support = 0;
750 return 1;
751 }
752 #endif /* CONFIG_EISA */
753
754 #ifdef CONFIG_ISA
755 static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
756 {
757 register gdt2_dpram_str __iomem *dp2_ptr;
758 int i;
759 unchar irq_drq,prot_ver;
760 ulong32 retries;
761
762 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
763
764 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
765 if (ha->brd == NULL) {
766 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
767 return 0;
768 }
769 dp2_ptr = ha->brd;
770 writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
771 /* reset interface area */
772 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
773 if (readl(&dp2_ptr->u) != 0) {
774 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
775 iounmap(ha->brd);
776 return 0;
777 }
778
779 /* disable board interrupts, read DRQ and IRQ */
780 writeb(0xff, &dp2_ptr->io.irqdel);
781 writeb(0x00, &dp2_ptr->io.irqen);
782 writeb(0x00, &dp2_ptr->u.ic.S_Status);
783 writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
784
785 irq_drq = readb(&dp2_ptr->io.rq);
786 for (i=0; i<3; ++i) {
787 if ((irq_drq & 1)==0)
788 break;
789 irq_drq >>= 1;
790 }
791 ha->drq = gdth_drq_tab[i];
792
793 irq_drq = readb(&dp2_ptr->io.rq) >> 3;
794 for (i=1; i<5; ++i) {
795 if ((irq_drq & 1)==0)
796 break;
797 irq_drq >>= 1;
798 }
799 ha->irq = gdth_irq_tab[i];
800
801 /* deinitialize services */
802 writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
803 writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
804 writeb(0, &dp2_ptr->io.event);
805 retries = INIT_RETRIES;
806 gdth_delay(20);
807 while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
808 if (--retries == 0) {
809 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
810 iounmap(ha->brd);
811 return 0;
812 }
813 gdth_delay(1);
814 }
815 prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
816 writeb(0, &dp2_ptr->u.ic.Status);
817 writeb(0xff, &dp2_ptr->io.irqdel);
818 if (prot_ver != PROTOCOL_VERSION) {
819 printk("GDT-ISA: Illegal protocol version\n");
820 iounmap(ha->brd);
821 return 0;
822 }
823
824 ha->oem_id = OEM_ID_ICP;
825 ha->type = GDT_ISA;
826 ha->ic_all_size = sizeof(dp2_ptr->u);
827 ha->stype= GDT2_ID;
828 ha->brd_phys = bios_adr >> 4;
829
830 /* special request to controller BIOS */
831 writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
832 writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
833 writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
834 writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
835 writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
836 writeb(0, &dp2_ptr->io.event);
837 retries = INIT_RETRIES;
838 gdth_delay(20);
839 while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
840 if (--retries == 0) {
841 printk("GDT-ISA: Initialization error\n");
842 iounmap(ha->brd);
843 return 0;
844 }
845 gdth_delay(1);
846 }
847 writeb(0, &dp2_ptr->u.ic.Status);
848 writeb(0xff, &dp2_ptr->io.irqdel);
849
850 ha->dma64_support = 0;
851 return 1;
852 }
853 #endif /* CONFIG_ISA */
854
855 #ifdef CONFIG_PCI
856 static int __devinit gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
857 gdth_ha_str *ha)
858 {
859 register gdt6_dpram_str __iomem *dp6_ptr;
860 register gdt6c_dpram_str __iomem *dp6c_ptr;
861 register gdt6m_dpram_str __iomem *dp6m_ptr;
862 ulong32 retries;
863 unchar prot_ver;
864 ushort command;
865 int i, found = FALSE;
866
867 TRACE(("gdth_init_pci()\n"));
868
869 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
870 ha->oem_id = OEM_ID_INTEL;
871 else
872 ha->oem_id = OEM_ID_ICP;
873 ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
874 ha->stype = (ulong32)pdev->device;
875 ha->irq = pdev->irq;
876 ha->pdev = pdev;
877
878 if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
879 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
880 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
881 if (ha->brd == NULL) {
882 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
883 return 0;
884 }
885 /* check and reset interface area */
886 dp6_ptr = ha->brd;
887 writel(DPMEM_MAGIC, &dp6_ptr->u);
888 if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
889 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
890 pcistr->dpmem);
891 found = FALSE;
892 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
893 iounmap(ha->brd);
894 ha->brd = ioremap(i, sizeof(ushort));
895 if (ha->brd == NULL) {
896 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
897 return 0;
898 }
899 if (readw(ha->brd) != 0xffff) {
900 TRACE2(("init_pci_old() address 0x%x busy\n", i));
901 continue;
902 }
903 iounmap(ha->brd);
904 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
905 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
906 if (ha->brd == NULL) {
907 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
908 return 0;
909 }
910 dp6_ptr = ha->brd;
911 writel(DPMEM_MAGIC, &dp6_ptr->u);
912 if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
913 printk("GDT-PCI: Use free address at 0x%x\n", i);
914 found = TRUE;
915 break;
916 }
917 }
918 if (!found) {
919 printk("GDT-PCI: No free address found!\n");
920 iounmap(ha->brd);
921 return 0;
922 }
923 }
924 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
925 if (readl(&dp6_ptr->u) != 0) {
926 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
927 iounmap(ha->brd);
928 return 0;
929 }
930
931 /* disable board interrupts, deinit services */
932 writeb(0xff, &dp6_ptr->io.irqdel);
933 writeb(0x00, &dp6_ptr->io.irqen);
934 writeb(0x00, &dp6_ptr->u.ic.S_Status);
935 writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
936
937 writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
938 writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
939 writeb(0, &dp6_ptr->io.event);
940 retries = INIT_RETRIES;
941 gdth_delay(20);
942 while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
943 if (--retries == 0) {
944 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
945 iounmap(ha->brd);
946 return 0;
947 }
948 gdth_delay(1);
949 }
950 prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
951 writeb(0, &dp6_ptr->u.ic.S_Status);
952 writeb(0xff, &dp6_ptr->io.irqdel);
953 if (prot_ver != PROTOCOL_VERSION) {
954 printk("GDT-PCI: Illegal protocol version\n");
955 iounmap(ha->brd);
956 return 0;
957 }
958
959 ha->type = GDT_PCI;
960 ha->ic_all_size = sizeof(dp6_ptr->u);
961
962 /* special command to controller BIOS */
963 writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
964 writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
965 writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
966 writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
967 writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
968 writeb(0, &dp6_ptr->io.event);
969 retries = INIT_RETRIES;
970 gdth_delay(20);
971 while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
972 if (--retries == 0) {
973 printk("GDT-PCI: Initialization error\n");
974 iounmap(ha->brd);
975 return 0;
976 }
977 gdth_delay(1);
978 }
979 writeb(0, &dp6_ptr->u.ic.S_Status);
980 writeb(0xff, &dp6_ptr->io.irqdel);
981
982 ha->dma64_support = 0;
983
984 } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
985 ha->plx = (gdt6c_plx_regs *)pcistr->io;
986 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
987 pcistr->dpmem,ha->irq));
988 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
989 if (ha->brd == NULL) {
990 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
991 iounmap(ha->brd);
992 return 0;
993 }
994 /* check and reset interface area */
995 dp6c_ptr = ha->brd;
996 writel(DPMEM_MAGIC, &dp6c_ptr->u);
997 if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
998 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
999 pcistr->dpmem);
1000 found = FALSE;
1001 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1002 iounmap(ha->brd);
1003 ha->brd = ioremap(i, sizeof(ushort));
1004 if (ha->brd == NULL) {
1005 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1006 return 0;
1007 }
1008 if (readw(ha->brd) != 0xffff) {
1009 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1010 continue;
1011 }
1012 iounmap(ha->brd);
1013 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
1014 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1015 if (ha->brd == NULL) {
1016 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1017 return 0;
1018 }
1019 dp6c_ptr = ha->brd;
1020 writel(DPMEM_MAGIC, &dp6c_ptr->u);
1021 if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1022 printk("GDT-PCI: Use free address at 0x%x\n", i);
1023 found = TRUE;
1024 break;
1025 }
1026 }
1027 if (!found) {
1028 printk("GDT-PCI: No free address found!\n");
1029 iounmap(ha->brd);
1030 return 0;
1031 }
1032 }
1033 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1034 if (readl(&dp6c_ptr->u) != 0) {
1035 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1036 iounmap(ha->brd);
1037 return 0;
1038 }
1039
1040 /* disable board interrupts, deinit services */
1041 outb(0x00,PTR2USHORT(&ha->plx->control1));
1042 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1043
1044 writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1045 writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1046
1047 writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1048 writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1049
1050 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1051
1052 retries = INIT_RETRIES;
1053 gdth_delay(20);
1054 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1055 if (--retries == 0) {
1056 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1057 iounmap(ha->brd);
1058 return 0;
1059 }
1060 gdth_delay(1);
1061 }
1062 prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
1063 writeb(0, &dp6c_ptr->u.ic.Status);
1064 if (prot_ver != PROTOCOL_VERSION) {
1065 printk("GDT-PCI: Illegal protocol version\n");
1066 iounmap(ha->brd);
1067 return 0;
1068 }
1069
1070 ha->type = GDT_PCINEW;
1071 ha->ic_all_size = sizeof(dp6c_ptr->u);
1072
1073 /* special command to controller BIOS */
1074 writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1075 writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1076 writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1077 writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1078 writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1079
1080 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1081
1082 retries = INIT_RETRIES;
1083 gdth_delay(20);
1084 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1085 if (--retries == 0) {
1086 printk("GDT-PCI: Initialization error\n");
1087 iounmap(ha->brd);
1088 return 0;
1089 }
1090 gdth_delay(1);
1091 }
1092 writeb(0, &dp6c_ptr->u.ic.S_Status);
1093
1094 ha->dma64_support = 0;
1095
1096 } else { /* MPR */
1097 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1098 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1099 if (ha->brd == NULL) {
1100 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1101 return 0;
1102 }
1103
1104 /* manipulate config. space to enable DPMEM, start RP controller */
1105 pci_read_config_word(pdev, PCI_COMMAND, &command);
1106 command |= 6;
1107 pci_write_config_word(pdev, PCI_COMMAND, command);
1108 if (pci_resource_start(pdev, 8) == 1UL)
1109 pci_resource_start(pdev, 8) = 0UL;
1110 i = 0xFEFF0001UL;
1111 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, i);
1112 gdth_delay(1);
1113 pci_write_config_dword(pdev, PCI_ROM_ADDRESS,
1114 pci_resource_start(pdev, 8));
1115
1116 dp6m_ptr = ha->brd;
1117
1118 /* Ensure that it is safe to access the non HW portions of DPMEM.
1119 * Aditional check needed for Xscale based RAID controllers */
1120 while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1121 gdth_delay(1);
1122
1123 /* check and reset interface area */
1124 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1125 if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1126 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1127 pcistr->dpmem);
1128 found = FALSE;
1129 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1130 iounmap(ha->brd);
1131 ha->brd = ioremap(i, sizeof(ushort));
1132 if (ha->brd == NULL) {
1133 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1134 return 0;
1135 }
1136 if (readw(ha->brd) != 0xffff) {
1137 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1138 continue;
1139 }
1140 iounmap(ha->brd);
1141 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
1142 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1143 if (ha->brd == NULL) {
1144 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1145 return 0;
1146 }
1147 dp6m_ptr = ha->brd;
1148 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1149 if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1150 printk("GDT-PCI: Use free address at 0x%x\n", i);
1151 found = TRUE;
1152 break;
1153 }
1154 }
1155 if (!found) {
1156 printk("GDT-PCI: No free address found!\n");
1157 iounmap(ha->brd);
1158 return 0;
1159 }
1160 }
1161 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1162
1163 /* disable board interrupts, deinit services */
1164 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1165 &dp6m_ptr->i960r.edoor_en_reg);
1166 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1167 writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1168 writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1169
1170 writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1171 writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1172 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1173 retries = INIT_RETRIES;
1174 gdth_delay(20);
1175 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1176 if (--retries == 0) {
1177 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1178 iounmap(ha->brd);
1179 return 0;
1180 }
1181 gdth_delay(1);
1182 }
1183 prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
1184 writeb(0, &dp6m_ptr->u.ic.S_Status);
1185 if (prot_ver != PROTOCOL_VERSION) {
1186 printk("GDT-PCI: Illegal protocol version\n");
1187 iounmap(ha->brd);
1188 return 0;
1189 }
1190
1191 ha->type = GDT_PCIMPR;
1192 ha->ic_all_size = sizeof(dp6m_ptr->u);
1193
1194 /* special command to controller BIOS */
1195 writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1196 writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1197 writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1198 writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1199 writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1200 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1201 retries = INIT_RETRIES;
1202 gdth_delay(20);
1203 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1204 if (--retries == 0) {
1205 printk("GDT-PCI: Initialization error\n");
1206 iounmap(ha->brd);
1207 return 0;
1208 }
1209 gdth_delay(1);
1210 }
1211 writeb(0, &dp6m_ptr->u.ic.S_Status);
1212
1213 /* read FW version to detect 64-bit DMA support */
1214 writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1215 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1216 retries = INIT_RETRIES;
1217 gdth_delay(20);
1218 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1219 if (--retries == 0) {
1220 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1221 iounmap(ha->brd);
1222 return 0;
1223 }
1224 gdth_delay(1);
1225 }
1226 prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1227 writeb(0, &dp6m_ptr->u.ic.S_Status);
1228 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1229 ha->dma64_support = 0;
1230 else
1231 ha->dma64_support = 1;
1232 }
1233
1234 return 1;
1235 }
1236 #endif /* CONFIG_PCI */
1237
1238 /* controller protocol functions */
1239
1240 static void __devinit gdth_enable_int(gdth_ha_str *ha)
1241 {
1242 ulong flags;
1243 gdt2_dpram_str __iomem *dp2_ptr;
1244 gdt6_dpram_str __iomem *dp6_ptr;
1245 gdt6m_dpram_str __iomem *dp6m_ptr;
1246
1247 TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
1248 spin_lock_irqsave(&ha->smp_lock, flags);
1249
1250 if (ha->type == GDT_EISA) {
1251 outb(0xff, ha->bmic + EDOORREG);
1252 outb(0xff, ha->bmic + EDENABREG);
1253 outb(0x01, ha->bmic + EINTENABREG);
1254 } else if (ha->type == GDT_ISA) {
1255 dp2_ptr = ha->brd;
1256 writeb(1, &dp2_ptr->io.irqdel);
1257 writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1258 writeb(1, &dp2_ptr->io.irqen);
1259 } else if (ha->type == GDT_PCI) {
1260 dp6_ptr = ha->brd;
1261 writeb(1, &dp6_ptr->io.irqdel);
1262 writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1263 writeb(1, &dp6_ptr->io.irqen);
1264 } else if (ha->type == GDT_PCINEW) {
1265 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1266 outb(0x03, PTR2USHORT(&ha->plx->control1));
1267 } else if (ha->type == GDT_PCIMPR) {
1268 dp6m_ptr = ha->brd;
1269 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1270 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1271 &dp6m_ptr->i960r.edoor_en_reg);
1272 }
1273 spin_unlock_irqrestore(&ha->smp_lock, flags);
1274 }
1275
1276 /* return IStatus if interrupt was from this card else 0 */
1277 static unchar gdth_get_status(gdth_ha_str *ha)
1278 {
1279 unchar IStatus = 0;
1280
1281 TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
1282
1283 if (ha->type == GDT_EISA)
1284 IStatus = inb((ushort)ha->bmic + EDOORREG);
1285 else if (ha->type == GDT_ISA)
1286 IStatus =
1287 readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1288 else if (ha->type == GDT_PCI)
1289 IStatus =
1290 readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1291 else if (ha->type == GDT_PCINEW)
1292 IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1293 else if (ha->type == GDT_PCIMPR)
1294 IStatus =
1295 readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1296
1297 return IStatus;
1298 }
1299
1300 static int gdth_test_busy(gdth_ha_str *ha)
1301 {
1302 register int gdtsema0 = 0;
1303
1304 TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
1305
1306 if (ha->type == GDT_EISA)
1307 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1308 else if (ha->type == GDT_ISA)
1309 gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1310 else if (ha->type == GDT_PCI)
1311 gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1312 else if (ha->type == GDT_PCINEW)
1313 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1314 else if (ha->type == GDT_PCIMPR)
1315 gdtsema0 =
1316 (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1317
1318 return (gdtsema0 & 1);
1319 }
1320
1321
1322 static int gdth_get_cmd_index(gdth_ha_str *ha)
1323 {
1324 int i;
1325
1326 TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
1327
1328 for (i=0; i<GDTH_MAXCMDS; ++i) {
1329 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1330 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1331 ha->cmd_tab[i].service = ha->pccb->Service;
1332 ha->pccb->CommandIndex = (ulong32)i+2;
1333 return (i+2);
1334 }
1335 }
1336 return 0;
1337 }
1338
1339
1340 static void gdth_set_sema0(gdth_ha_str *ha)
1341 {
1342 TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
1343
1344 if (ha->type == GDT_EISA) {
1345 outb(1, ha->bmic + SEMA0REG);
1346 } else if (ha->type == GDT_ISA) {
1347 writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1348 } else if (ha->type == GDT_PCI) {
1349 writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1350 } else if (ha->type == GDT_PCINEW) {
1351 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1352 } else if (ha->type == GDT_PCIMPR) {
1353 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1354 }
1355 }
1356
1357
1358 static void gdth_copy_command(gdth_ha_str *ha)
1359 {
1360 register gdth_cmd_str *cmd_ptr;
1361 register gdt6m_dpram_str __iomem *dp6m_ptr;
1362 register gdt6c_dpram_str __iomem *dp6c_ptr;
1363 gdt6_dpram_str __iomem *dp6_ptr;
1364 gdt2_dpram_str __iomem *dp2_ptr;
1365 ushort cp_count,dp_offset,cmd_no;
1366
1367 TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
1368
1369 cp_count = ha->cmd_len;
1370 dp_offset= ha->cmd_offs_dpmem;
1371 cmd_no = ha->cmd_cnt;
1372 cmd_ptr = ha->pccb;
1373
1374 ++ha->cmd_cnt;
1375 if (ha->type == GDT_EISA)
1376 return; /* no DPMEM, no copy */
1377
1378 /* set cpcount dword aligned */
1379 if (cp_count & 3)
1380 cp_count += (4 - (cp_count & 3));
1381
1382 ha->cmd_offs_dpmem += cp_count;
1383
1384 /* set offset and service, copy command to DPMEM */
1385 if (ha->type == GDT_ISA) {
1386 dp2_ptr = ha->brd;
1387 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1388 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1389 writew((ushort)cmd_ptr->Service,
1390 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1391 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1392 } else if (ha->type == GDT_PCI) {
1393 dp6_ptr = ha->brd;
1394 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1395 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1396 writew((ushort)cmd_ptr->Service,
1397 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1398 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1399 } else if (ha->type == GDT_PCINEW) {
1400 dp6c_ptr = ha->brd;
1401 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1402 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1403 writew((ushort)cmd_ptr->Service,
1404 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1405 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1406 } else if (ha->type == GDT_PCIMPR) {
1407 dp6m_ptr = ha->brd;
1408 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1409 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1410 writew((ushort)cmd_ptr->Service,
1411 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1412 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1413 }
1414 }
1415
1416
1417 static void gdth_release_event(gdth_ha_str *ha)
1418 {
1419 TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
1420
1421 #ifdef GDTH_STATISTICS
1422 {
1423 ulong32 i,j;
1424 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1425 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1426 ++i;
1427 }
1428 if (max_index < i) {
1429 max_index = i;
1430 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1431 }
1432 }
1433 #endif
1434
1435 if (ha->pccb->OpCode == GDT_INIT)
1436 ha->pccb->Service |= 0x80;
1437
1438 if (ha->type == GDT_EISA) {
1439 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1440 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1441 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1442 } else if (ha->type == GDT_ISA) {
1443 writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1444 } else if (ha->type == GDT_PCI) {
1445 writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1446 } else if (ha->type == GDT_PCINEW) {
1447 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1448 } else if (ha->type == GDT_PCIMPR) {
1449 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1450 }
1451 }
1452
1453 static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
1454 {
1455 int answer_found = FALSE;
1456 int wait_index = 0;
1457
1458 TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
1459
1460 if (index == 0)
1461 return 1; /* no wait required */
1462
1463 do {
1464 __gdth_interrupt(ha, true, &wait_index);
1465 if (wait_index == index) {
1466 answer_found = TRUE;
1467 break;
1468 }
1469 gdth_delay(1);
1470 } while (--time);
1471
1472 while (gdth_test_busy(ha))
1473 gdth_delay(0);
1474
1475 return (answer_found);
1476 }
1477
1478
1479 static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
1480 ulong32 p1, ulong64 p2, ulong64 p3)
1481 {
1482 register gdth_cmd_str *cmd_ptr;
1483 int retries,index;
1484
1485 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1486
1487 cmd_ptr = ha->pccb;
1488 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1489
1490 /* make command */
1491 for (retries = INIT_RETRIES;;) {
1492 cmd_ptr->Service = service;
1493 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1494 if (!(index=gdth_get_cmd_index(ha))) {
1495 TRACE(("GDT: No free command index found\n"));
1496 return 0;
1497 }
1498 gdth_set_sema0(ha);
1499 cmd_ptr->OpCode = opcode;
1500 cmd_ptr->BoardNode = LOCALBOARD;
1501 if (service == CACHESERVICE) {
1502 if (opcode == GDT_IOCTL) {
1503 cmd_ptr->u.ioctl.subfunc = p1;
1504 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1505 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1506 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1507 } else {
1508 if (ha->cache_feat & GDT_64BIT) {
1509 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1510 cmd_ptr->u.cache64.BlockNo = p2;
1511 } else {
1512 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1513 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1514 }
1515 }
1516 } else if (service == SCSIRAWSERVICE) {
1517 if (ha->raw_feat & GDT_64BIT) {
1518 cmd_ptr->u.raw64.direction = p1;
1519 cmd_ptr->u.raw64.bus = (unchar)p2;
1520 cmd_ptr->u.raw64.target = (unchar)p3;
1521 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1522 } else {
1523 cmd_ptr->u.raw.direction = p1;
1524 cmd_ptr->u.raw.bus = (unchar)p2;
1525 cmd_ptr->u.raw.target = (unchar)p3;
1526 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1527 }
1528 } else if (service == SCREENSERVICE) {
1529 if (opcode == GDT_REALTIME) {
1530 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1531 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1532 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1533 }
1534 }
1535 ha->cmd_len = sizeof(gdth_cmd_str);
1536 ha->cmd_offs_dpmem = 0;
1537 ha->cmd_cnt = 0;
1538 gdth_copy_command(ha);
1539 gdth_release_event(ha);
1540 gdth_delay(20);
1541 if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
1542 printk("GDT: Initialization error (timeout service %d)\n",service);
1543 return 0;
1544 }
1545 if (ha->status != S_BSY || --retries == 0)
1546 break;
1547 gdth_delay(1);
1548 }
1549
1550 return (ha->status != S_OK ? 0:1);
1551 }
1552
1553
1554 /* search for devices */
1555
1556 static int __devinit gdth_search_drives(gdth_ha_str *ha)
1557 {
1558 ushort cdev_cnt, i;
1559 int ok;
1560 ulong32 bus_no, drv_cnt, drv_no, j;
1561 gdth_getch_str *chn;
1562 gdth_drlist_str *drl;
1563 gdth_iochan_str *ioc;
1564 gdth_raw_iochan_str *iocr;
1565 gdth_arcdl_str *alst;
1566 gdth_alist_str *alst2;
1567 gdth_oem_str_ioctl *oemstr;
1568 #ifdef INT_COAL
1569 gdth_perf_modes *pmod;
1570 #endif
1571
1572 #ifdef GDTH_RTC
1573 unchar rtc[12];
1574 ulong flags;
1575 #endif
1576
1577 TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
1578 ok = 0;
1579
1580 /* initialize controller services, at first: screen service */
1581 ha->screen_feat = 0;
1582 if (!force_dma32) {
1583 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
1584 if (ok)
1585 ha->screen_feat = GDT_64BIT;
1586 }
1587 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1588 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
1589 if (!ok) {
1590 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1591 ha->hanum, ha->status);
1592 return 0;
1593 }
1594 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1595
1596 #ifdef GDTH_RTC
1597 /* read realtime clock info, send to controller */
1598 /* 1. wait for the falling edge of update flag */
1599 spin_lock_irqsave(&rtc_lock, flags);
1600 for (j = 0; j < 1000000; ++j)
1601 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1602 break;
1603 for (j = 0; j < 1000000; ++j)
1604 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1605 break;
1606 /* 2. read info */
1607 do {
1608 for (j = 0; j < 12; ++j)
1609 rtc[j] = CMOS_READ(j);
1610 } while (rtc[0] != CMOS_READ(0));
1611 spin_unlock_irqrestore(&rtc_lock, flags);
1612 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1613 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1614 /* 3. send to controller firmware */
1615 gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
1616 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1617 #endif
1618
1619 /* unfreeze all IOs */
1620 gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
1621
1622 /* initialize cache service */
1623 ha->cache_feat = 0;
1624 if (!force_dma32) {
1625 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
1626 0, 0);
1627 if (ok)
1628 ha->cache_feat = GDT_64BIT;
1629 }
1630 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1631 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
1632 if (!ok) {
1633 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1634 ha->hanum, ha->status);
1635 return 0;
1636 }
1637 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1638 cdev_cnt = (ushort)ha->info;
1639 ha->fw_vers = ha->service;
1640
1641 #ifdef INT_COAL
1642 if (ha->type == GDT_PCIMPR) {
1643 /* set perf. modes */
1644 pmod = (gdth_perf_modes *)ha->pscratch;
1645 pmod->version = 1;
1646 pmod->st_mode = 1; /* enable one status buffer */
1647 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1648 pmod->st_buff_indx1 = COALINDEX;
1649 pmod->st_buff_addr2 = 0;
1650 pmod->st_buff_u_addr2 = 0;
1651 pmod->st_buff_indx2 = 0;
1652 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1653 pmod->cmd_mode = 0; // disable all cmd buffers
1654 pmod->cmd_buff_addr1 = 0;
1655 pmod->cmd_buff_u_addr1 = 0;
1656 pmod->cmd_buff_indx1 = 0;
1657 pmod->cmd_buff_addr2 = 0;
1658 pmod->cmd_buff_u_addr2 = 0;
1659 pmod->cmd_buff_indx2 = 0;
1660 pmod->cmd_buff_size = 0;
1661 pmod->reserved1 = 0;
1662 pmod->reserved2 = 0;
1663 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
1664 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
1665 printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
1666 }
1667 }
1668 #endif
1669
1670 /* detect number of buses - try new IOCTL */
1671 iocr = (gdth_raw_iochan_str *)ha->pscratch;
1672 iocr->hdr.version = 0xffffffff;
1673 iocr->hdr.list_entries = MAXBUS;
1674 iocr->hdr.first_chan = 0;
1675 iocr->hdr.last_chan = MAXBUS-1;
1676 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
1677 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
1678 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
1679 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
1680 ha->bus_cnt = iocr->hdr.chan_count;
1681 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1682 if (iocr->list[bus_no].proc_id < MAXID)
1683 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
1684 else
1685 ha->bus_id[bus_no] = 0xff;
1686 }
1687 } else {
1688 /* old method */
1689 chn = (gdth_getch_str *)ha->pscratch;
1690 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
1691 chn->channel_no = bus_no;
1692 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1693 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1694 IO_CHANNEL | INVALID_CHANNEL,
1695 sizeof(gdth_getch_str))) {
1696 if (bus_no == 0) {
1697 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
1698 ha->hanum, ha->status);
1699 return 0;
1700 }
1701 break;
1702 }
1703 if (chn->siop_id < MAXID)
1704 ha->bus_id[bus_no] = chn->siop_id;
1705 else
1706 ha->bus_id[bus_no] = 0xff;
1707 }
1708 ha->bus_cnt = (unchar)bus_no;
1709 }
1710 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
1711
1712 /* read cache configuration */
1713 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
1714 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
1715 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1716 ha->hanum, ha->status);
1717 return 0;
1718 }
1719 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
1720 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
1721 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
1722 ha->cpar.write_back,ha->cpar.block_size));
1723
1724 /* read board info and features */
1725 ha->more_proc = FALSE;
1726 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
1727 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
1728 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
1729 sizeof(gdth_binfo_str));
1730 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
1731 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
1732 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
1733 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
1734 ha->more_proc = TRUE;
1735 }
1736 } else {
1737 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
1738 strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
1739 }
1740 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
1741
1742 /* read more informations */
1743 if (ha->more_proc) {
1744 /* physical drives, channel addresses */
1745 ioc = (gdth_iochan_str *)ha->pscratch;
1746 ioc->hdr.version = 0xffffffff;
1747 ioc->hdr.list_entries = MAXBUS;
1748 ioc->hdr.first_chan = 0;
1749 ioc->hdr.last_chan = MAXBUS-1;
1750 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
1751 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
1752 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
1753 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1754 ha->raw[bus_no].address = ioc->list[bus_no].address;
1755 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
1756 }
1757 } else {
1758 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1759 ha->raw[bus_no].address = IO_CHANNEL;
1760 ha->raw[bus_no].local_no = bus_no;
1761 }
1762 }
1763 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1764 chn = (gdth_getch_str *)ha->pscratch;
1765 chn->channel_no = ha->raw[bus_no].local_no;
1766 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1767 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1768 ha->raw[bus_no].address | INVALID_CHANNEL,
1769 sizeof(gdth_getch_str))) {
1770 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
1771 TRACE2(("Channel %d: %d phys. drives\n",
1772 bus_no,chn->drive_cnt));
1773 }
1774 if (ha->raw[bus_no].pdev_cnt > 0) {
1775 drl = (gdth_drlist_str *)ha->pscratch;
1776 drl->sc_no = ha->raw[bus_no].local_no;
1777 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
1778 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1779 SCSI_DR_LIST | L_CTRL_PATTERN,
1780 ha->raw[bus_no].address | INVALID_CHANNEL,
1781 sizeof(gdth_drlist_str))) {
1782 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
1783 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
1784 } else {
1785 ha->raw[bus_no].pdev_cnt = 0;
1786 }
1787 }
1788 }
1789
1790 /* logical drives */
1791 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
1792 INVALID_CHANNEL,sizeof(ulong32))) {
1793 drv_cnt = *(ulong32 *)ha->pscratch;
1794 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
1795 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
1796 for (j = 0; j < drv_cnt; ++j) {
1797 drv_no = ((ulong32 *)ha->pscratch)[j];
1798 if (drv_no < MAX_LDRIVES) {
1799 ha->hdr[drv_no].is_logdrv = TRUE;
1800 TRACE2(("Drive %d is log. drive\n",drv_no));
1801 }
1802 }
1803 }
1804 alst = (gdth_arcdl_str *)ha->pscratch;
1805 alst->entries_avail = MAX_LDRIVES;
1806 alst->first_entry = 0;
1807 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
1808 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1809 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
1810 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
1811 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
1812 for (j = 0; j < alst->entries_init; ++j) {
1813 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
1814 ha->hdr[j].is_master = alst->list[j].is_master;
1815 ha->hdr[j].is_parity = alst->list[j].is_parity;
1816 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
1817 ha->hdr[j].master_no = alst->list[j].cd_handle;
1818 }
1819 } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1820 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
1821 0, 35 * sizeof(gdth_alist_str))) {
1822 for (j = 0; j < 35; ++j) {
1823 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
1824 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
1825 ha->hdr[j].is_master = alst2->is_master;
1826 ha->hdr[j].is_parity = alst2->is_parity;
1827 ha->hdr[j].is_hotfix = alst2->is_hotfix;
1828 ha->hdr[j].master_no = alst2->cd_handle;
1829 }
1830 }
1831 }
1832 }
1833
1834 /* initialize raw service */
1835 ha->raw_feat = 0;
1836 if (!force_dma32) {
1837 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
1838 if (ok)
1839 ha->raw_feat = GDT_64BIT;
1840 }
1841 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1842 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
1843 if (!ok) {
1844 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
1845 ha->hanum, ha->status);
1846 return 0;
1847 }
1848 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
1849
1850 /* set/get features raw service (scatter/gather) */
1851 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
1852 0, 0)) {
1853 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
1854 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1855 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
1856 ha->info));
1857 ha->raw_feat |= (ushort)ha->info;
1858 }
1859 }
1860
1861 /* set/get features cache service (equal to raw service) */
1862 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
1863 SCATTER_GATHER,0)) {
1864 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
1865 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1866 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
1867 ha->info));
1868 ha->cache_feat |= (ushort)ha->info;
1869 }
1870 }
1871
1872 /* reserve drives for raw service */
1873 if (reserve_mode != 0) {
1874 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
1875 reserve_mode == 1 ? 1 : 3, 0, 0);
1876 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
1877 ha->status));
1878 }
1879 for (i = 0; i < MAX_RES_ARGS; i += 4) {
1880 if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
1881 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
1882 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
1883 reserve_list[i], reserve_list[i+1],
1884 reserve_list[i+2], reserve_list[i+3]));
1885 if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
1886 reserve_list[i+1], reserve_list[i+2] |
1887 (reserve_list[i+3] << 8))) {
1888 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
1889 ha->hanum, ha->status);
1890 }
1891 }
1892 }
1893
1894 /* Determine OEM string using IOCTL */
1895 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
1896 oemstr->params.ctl_version = 0x01;
1897 oemstr->params.buffer_size = sizeof(oemstr->text);
1898 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1899 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
1900 sizeof(gdth_oem_str_ioctl))) {
1901 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
1902 printk("GDT-HA %d: Vendor: %s Name: %s\n",
1903 ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
1904 /* Save the Host Drive inquiry data */
1905 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
1906 sizeof(ha->oem_name));
1907 } else {
1908 /* Old method, based on PCI ID */
1909 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
1910 printk("GDT-HA %d: Name: %s\n",
1911 ha->hanum, ha->binfo.type_string);
1912 if (ha->oem_id == OEM_ID_INTEL)
1913 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
1914 else
1915 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
1916 }
1917
1918 /* scanning for host drives */
1919 for (i = 0; i < cdev_cnt; ++i)
1920 gdth_analyse_hdrive(ha, i);
1921
1922 TRACE(("gdth_search_drives() OK\n"));
1923 return 1;
1924 }
1925
1926 static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
1927 {
1928 ulong32 drv_cyls;
1929 int drv_hds, drv_secs;
1930
1931 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
1932 if (hdrive >= MAX_HDRIVES)
1933 return 0;
1934
1935 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
1936 return 0;
1937 ha->hdr[hdrive].present = TRUE;
1938 ha->hdr[hdrive].size = ha->info;
1939
1940 /* evaluate mapping (sectors per head, heads per cylinder) */
1941 ha->hdr[hdrive].size &= ~SECS32;
1942 if (ha->info2 == 0) {
1943 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
1944 } else {
1945 drv_hds = ha->info2 & 0xff;
1946 drv_secs = (ha->info2 >> 8) & 0xff;
1947 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
1948 }
1949 ha->hdr[hdrive].heads = (unchar)drv_hds;
1950 ha->hdr[hdrive].secs = (unchar)drv_secs;
1951 /* round size */
1952 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
1953
1954 if (ha->cache_feat & GDT_64BIT) {
1955 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
1956 && ha->info2 != 0) {
1957 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
1958 }
1959 }
1960 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
1961 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
1962
1963 /* get informations about device */
1964 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
1965 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
1966 hdrive,ha->info));
1967 ha->hdr[hdrive].devtype = (ushort)ha->info;
1968 }
1969
1970 /* cluster info */
1971 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
1972 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
1973 hdrive,ha->info));
1974 if (!shared_access)
1975 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
1976 }
1977
1978 /* R/W attributes */
1979 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
1980 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
1981 hdrive,ha->info));
1982 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
1983 }
1984
1985 return 1;
1986 }
1987
1988
1989 /* command queueing/sending functions */
1990
1991 static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
1992 {
1993 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
1994 register Scsi_Cmnd *pscp;
1995 register Scsi_Cmnd *nscp;
1996 ulong flags;
1997
1998 TRACE(("gdth_putq() priority %d\n",priority));
1999 spin_lock_irqsave(&ha->smp_lock, flags);
2000
2001 if (!cmndinfo->internal_command)
2002 cmndinfo->priority = priority;
2003
2004 if (ha->req_first==NULL) {
2005 ha->req_first = scp; /* queue was empty */
2006 scp->SCp.ptr = NULL;
2007 } else { /* queue not empty */
2008 pscp = ha->req_first;
2009 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2010 /* priority: 0-highest,..,0xff-lowest */
2011 while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
2012 pscp = nscp;
2013 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2014 }
2015 pscp->SCp.ptr = (char *)scp;
2016 scp->SCp.ptr = (char *)nscp;
2017 }
2018 spin_unlock_irqrestore(&ha->smp_lock, flags);
2019
2020 #ifdef GDTH_STATISTICS
2021 flags = 0;
2022 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2023 ++flags;
2024 if (max_rq < flags) {
2025 max_rq = flags;
2026 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2027 }
2028 #endif
2029 }
2030
2031 static void gdth_next(gdth_ha_str *ha)
2032 {
2033 register Scsi_Cmnd *pscp;
2034 register Scsi_Cmnd *nscp;
2035 unchar b, t, l, firsttime;
2036 unchar this_cmd, next_cmd;
2037 ulong flags = 0;
2038 int cmd_index;
2039
2040 TRACE(("gdth_next() hanum %d\n", ha->hanum));
2041 if (!gdth_polling)
2042 spin_lock_irqsave(&ha->smp_lock, flags);
2043
2044 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2045 this_cmd = firsttime = TRUE;
2046 next_cmd = gdth_polling ? FALSE:TRUE;
2047 cmd_index = 0;
2048
2049 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2050 struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
2051 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2052 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2053 if (!nscp_cmndinfo->internal_command) {
2054 b = nscp->device->channel;
2055 t = nscp->device->id;
2056 l = nscp->device->lun;
2057 if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
2058 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2059 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2060 continue;
2061 }
2062 } else
2063 b = t = l = 0;
2064
2065 if (firsttime) {
2066 if (gdth_test_busy(ha)) { /* controller busy ? */
2067 TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
2068 if (!gdth_polling) {
2069 spin_unlock_irqrestore(&ha->smp_lock, flags);
2070 return;
2071 }
2072 while (gdth_test_busy(ha))
2073 gdth_delay(1);
2074 }
2075 firsttime = FALSE;
2076 }
2077
2078 if (!nscp_cmndinfo->internal_command) {
2079 if (nscp_cmndinfo->phase == -1) {
2080 nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
2081 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2082 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2083 b, t, l));
2084 /* TEST_UNIT_READY -> set scan mode */
2085 if ((ha->scan_mode & 0x0f) == 0) {
2086 if (b == 0 && t == 0 && l == 0) {
2087 ha->scan_mode |= 1;
2088 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2089 }
2090 } else if ((ha->scan_mode & 0x0f) == 1) {
2091 if (b == 0 && ((t == 0 && l == 1) ||
2092 (t == 1 && l == 0))) {
2093 nscp_cmndinfo->OpCode = GDT_SCAN_START;
2094 nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2095 | SCSIRAWSERVICE;
2096 ha->scan_mode = 0x12;
2097 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2098 ha->scan_mode));
2099 } else {
2100 ha->scan_mode &= 0x10;
2101 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2102 }
2103 } else if (ha->scan_mode == 0x12) {
2104 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2105 nscp_cmndinfo->phase = SCSIRAWSERVICE;
2106 nscp_cmndinfo->OpCode = GDT_SCAN_END;
2107 ha->scan_mode &= 0x10;
2108 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2109 ha->scan_mode));
2110 }
2111 }
2112 }
2113 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2114 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2115 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2116 /* always GDT_CLUST_INFO! */
2117 nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
2118 }
2119 }
2120 }
2121
2122 if (nscp_cmndinfo->OpCode != -1) {
2123 if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
2124 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2125 this_cmd = FALSE;
2126 next_cmd = FALSE;
2127 } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
2128 if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
2129 this_cmd = FALSE;
2130 next_cmd = FALSE;
2131 } else {
2132 memset((char*)nscp->sense_buffer,0,16);
2133 nscp->sense_buffer[0] = 0x70;
2134 nscp->sense_buffer[2] = NOT_READY;
2135 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2136 if (!nscp_cmndinfo->wait_for_completion)
2137 nscp_cmndinfo->wait_for_completion++;
2138 else
2139 gdth_scsi_done(nscp);
2140 }
2141 } else if (gdth_cmnd_priv(nscp)->internal_command) {
2142 if (!(cmd_index=gdth_special_cmd(ha, nscp)))
2143 this_cmd = FALSE;
2144 next_cmd = FALSE;
2145 } else if (b != ha->virt_bus) {
2146 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2147 !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
2148 this_cmd = FALSE;
2149 else
2150 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2151 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2152 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2153 nscp->cmnd[0], b, t, l));
2154 nscp->result = DID_BAD_TARGET << 16;
2155 if (!nscp_cmndinfo->wait_for_completion)
2156 nscp_cmndinfo->wait_for_completion++;
2157 else
2158 gdth_scsi_done(nscp);
2159 } else {
2160 switch (nscp->cmnd[0]) {
2161 case TEST_UNIT_READY:
2162 case INQUIRY:
2163 case REQUEST_SENSE:
2164 case READ_CAPACITY:
2165 case VERIFY:
2166 case START_STOP:
2167 case MODE_SENSE:
2168 case SERVICE_ACTION_IN:
2169 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2170 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2171 nscp->cmnd[4],nscp->cmnd[5]));
2172 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2173 /* return UNIT_ATTENTION */
2174 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2175 nscp->cmnd[0], t));
2176 ha->hdr[t].media_changed = FALSE;
2177 memset((char*)nscp->sense_buffer,0,16);
2178 nscp->sense_buffer[0] = 0x70;
2179 nscp->sense_buffer[2] = UNIT_ATTENTION;
2180 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2181 if (!nscp_cmndinfo->wait_for_completion)
2182 nscp_cmndinfo->wait_for_completion++;
2183 else
2184 gdth_scsi_done(nscp);
2185 } else if (gdth_internal_cache_cmd(ha, nscp))
2186 gdth_scsi_done(nscp);
2187 break;
2188
2189 case ALLOW_MEDIUM_REMOVAL:
2190 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2191 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2192 nscp->cmnd[4],nscp->cmnd[5]));
2193 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2194 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2195 nscp->result = DID_OK << 16;
2196 nscp->sense_buffer[0] = 0;
2197 if (!nscp_cmndinfo->wait_for_completion)
2198 nscp_cmndinfo->wait_for_completion++;
2199 else
2200 gdth_scsi_done(nscp);
2201 } else {
2202 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2203 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2204 nscp->cmnd[4],nscp->cmnd[3]));
2205 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2206 this_cmd = FALSE;
2207 }
2208 break;
2209
2210 case RESERVE:
2211 case RELEASE:
2212 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2213 "RESERVE" : "RELEASE"));
2214 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2215 this_cmd = FALSE;
2216 break;
2217
2218 case READ_6:
2219 case WRITE_6:
2220 case READ_10:
2221 case WRITE_10:
2222 case READ_16:
2223 case WRITE_16:
2224 if (ha->hdr[t].media_changed) {
2225 /* return UNIT_ATTENTION */
2226 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2227 nscp->cmnd[0], t));
2228 ha->hdr[t].media_changed = FALSE;
2229 memset((char*)nscp->sense_buffer,0,16);
2230 nscp->sense_buffer[0] = 0x70;
2231 nscp->sense_buffer[2] = UNIT_ATTENTION;
2232 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2233 if (!nscp_cmndinfo->wait_for_completion)
2234 nscp_cmndinfo->wait_for_completion++;
2235 else
2236 gdth_scsi_done(nscp);
2237 } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2238 this_cmd = FALSE;
2239 break;
2240
2241 default:
2242 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2243 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2244 nscp->cmnd[4],nscp->cmnd[5]));
2245 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2246 ha->hanum, nscp->cmnd[0]);
2247 nscp->result = DID_ABORT << 16;
2248 if (!nscp_cmndinfo->wait_for_completion)
2249 nscp_cmndinfo->wait_for_completion++;
2250 else
2251 gdth_scsi_done(nscp);
2252 break;
2253 }
2254 }
2255
2256 if (!this_cmd)
2257 break;
2258 if (nscp == ha->req_first)
2259 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2260 else
2261 pscp->SCp.ptr = nscp->SCp.ptr;
2262 if (!next_cmd)
2263 break;
2264 }
2265
2266 if (ha->cmd_cnt > 0) {
2267 gdth_release_event(ha);
2268 }
2269
2270 if (!gdth_polling)
2271 spin_unlock_irqrestore(&ha->smp_lock, flags);
2272
2273 if (gdth_polling && ha->cmd_cnt > 0) {
2274 if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
2275 printk("GDT-HA %d: Command %d timed out !\n",
2276 ha->hanum, cmd_index);
2277 }
2278 }
2279
2280 /*
2281 * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
2282 * buffers, kmap_atomic() as needed.
2283 */
2284 static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
2285 char *buffer, ushort count)
2286 {
2287 ushort cpcount,i, max_sg = scsi_sg_count(scp);
2288 ushort cpsum,cpnow;
2289 struct scatterlist *sl;
2290 char *address;
2291
2292 cpcount = min_t(ushort, count, scsi_bufflen(scp));
2293
2294 if (cpcount) {
2295 cpsum=0;
2296 scsi_for_each_sg(scp, sl, max_sg, i) {
2297 unsigned long flags;
2298 cpnow = (ushort)sl->length;
2299 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2300 cpnow, cpsum, cpcount, scsi_bufflen(scp)));
2301 if (cpsum+cpnow > cpcount)
2302 cpnow = cpcount - cpsum;
2303 cpsum += cpnow;
2304 if (!sg_page(sl)) {
2305 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2306 ha->hanum);
2307 return;
2308 }
2309 local_irq_save(flags);
2310 address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
2311 memcpy(address, buffer, cpnow);
2312 flush_dcache_page(sg_page(sl));
2313 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2314 local_irq_restore(flags);
2315 if (cpsum == cpcount)
2316 break;
2317 buffer += cpnow;
2318 }
2319 } else if (count) {
2320 printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
2321 ha->hanum);
2322 WARN_ON(1);
2323 }
2324 }
2325
2326 static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
2327 {
2328 unchar t;
2329 gdth_inq_data inq;
2330 gdth_rdcap_data rdc;
2331 gdth_sense_data sd;
2332 gdth_modep_data mpd;
2333 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2334
2335 t = scp->device->id;
2336 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2337 scp->cmnd[0],t));
2338
2339 scp->result = DID_OK << 16;
2340 scp->sense_buffer[0] = 0;
2341
2342 switch (scp->cmnd[0]) {
2343 case TEST_UNIT_READY:
2344 case VERIFY:
2345 case START_STOP:
2346 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2347 break;
2348
2349 case INQUIRY:
2350 TRACE2(("Inquiry hdrive %d devtype %d\n",
2351 t,ha->hdr[t].devtype));
2352 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2353 /* you can here set all disks to removable, if you want to do
2354 a flush using the ALLOW_MEDIUM_REMOVAL command */
2355 inq.modif_rmb = 0x00;
2356 if ((ha->hdr[t].devtype & 1) ||
2357 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2358 inq.modif_rmb = 0x80;
2359 inq.version = 2;
2360 inq.resp_aenc = 2;
2361 inq.add_length= 32;
2362 strcpy(inq.vendor,ha->oem_name);
2363 sprintf(inq.product,"Host Drive #%02d",t);
2364 strcpy(inq.revision," ");
2365 gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
2366 break;
2367
2368 case REQUEST_SENSE:
2369 TRACE2(("Request sense hdrive %d\n",t));
2370 sd.errorcode = 0x70;
2371 sd.segno = 0x00;
2372 sd.key = NO_SENSE;
2373 sd.info = 0;
2374 sd.add_length= 0;
2375 gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
2376 break;
2377
2378 case MODE_SENSE:
2379 TRACE2(("Mode sense hdrive %d\n",t));
2380 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2381 mpd.hd.data_length = sizeof(gdth_modep_data);
2382 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2383 mpd.hd.bd_length = sizeof(mpd.bd);
2384 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2385 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2386 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2387 gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
2388 break;
2389
2390 case READ_CAPACITY:
2391 TRACE2(("Read capacity hdrive %d\n",t));
2392 if (ha->hdr[t].size > (ulong64)0xffffffff)
2393 rdc.last_block_no = 0xffffffff;
2394 else
2395 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2396 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2397 gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
2398 break;
2399
2400 case SERVICE_ACTION_IN:
2401 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2402 (ha->cache_feat & GDT_64BIT)) {
2403 gdth_rdcap16_data rdc16;
2404
2405 TRACE2(("Read capacity (16) hdrive %d\n",t));
2406 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2407 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2408 gdth_copy_internal_data(ha, scp, (char*)&rdc16,
2409 sizeof(gdth_rdcap16_data));
2410 } else {
2411 scp->result = DID_ABORT << 16;
2412 }
2413 break;
2414
2415 default:
2416 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2417 break;
2418 }
2419
2420 if (!cmndinfo->wait_for_completion)
2421 cmndinfo->wait_for_completion++;
2422 else
2423 return 1;
2424
2425 return 0;
2426 }
2427
2428 static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
2429 {
2430 register gdth_cmd_str *cmdp;
2431 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2432 ulong32 cnt, blockcnt;
2433 ulong64 no, blockno;
2434 int i, cmd_index, read_write, sgcnt, mode64;
2435
2436 cmdp = ha->pccb;
2437 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2438 scp->cmnd[0],scp->cmd_len,hdrive));
2439
2440 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2441 return 0;
2442
2443 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2444 /* test for READ_16, WRITE_16 if !mode64 ? ---
2445 not required, should not occur due to error return on
2446 READ_CAPACITY_16 */
2447
2448 cmdp->Service = CACHESERVICE;
2449 cmdp->RequestBuffer = scp;
2450 /* search free command index */
2451 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2452 TRACE(("GDT: No free command index found\n"));
2453 return 0;
2454 }
2455 /* if it's the first command, set command semaphore */
2456 if (ha->cmd_cnt == 0)
2457 gdth_set_sema0(ha);
2458
2459 /* fill command */
2460 read_write = 0;
2461 if (cmndinfo->OpCode != -1)
2462 cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
2463 else if (scp->cmnd[0] == RESERVE)
2464 cmdp->OpCode = GDT_RESERVE_DRV;
2465 else if (scp->cmnd[0] == RELEASE)
2466 cmdp->OpCode = GDT_RELEASE_DRV;
2467 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2468 if (scp->cmnd[4] & 1) /* prevent ? */
2469 cmdp->OpCode = GDT_MOUNT;
2470 else if (scp->cmnd[3] & 1) /* removable drive ? */
2471 cmdp->OpCode = GDT_UNMOUNT;
2472 else
2473 cmdp->OpCode = GDT_FLUSH;
2474 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2475 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2476 ) {
2477 read_write = 1;
2478 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2479 (ha->cache_feat & GDT_WR_THROUGH)))
2480 cmdp->OpCode = GDT_WRITE_THR;
2481 else
2482 cmdp->OpCode = GDT_WRITE;
2483 } else {
2484 read_write = 2;
2485 cmdp->OpCode = GDT_READ;
2486 }
2487
2488 cmdp->BoardNode = LOCALBOARD;
2489 if (mode64) {
2490 cmdp->u.cache64.DeviceNo = hdrive;
2491 cmdp->u.cache64.BlockNo = 1;
2492 cmdp->u.cache64.sg_canz = 0;
2493 } else {
2494 cmdp->u.cache.DeviceNo = hdrive;
2495 cmdp->u.cache.BlockNo = 1;
2496 cmdp->u.cache.sg_canz = 0;
2497 }
2498
2499 if (read_write) {
2500 if (scp->cmd_len == 16) {
2501 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2502 blockno = be64_to_cpu(no);
2503 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2504 blockcnt = be32_to_cpu(cnt);
2505 } else if (scp->cmd_len == 10) {
2506 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2507 blockno = be32_to_cpu(no);
2508 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2509 blockcnt = be16_to_cpu(cnt);
2510 } else {
2511 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2512 blockno = be32_to_cpu(no) & 0x001fffffUL;
2513 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2514 }
2515 if (mode64) {
2516 cmdp->u.cache64.BlockNo = blockno;
2517 cmdp->u.cache64.BlockCnt = blockcnt;
2518 } else {
2519 cmdp->u.cache.BlockNo = (ulong32)blockno;
2520 cmdp->u.cache.BlockCnt = blockcnt;
2521 }
2522
2523 if (scsi_bufflen(scp)) {
2524 cmndinfo->dma_dir = (read_write == 1 ?
2525 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2526 sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
2527 cmndinfo->dma_dir);
2528 if (mode64) {
2529 struct scatterlist *sl;
2530
2531 cmdp->u.cache64.DestAddr= (ulong64)-1;
2532 cmdp->u.cache64.sg_canz = sgcnt;
2533 scsi_for_each_sg(scp, sl, sgcnt, i) {
2534 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2535 #ifdef GDTH_DMA_STATISTICS
2536 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2537 ha->dma64_cnt++;
2538 else
2539 ha->dma32_cnt++;
2540 #endif
2541 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2542 }
2543 } else {
2544 struct scatterlist *sl;
2545
2546 cmdp->u.cache.DestAddr= 0xffffffff;
2547 cmdp->u.cache.sg_canz = sgcnt;
2548 scsi_for_each_sg(scp, sl, sgcnt, i) {
2549 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2550 #ifdef GDTH_DMA_STATISTICS
2551 ha->dma32_cnt++;
2552 #endif
2553 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2554 }
2555 }
2556
2557 #ifdef GDTH_STATISTICS
2558 if (max_sg < (ulong32)sgcnt) {
2559 max_sg = (ulong32)sgcnt;
2560 TRACE3(("GDT: max_sg = %d\n",max_sg));
2561 }
2562 #endif
2563
2564 }
2565 }
2566 /* evaluate command size, check space */
2567 if (mode64) {
2568 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2569 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2570 cmdp->u.cache64.sg_lst[0].sg_ptr,
2571 cmdp->u.cache64.sg_lst[0].sg_len));
2572 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2573 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2574 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2575 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2576 } else {
2577 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2578 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2579 cmdp->u.cache.sg_lst[0].sg_ptr,
2580 cmdp->u.cache.sg_lst[0].sg_len));
2581 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2582 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2583 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2584 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2585 }
2586 if (ha->cmd_len & 3)
2587 ha->cmd_len += (4 - (ha->cmd_len & 3));
2588
2589 if (ha->cmd_cnt > 0) {
2590 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2591 ha->ic_all_size) {
2592 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
2593 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2594 return 0;
2595 }
2596 }
2597
2598 /* copy command */
2599 gdth_copy_command(ha);
2600 return cmd_index;
2601 }
2602
2603 static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
2604 {
2605 register gdth_cmd_str *cmdp;
2606 ushort i;
2607 dma_addr_t sense_paddr;
2608 int cmd_index, sgcnt, mode64;
2609 unchar t,l;
2610 struct page *page;
2611 ulong offset;
2612 struct gdth_cmndinfo *cmndinfo;
2613
2614 t = scp->device->id;
2615 l = scp->device->lun;
2616 cmdp = ha->pccb;
2617 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
2618 scp->cmnd[0],b,t,l));
2619
2620 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2621 return 0;
2622
2623 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
2624
2625 cmdp->Service = SCSIRAWSERVICE;
2626 cmdp->RequestBuffer = scp;
2627 /* search free command index */
2628 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2629 TRACE(("GDT: No free command index found\n"));
2630 return 0;
2631 }
2632 /* if it's the first command, set command semaphore */
2633 if (ha->cmd_cnt == 0)
2634 gdth_set_sema0(ha);
2635
2636 cmndinfo = gdth_cmnd_priv(scp);
2637 /* fill command */
2638 if (cmndinfo->OpCode != -1) {
2639 cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
2640 cmdp->BoardNode = LOCALBOARD;
2641 if (mode64) {
2642 cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
2643 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2644 cmdp->OpCode, cmdp->u.raw64.direction));
2645 /* evaluate command size */
2646 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
2647 } else {
2648 cmdp->u.raw.direction = (cmndinfo->phase >> 8);
2649 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2650 cmdp->OpCode, cmdp->u.raw.direction));
2651 /* evaluate command size */
2652 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
2653 }
2654
2655 } else {
2656 page = virt_to_page(scp->sense_buffer);
2657 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
2658 sense_paddr = pci_map_page(ha->pdev,page,offset,
2659 16,PCI_DMA_FROMDEVICE);
2660
2661 cmndinfo->sense_paddr = sense_paddr;
2662 cmdp->OpCode = GDT_WRITE; /* always */
2663 cmdp->BoardNode = LOCALBOARD;
2664 if (mode64) {
2665 cmdp->u.raw64.reserved = 0;
2666 cmdp->u.raw64.mdisc_time = 0;
2667 cmdp->u.raw64.mcon_time = 0;
2668 cmdp->u.raw64.clen = scp->cmd_len;
2669 cmdp->u.raw64.target = t;
2670 cmdp->u.raw64.lun = l;
2671 cmdp->u.raw64.bus = b;
2672 cmdp->u.raw64.priority = 0;
2673 cmdp->u.raw64.sdlen = scsi_bufflen(scp);
2674 cmdp->u.raw64.sense_len = 16;
2675 cmdp->u.raw64.sense_data = sense_paddr;
2676 cmdp->u.raw64.direction =
2677 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2678 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
2679 cmdp->u.raw64.sg_ranz = 0;
2680 } else {
2681 cmdp->u.raw.reserved = 0;
2682 cmdp->u.raw.mdisc_time = 0;
2683 cmdp->u.raw.mcon_time = 0;
2684 cmdp->u.raw.clen = scp->cmd_len;
2685 cmdp->u.raw.target = t;
2686 cmdp->u.raw.lun = l;
2687 cmdp->u.raw.bus = b;
2688 cmdp->u.raw.priority = 0;
2689 cmdp->u.raw.link_p = 0;
2690 cmdp->u.raw.sdlen = scsi_bufflen(scp);
2691 cmdp->u.raw.sense_len = 16;
2692 cmdp->u.raw.sense_data = sense_paddr;
2693 cmdp->u.raw.direction =
2694 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2695 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
2696 cmdp->u.raw.sg_ranz = 0;
2697 }
2698
2699 if (scsi_bufflen(scp)) {
2700 cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
2701 sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
2702 cmndinfo->dma_dir);
2703 if (mode64) {
2704 struct scatterlist *sl;
2705
2706 cmdp->u.raw64.sdata = (ulong64)-1;
2707 cmdp->u.raw64.sg_ranz = sgcnt;
2708 scsi_for_each_sg(scp, sl, sgcnt, i) {
2709 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2710 #ifdef GDTH_DMA_STATISTICS
2711 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2712 ha->dma64_cnt++;
2713 else
2714 ha->dma32_cnt++;
2715 #endif
2716 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
2717 }
2718 } else {
2719 struct scatterlist *sl;
2720
2721 cmdp->u.raw.sdata = 0xffffffff;
2722 cmdp->u.raw.sg_ranz = sgcnt;
2723 scsi_for_each_sg(scp, sl, sgcnt, i) {
2724 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
2725 #ifdef GDTH_DMA_STATISTICS
2726 ha->dma32_cnt++;
2727 #endif
2728 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
2729 }
2730 }
2731
2732 #ifdef GDTH_STATISTICS
2733 if (max_sg < sgcnt) {
2734 max_sg = sgcnt;
2735 TRACE3(("GDT: max_sg = %d\n",sgcnt));
2736 }
2737 #endif
2738
2739 }
2740 if (mode64) {
2741 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2742 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
2743 cmdp->u.raw64.sg_lst[0].sg_ptr,
2744 cmdp->u.raw64.sg_lst[0].sg_len));
2745 /* evaluate command size */
2746 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
2747 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
2748 } else {
2749 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2750 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
2751 cmdp->u.raw.sg_lst[0].sg_ptr,
2752 cmdp->u.raw.sg_lst[0].sg_len));
2753 /* evaluate command size */
2754 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
2755 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
2756 }
2757 }
2758 /* check space */
2759 if (ha->cmd_len & 3)
2760 ha->cmd_len += (4 - (ha->cmd_len & 3));
2761
2762 if (ha->cmd_cnt > 0) {
2763 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2764 ha->ic_all_size) {
2765 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
2766 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2767 return 0;
2768 }
2769 }
2770
2771 /* copy command */
2772 gdth_copy_command(ha);
2773 return cmd_index;
2774 }
2775
2776 static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
2777 {
2778 register gdth_cmd_str *cmdp;
2779 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2780 int cmd_index;
2781
2782 cmdp= ha->pccb;
2783 TRACE2(("gdth_special_cmd(): "));
2784
2785 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2786 return 0;
2787
2788 *cmdp = *cmndinfo->internal_cmd_str;
2789 cmdp->RequestBuffer = scp;
2790
2791 /* search free command index */
2792 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2793 TRACE(("GDT: No free command index found\n"));
2794 return 0;
2795 }
2796
2797 /* if it's the first command, set command semaphore */
2798 if (ha->cmd_cnt == 0)
2799 gdth_set_sema0(ha);
2800
2801 /* evaluate command size, check space */
2802 if (cmdp->OpCode == GDT_IOCTL) {
2803 TRACE2(("IOCTL\n"));
2804 ha->cmd_len =
2805 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
2806 } else if (cmdp->Service == CACHESERVICE) {
2807 TRACE2(("cache command %d\n",cmdp->OpCode));
2808 if (ha->cache_feat & GDT_64BIT)
2809 ha->cmd_len =
2810 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
2811 else
2812 ha->cmd_len =
2813 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
2814 } else if (cmdp->Service == SCSIRAWSERVICE) {
2815 TRACE2(("raw command %d\n",cmdp->OpCode));
2816 if (ha->raw_feat & GDT_64BIT)
2817 ha->cmd_len =
2818 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
2819 else
2820 ha->cmd_len =
2821 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
2822 }
2823
2824 if (ha->cmd_len & 3)
2825 ha->cmd_len += (4 - (ha->cmd_len & 3));
2826
2827 if (ha->cmd_cnt > 0) {
2828 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2829 ha->ic_all_size) {
2830 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
2831 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2832 return 0;
2833 }
2834 }
2835
2836 /* copy command */
2837 gdth_copy_command(ha);
2838 return cmd_index;
2839 }
2840
2841
2842 /* Controller event handling functions */
2843 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
2844 ushort idx, gdth_evt_data *evt)
2845 {
2846 gdth_evt_str *e;
2847 struct timeval tv;
2848
2849 /* no GDTH_LOCK_HA() ! */
2850 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
2851 if (source == 0) /* no source -> no event */
2852 return NULL;
2853
2854 if (ebuffer[elastidx].event_source == source &&
2855 ebuffer[elastidx].event_idx == idx &&
2856 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
2857 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
2858 (char *)&evt->eu, evt->size)) ||
2859 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
2860 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
2861 (char *)&evt->event_string)))) {
2862 e = &ebuffer[elastidx];
2863 do_gettimeofday(&tv);
2864 e->last_stamp = tv.tv_sec;
2865 ++e->same_count;
2866 } else {
2867 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
2868 ++elastidx;
2869 if (elastidx == MAX_EVENTS)
2870 elastidx = 0;
2871 if (elastidx == eoldidx) { /* reached mark ? */
2872 ++eoldidx;
2873 if (eoldidx == MAX_EVENTS)
2874 eoldidx = 0;
2875 }
2876 }
2877 e = &ebuffer[elastidx];
2878 e->event_source = source;
2879 e->event_idx = idx;
2880 do_gettimeofday(&tv);
2881 e->first_stamp = e->last_stamp = tv.tv_sec;
2882 e->same_count = 1;
2883 e->event_data = *evt;
2884 e->application = 0;
2885 }
2886 return e;
2887 }
2888
2889 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
2890 {
2891 gdth_evt_str *e;
2892 int eindex;
2893 ulong flags;
2894
2895 TRACE2(("gdth_read_event() handle %d\n", handle));
2896 spin_lock_irqsave(&ha->smp_lock, flags);
2897 if (handle == -1)
2898 eindex = eoldidx;
2899 else
2900 eindex = handle;
2901 estr->event_source = 0;
2902
2903 if (eindex < 0 || eindex >= MAX_EVENTS) {
2904 spin_unlock_irqrestore(&ha->smp_lock, flags);
2905 return eindex;
2906 }
2907 e = &ebuffer[eindex];
2908 if (e->event_source != 0) {
2909 if (eindex != elastidx) {
2910 if (++eindex == MAX_EVENTS)
2911 eindex = 0;
2912 } else {
2913 eindex = -1;
2914 }
2915 memcpy(estr, e, sizeof(gdth_evt_str));
2916 }
2917 spin_unlock_irqrestore(&ha->smp_lock, flags);
2918 return eindex;
2919 }
2920
2921 static void gdth_readapp_event(gdth_ha_str *ha,
2922 unchar application, gdth_evt_str *estr)
2923 {
2924 gdth_evt_str *e;
2925 int eindex;
2926 ulong flags;
2927 unchar found = FALSE;
2928
2929 TRACE2(("gdth_readapp_event() app. %d\n", application));
2930 spin_lock_irqsave(&ha->smp_lock, flags);
2931 eindex = eoldidx;
2932 for (;;) {
2933 e = &ebuffer[eindex];
2934 if (e->event_source == 0)
2935 break;
2936 if ((e->application & application) == 0) {
2937 e->application |= application;
2938 found = TRUE;
2939 break;
2940 }
2941 if (eindex == elastidx)
2942 break;
2943 if (++eindex == MAX_EVENTS)
2944 eindex = 0;
2945 }
2946 if (found)
2947 memcpy(estr, e, sizeof(gdth_evt_str));
2948 else
2949 estr->event_source = 0;
2950 spin_unlock_irqrestore(&ha->smp_lock, flags);
2951 }
2952
2953 static void gdth_clear_events(void)
2954 {
2955 TRACE(("gdth_clear_events()"));
2956
2957 eoldidx = elastidx = 0;
2958 ebuffer[0].event_source = 0;
2959 }
2960
2961
2962 /* SCSI interface functions */
2963
2964 static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
2965 int gdth_from_wait, int* pIndex)
2966 {
2967 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
2968 gdt6_dpram_str __iomem *dp6_ptr;
2969 gdt2_dpram_str __iomem *dp2_ptr;
2970 Scsi_Cmnd *scp;
2971 int rval, i;
2972 unchar IStatus;
2973 ushort Service;
2974 ulong flags = 0;
2975 #ifdef INT_COAL
2976 int coalesced = FALSE;
2977 int next = FALSE;
2978 gdth_coal_status *pcs = NULL;
2979 int act_int_coal = 0;
2980 #endif
2981
2982 TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
2983
2984 /* if polling and not from gdth_wait() -> return */
2985 if (gdth_polling) {
2986 if (!gdth_from_wait) {
2987 return IRQ_HANDLED;
2988 }
2989 }
2990
2991 if (!gdth_polling)
2992 spin_lock_irqsave(&ha->smp_lock, flags);
2993
2994 /* search controller */
2995 IStatus = gdth_get_status(ha);
2996 if (IStatus == 0) {
2997 /* spurious interrupt */
2998 if (!gdth_polling)
2999 spin_unlock_irqrestore(&ha->smp_lock, flags);
3000 return IRQ_HANDLED;
3001 }
3002
3003 #ifdef GDTH_STATISTICS
3004 ++act_ints;
3005 #endif
3006
3007 #ifdef INT_COAL
3008 /* See if the fw is returning coalesced status */
3009 if (IStatus == COALINDEX) {
3010 /* Coalesced status. Setup the initial status
3011 buffer pointer and flags */
3012 pcs = ha->coal_stat;
3013 coalesced = TRUE;
3014 next = TRUE;
3015 }
3016
3017 do {
3018 if (coalesced) {
3019 /* For coalesced requests all status
3020 information is found in the status buffer */
3021 IStatus = (unchar)(pcs->status & 0xff);
3022 }
3023 #endif
3024
3025 if (ha->type == GDT_EISA) {
3026 if (IStatus & 0x80) { /* error flag */
3027 IStatus &= ~0x80;
3028 ha->status = inw(ha->bmic + MAILBOXREG+8);
3029 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3030 } else /* no error */
3031 ha->status = S_OK;
3032 ha->info = inl(ha->bmic + MAILBOXREG+12);
3033 ha->service = inw(ha->bmic + MAILBOXREG+10);
3034 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3035
3036 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3037 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3038 } else if (ha->type == GDT_ISA) {
3039 dp2_ptr = ha->brd;
3040 if (IStatus & 0x80) { /* error flag */
3041 IStatus &= ~0x80;
3042 ha->status = readw(&dp2_ptr->u.ic.Status);
3043 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3044 } else /* no error */
3045 ha->status = S_OK;
3046 ha->info = readl(&dp2_ptr->u.ic.Info[0]);
3047 ha->service = readw(&dp2_ptr->u.ic.Service);
3048 ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
3049
3050 writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3051 writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3052 writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3053 } else if (ha->type == GDT_PCI) {
3054 dp6_ptr = ha->brd;
3055 if (IStatus & 0x80) { /* error flag */
3056 IStatus &= ~0x80;
3057 ha->status = readw(&dp6_ptr->u.ic.Status);
3058 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3059 } else /* no error */
3060 ha->status = S_OK;
3061 ha->info = readl(&dp6_ptr->u.ic.Info[0]);
3062 ha->service = readw(&dp6_ptr->u.ic.Service);
3063 ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
3064
3065 writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3066 writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3067 writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3068 } else if (ha->type == GDT_PCINEW) {
3069 if (IStatus & 0x80) { /* error flag */
3070 IStatus &= ~0x80;
3071 ha->status = inw(PTR2USHORT(&ha->plx->status));
3072 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3073 } else
3074 ha->status = S_OK;
3075 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3076 ha->service = inw(PTR2USHORT(&ha->plx->service));
3077 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3078
3079 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3080 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3081 } else if (ha->type == GDT_PCIMPR) {
3082 dp6m_ptr = ha->brd;
3083 if (IStatus & 0x80) { /* error flag */
3084 IStatus &= ~0x80;
3085 #ifdef INT_COAL
3086 if (coalesced)
3087 ha->status = pcs->ext_status & 0xffff;
3088 else
3089 #endif
3090 ha->status = readw(&dp6m_ptr->i960r.status);
3091 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3092 } else /* no error */
3093 ha->status = S_OK;
3094 #ifdef INT_COAL
3095 /* get information */
3096 if (coalesced) {
3097 ha->info = pcs->info0;
3098 ha->info2 = pcs->info1;
3099 ha->service = (pcs->ext_status >> 16) & 0xffff;
3100 } else
3101 #endif
3102 {
3103 ha->info = readl(&dp6m_ptr->i960r.info[0]);
3104 ha->service = readw(&dp6m_ptr->i960r.service);
3105 ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
3106 }
3107 /* event string */
3108 if (IStatus == ASYNCINDEX) {
3109 if (ha->service != SCREENSERVICE &&
3110 (ha->fw_vers & 0xff) >= 0x1a) {
3111 ha->dvr.severity = readb
3112 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3113 for (i = 0; i < 256; ++i) {
3114 ha->dvr.event_string[i] = readb
3115 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3116 if (ha->dvr.event_string[i] == 0)
3117 break;
3118 }
3119 }
3120 }
3121 #ifdef INT_COAL
3122 /* Make sure that non coalesced interrupts get cleared
3123 before being handled by gdth_async_event/gdth_sync_event */
3124 if (!coalesced)
3125 #endif
3126 {
3127 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3128 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3129 }
3130 } else {
3131 TRACE2(("gdth_interrupt() unknown controller type\n"));
3132 if (!gdth_polling)
3133 spin_unlock_irqrestore(&ha->smp_lock, flags);
3134 return IRQ_HANDLED;
3135 }
3136
3137 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3138 IStatus,ha->status,ha->info));
3139
3140 if (gdth_from_wait) {
3141 *pIndex = (int)IStatus;
3142 }
3143
3144 if (IStatus == ASYNCINDEX) {
3145 TRACE2(("gdth_interrupt() async. event\n"));
3146 gdth_async_event(ha);
3147 if (!gdth_polling)
3148 spin_unlock_irqrestore(&ha->smp_lock, flags);
3149 gdth_next(ha);
3150 return IRQ_HANDLED;
3151 }
3152
3153 if (IStatus == SPEZINDEX) {
3154 TRACE2(("Service unknown or not initialized !\n"));
3155 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3156 ha->dvr.eu.driver.ionode = ha->hanum;
3157 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3158 if (!gdth_polling)
3159 spin_unlock_irqrestore(&ha->smp_lock, flags);
3160 return IRQ_HANDLED;
3161 }
3162 scp = ha->cmd_tab[IStatus-2].cmnd;
3163 Service = ha->cmd_tab[IStatus-2].service;
3164 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3165 if (scp == UNUSED_CMND) {
3166 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3167 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3168 ha->dvr.eu.driver.ionode = ha->hanum;
3169 ha->dvr.eu.driver.index = IStatus;
3170 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3171 if (!gdth_polling)
3172 spin_unlock_irqrestore(&ha->smp_lock, flags);
3173 return IRQ_HANDLED;
3174 }
3175 if (scp == INTERNAL_CMND) {
3176 TRACE(("gdth_interrupt() answer to internal command\n"));
3177 if (!gdth_polling)
3178 spin_unlock_irqrestore(&ha->smp_lock, flags);
3179 return IRQ_HANDLED;
3180 }
3181
3182 TRACE(("gdth_interrupt() sync. status\n"));
3183 rval = gdth_sync_event(ha,Service,IStatus,scp);
3184 if (!gdth_polling)
3185 spin_unlock_irqrestore(&ha->smp_lock, flags);
3186 if (rval == 2) {
3187 gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
3188 } else if (rval == 1) {
3189 gdth_scsi_done(scp);
3190 }
3191
3192 #ifdef INT_COAL
3193 if (coalesced) {
3194 /* go to the next status in the status buffer */
3195 ++pcs;
3196 #ifdef GDTH_STATISTICS
3197 ++act_int_coal;
3198 if (act_int_coal > max_int_coal) {
3199 max_int_coal = act_int_coal;
3200 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3201 }
3202 #endif
3203 /* see if there is another status */
3204 if (pcs->status == 0)
3205 /* Stop the coalesce loop */
3206 next = FALSE;
3207 }
3208 } while (next);
3209
3210 /* coalescing only for new GDT_PCIMPR controllers available */
3211 if (ha->type == GDT_PCIMPR && coalesced) {
3212 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3213 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3214 }
3215 #endif
3216
3217 gdth_next(ha);
3218 return IRQ_HANDLED;
3219 }
3220
3221 static irqreturn_t gdth_interrupt(int irq, void *dev_id)
3222 {
3223 gdth_ha_str *ha = dev_id;
3224
3225 return __gdth_interrupt(ha, false, NULL);
3226 }
3227
3228 static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
3229 Scsi_Cmnd *scp)
3230 {
3231 gdth_msg_str *msg;
3232 gdth_cmd_str *cmdp;
3233 unchar b, t;
3234 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
3235
3236 cmdp = ha->pccb;
3237 TRACE(("gdth_sync_event() serv %d status %d\n",
3238 service,ha->status));
3239
3240 if (service == SCREENSERVICE) {
3241 msg = ha->pmsg;
3242 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3243 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3244 if (msg->msg_len > MSGLEN+1)
3245 msg->msg_len = MSGLEN+1;
3246 if (msg->msg_len)
3247 if (!(msg->msg_answer && msg->msg_ext)) {
3248 msg->msg_text[msg->msg_len] = '\0';
3249 printk("%s",msg->msg_text);
3250 }
3251
3252 if (msg->msg_ext && !msg->msg_answer) {
3253 while (gdth_test_busy(ha))
3254 gdth_delay(0);
3255 cmdp->Service = SCREENSERVICE;
3256 cmdp->RequestBuffer = SCREEN_CMND;
3257 gdth_get_cmd_index(ha);
3258 gdth_set_sema0(ha);
3259 cmdp->OpCode = GDT_READ;
3260 cmdp->BoardNode = LOCALBOARD;
3261 cmdp->u.screen.reserved = 0;
3262 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3263 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3264 ha->cmd_offs_dpmem = 0;
3265 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3266 + sizeof(ulong64);
3267 ha->cmd_cnt = 0;
3268 gdth_copy_command(ha);
3269 gdth_release_event(ha);
3270 return 0;
3271 }
3272
3273 if (msg->msg_answer && msg->msg_alen) {
3274 /* default answers (getchar() not possible) */
3275 if (msg->msg_alen == 1) {
3276 msg->msg_alen = 0;
3277 msg->msg_len = 1;
3278 msg->msg_text[0] = 0;
3279 } else {
3280 msg->msg_alen -= 2;
3281 msg->msg_len = 2;
3282 msg->msg_text[0] = 1;
3283 msg->msg_text[1] = 0;
3284 }
3285 msg->msg_ext = 0;
3286 msg->msg_answer = 0;
3287 while (gdth_test_busy(ha))
3288 gdth_delay(0);
3289 cmdp->Service = SCREENSERVICE;
3290 cmdp->RequestBuffer = SCREEN_CMND;
3291 gdth_get_cmd_index(ha);
3292 gdth_set_sema0(ha);
3293 cmdp->OpCode = GDT_WRITE;
3294 cmdp->BoardNode = LOCALBOARD;
3295 cmdp->u.screen.reserved = 0;
3296 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3297 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3298 ha->cmd_offs_dpmem = 0;
3299 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3300 + sizeof(ulong64);
3301 ha->cmd_cnt = 0;
3302 gdth_copy_command(ha);
3303 gdth_release_event(ha);
3304 return 0;
3305 }
3306 printk("\n");
3307
3308 } else {
3309 b = scp->device->channel;
3310 t = scp->device->id;
3311 if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
3312 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3313 }
3314 /* cache or raw service */
3315 if (ha->status == S_BSY) {
3316 TRACE2(("Controller busy -> retry !\n"));
3317 if (cmndinfo->OpCode == GDT_MOUNT)
3318 cmndinfo->OpCode = GDT_CLUST_INFO;
3319 /* retry */
3320 return 2;
3321 }
3322 if (scsi_bufflen(scp))
3323 pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
3324 cmndinfo->dma_dir);
3325
3326 if (cmndinfo->sense_paddr)
3327 pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
3328 PCI_DMA_FROMDEVICE);
3329
3330 if (ha->status == S_OK) {
3331 cmndinfo->status = S_OK;
3332 cmndinfo->info = ha->info;
3333 if (cmndinfo->OpCode != -1) {
3334 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3335 cmndinfo->OpCode));
3336 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3337 if (cmndinfo->OpCode == GDT_CLUST_INFO) {
3338 ha->hdr[t].cluster_type = (unchar)ha->info;
3339 if (!(ha->hdr[t].cluster_type &
3340 CLUSTER_MOUNTED)) {
3341 /* NOT MOUNTED -> MOUNT */
3342 cmndinfo->OpCode = GDT_MOUNT;
3343 if (ha->hdr[t].cluster_type &
3344 CLUSTER_RESERVED) {
3345 /* cluster drive RESERVED (on the other node) */
3346 cmndinfo->phase = -2; /* reservation conflict */
3347 }
3348 } else {
3349 cmndinfo->OpCode = -1;
3350 }
3351 } else {
3352 if (cmndinfo->OpCode == GDT_MOUNT) {
3353 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3354 ha->hdr[t].media_changed = TRUE;
3355 } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
3356 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3357 ha->hdr[t].media_changed = TRUE;
3358 }
3359 cmndinfo->OpCode = -1;
3360 }
3361 /* retry */
3362 cmndinfo->priority = HIGH_PRI;
3363 return 2;
3364 } else {
3365 /* RESERVE/RELEASE ? */
3366 if (scp->cmnd[0] == RESERVE) {
3367 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3368 } else if (scp->cmnd[0] == RELEASE) {
3369 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3370 }
3371 scp->result = DID_OK << 16;
3372 scp->sense_buffer[0] = 0;
3373 }
3374 } else {
3375 cmndinfo->status = ha->status;
3376 cmndinfo->info = ha->info;
3377
3378 if (cmndinfo->OpCode != -1) {
3379 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3380 cmndinfo->OpCode, ha->status));
3381 if (cmndinfo->OpCode == GDT_SCAN_START ||
3382 cmndinfo->OpCode == GDT_SCAN_END) {
3383 cmndinfo->OpCode = -1;
3384 /* retry */
3385 cmndinfo->priority = HIGH_PRI;
3386 return 2;
3387 }
3388 memset((char*)scp->sense_buffer,0,16);
3389 scp->sense_buffer[0] = 0x70;
3390 scp->sense_buffer[2] = NOT_READY;
3391 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3392 } else if (service == CACHESERVICE) {
3393 if (ha->status == S_CACHE_UNKNOWN &&
3394 (ha->hdr[t].cluster_type &
3395 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3396 /* bus reset -> force GDT_CLUST_INFO */
3397 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3398 }
3399 memset((char*)scp->sense_buffer,0,16);
3400 if (ha->status == (ushort)S_CACHE_RESERV) {
3401 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3402 } else {
3403 scp->sense_buffer[0] = 0x70;
3404 scp->sense_buffer[2] = NOT_READY;
3405 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3406 }
3407 if (!cmndinfo->internal_command) {
3408 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3409 ha->dvr.eu.sync.ionode = ha->hanum;
3410 ha->dvr.eu.sync.service = service;
3411 ha->dvr.eu.sync.status = ha->status;
3412 ha->dvr.eu.sync.info = ha->info;
3413 ha->dvr.eu.sync.hostdrive = t;
3414 if (ha->status >= 0x8000)
3415 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3416 else
3417 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3418 }
3419 } else {
3420 /* sense buffer filled from controller firmware (DMA) */
3421 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3422 scp->result = DID_BAD_TARGET << 16;
3423 } else {
3424 scp->result = (DID_OK << 16) | ha->info;
3425 }
3426 }
3427 }
3428 if (!cmndinfo->wait_for_completion)
3429 cmndinfo->wait_for_completion++;
3430 else
3431 return 1;
3432 }
3433
3434 return 0;
3435 }
3436
3437 static char *async_cache_tab[] = {
3438 /* 0*/ "\011\000\002\002\002\004\002\006\004"
3439 "GDT HA %u, service %u, async. status %u/%lu unknown",
3440 /* 1*/ "\011\000\002\002\002\004\002\006\004"
3441 "GDT HA %u, service %u, async. status %u/%lu unknown",
3442 /* 2*/ "\005\000\002\006\004"
3443 "GDT HA %u, Host Drive %lu not ready",
3444 /* 3*/ "\005\000\002\006\004"
3445 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3446 /* 4*/ "\005\000\002\006\004"
3447 "GDT HA %u, mirror update on Host Drive %lu failed",
3448 /* 5*/ "\005\000\002\006\004"
3449 "GDT HA %u, Mirror Drive %lu failed",
3450 /* 6*/ "\005\000\002\006\004"
3451 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3452 /* 7*/ "\005\000\002\006\004"
3453 "GDT HA %u, Host Drive %lu write protected",
3454 /* 8*/ "\005\000\002\006\004"
3455 "GDT HA %u, media changed in Host Drive %lu",
3456 /* 9*/ "\005\000\002\006\004"
3457 "GDT HA %u, Host Drive %lu is offline",
3458 /*10*/ "\005\000\002\006\004"
3459 "GDT HA %u, media change of Mirror Drive %lu",
3460 /*11*/ "\005\000\002\006\004"
3461 "GDT HA %u, Mirror Drive %lu is write protected",
3462 /*12*/ "\005\000\002\006\004"
3463 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3464 /*13*/ "\007\000\002\006\002\010\002"
3465 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3466 /*14*/ "\005\000\002\006\002"
3467 "GDT HA %u, Array Drive %u: FAIL state entered",
3468 /*15*/ "\005\000\002\006\002"
3469 "GDT HA %u, Array Drive %u: error",
3470 /*16*/ "\007\000\002\006\002\010\002"
3471 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3472 /*17*/ "\005\000\002\006\002"
3473 "GDT HA %u, Array Drive %u: parity build failed",
3474 /*18*/ "\005\000\002\006\002"
3475 "GDT HA %u, Array Drive %u: drive rebuild failed",
3476 /*19*/ "\005\000\002\010\002"
3477 "GDT HA %u, Test of Hot Fix %u failed",
3478 /*20*/ "\005\000\002\006\002"
3479 "GDT HA %u, Array Drive %u: drive build finished successfully",
3480 /*21*/ "\005\000\002\006\002"
3481 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3482 /*22*/ "\007\000\002\006\002\010\002"
3483 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3484 /*23*/ "\005\000\002\006\002"
3485 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3486 /*24*/ "\005\000\002\010\002"
3487 "GDT HA %u, mirror update on Cache Drive %u completed",
3488 /*25*/ "\005\000\002\010\002"
3489 "GDT HA %u, mirror update on Cache Drive %lu failed",
3490 /*26*/ "\005\000\002\006\002"
3491 "GDT HA %u, Array Drive %u: drive rebuild started",
3492 /*27*/ "\005\000\002\012\001"
3493 "GDT HA %u, Fault bus %u: SHELF OK detected",
3494 /*28*/ "\005\000\002\012\001"
3495 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3496 /*29*/ "\007\000\002\012\001\013\001"
3497 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3498 /*30*/ "\007\000\002\012\001\013\001"
3499 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3500 /*31*/ "\007\000\002\012\001\013\001"
3501 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3502 /*32*/ "\007\000\002\012\001\013\001"
3503 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3504 /*33*/ "\007\000\002\012\001\013\001"
3505 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3506 /*34*/ "\011\000\002\012\001\013\001\006\004"
3507 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3508 /*35*/ "\007\000\002\012\001\013\001"
3509 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3510 /*36*/ "\007\000\002\012\001\013\001"
3511 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3512 /*37*/ "\007\000\002\012\001\006\004"
3513 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3514 /*38*/ "\007\000\002\012\001\013\001"
3515 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3516 /*39*/ "\007\000\002\012\001\013\001"
3517 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3518 /*40*/ "\007\000\002\012\001\013\001"
3519 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3520 /*41*/ "\007\000\002\012\001\013\001"
3521 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3522 /*42*/ "\005\000\002\006\002"
3523 "GDT HA %u, Array Drive %u: drive build started",
3524 /*43*/ "\003\000\002"
3525 "GDT HA %u, DRAM parity error detected",
3526 /*44*/ "\005\000\002\006\002"
3527 "GDT HA %u, Mirror Drive %u: update started",
3528 /*45*/ "\007\000\002\006\002\010\002"
3529 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3530 /*46*/ "\005\000\002\006\002"
3531 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3532 /*47*/ "\005\000\002\006\002"
3533 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3534 /*48*/ "\005\000\002\006\002"
3535 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3536 /*49*/ "\005\000\002\006\002"
3537 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3538 /*50*/ "\007\000\002\012\001\013\001"
3539 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3540 /*51*/ "\005\000\002\006\002"
3541 "GDT HA %u, Array Drive %u: expand started",
3542 /*52*/ "\005\000\002\006\002"
3543 "GDT HA %u, Array Drive %u: expand finished successfully",
3544 /*53*/ "\005\000\002\006\002"
3545 "GDT HA %u, Array Drive %u: expand failed",
3546 /*54*/ "\003\000\002"
3547 "GDT HA %u, CPU temperature critical",
3548 /*55*/ "\003\000\002"
3549 "GDT HA %u, CPU temperature OK",
3550 /*56*/ "\005\000\002\006\004"
3551 "GDT HA %u, Host drive %lu created",
3552 /*57*/ "\005\000\002\006\002"
3553 "GDT HA %u, Array Drive %u: expand restarted",
3554 /*58*/ "\005\000\002\006\002"
3555 "GDT HA %u, Array Drive %u: expand stopped",
3556 /*59*/ "\005\000\002\010\002"
3557 "GDT HA %u, Mirror Drive %u: drive build quited",
3558 /*60*/ "\005\000\002\006\002"
3559 "GDT HA %u, Array Drive %u: parity build quited",
3560 /*61*/ "\005\000\002\006\002"
3561 "GDT HA %u, Array Drive %u: drive rebuild quited",
3562 /*62*/ "\005\000\002\006\002"
3563 "GDT HA %u, Array Drive %u: parity verify started",
3564 /*63*/ "\005\000\002\006\002"
3565 "GDT HA %u, Array Drive %u: parity verify done",
3566 /*64*/ "\005\000\002\006\002"
3567 "GDT HA %u, Array Drive %u: parity verify failed",
3568 /*65*/ "\005\000\002\006\002"
3569 "GDT HA %u, Array Drive %u: parity error detected",
3570 /*66*/ "\005\000\002\006\002"
3571 "GDT HA %u, Array Drive %u: parity verify quited",
3572 /*67*/ "\005\000\002\006\002"
3573 "GDT HA %u, Host Drive %u reserved",
3574 /*68*/ "\005\000\002\006\002"
3575 "GDT HA %u, Host Drive %u mounted and released",
3576 /*69*/ "\005\000\002\006\002"
3577 "GDT HA %u, Host Drive %u released",
3578 /*70*/ "\003\000\002"
3579 "GDT HA %u, DRAM error detected and corrected with ECC",
3580 /*71*/ "\003\000\002"
3581 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
3582 /*72*/ "\011\000\002\012\001\013\001\014\001"
3583 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
3584 /*73*/ "\005\000\002\006\002"
3585 "GDT HA %u, Host drive %u resetted locally",
3586 /*74*/ "\005\000\002\006\002"
3587 "GDT HA %u, Host drive %u resetted remotely",
3588 /*75*/ "\003\000\002"
3589 "GDT HA %u, async. status 75 unknown",
3590 };
3591
3592
3593 static int gdth_async_event(gdth_ha_str *ha)
3594 {
3595 gdth_cmd_str *cmdp;
3596 int cmd_index;
3597
3598 cmdp= ha->pccb;
3599 TRACE2(("gdth_async_event() ha %d serv %d\n",
3600 ha->hanum, ha->service));
3601
3602 if (ha->service == SCREENSERVICE) {
3603 if (ha->status == MSG_REQUEST) {
3604 while (gdth_test_busy(ha))
3605 gdth_delay(0);
3606 cmdp->Service = SCREENSERVICE;
3607 cmdp->RequestBuffer = SCREEN_CMND;
3608 cmd_index = gdth_get_cmd_index(ha);
3609 gdth_set_sema0(ha);
3610 cmdp->OpCode = GDT_READ;
3611 cmdp->BoardNode = LOCALBOARD;
3612 cmdp->u.screen.reserved = 0;
3613 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
3614 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3615 ha->cmd_offs_dpmem = 0;
3616 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3617 + sizeof(ulong64);
3618 ha->cmd_cnt = 0;
3619 gdth_copy_command(ha);
3620 if (ha->type == GDT_EISA)
3621 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
3622 else if (ha->type == GDT_ISA)
3623 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
3624 else
3625 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
3626 (ushort)((ha->brd_phys>>3)&0x1f));
3627 gdth_release_event(ha);
3628 }
3629
3630 } else {
3631 if (ha->type == GDT_PCIMPR &&
3632 (ha->fw_vers & 0xff) >= 0x1a) {
3633 ha->dvr.size = 0;
3634 ha->dvr.eu.async.ionode = ha->hanum;
3635 ha->dvr.eu.async.status = ha->status;
3636 /* severity and event_string already set! */
3637 } else {
3638 ha->dvr.size = sizeof(ha->dvr.eu.async);
3639 ha->dvr.eu.async.ionode = ha->hanum;
3640 ha->dvr.eu.async.service = ha->service;
3641 ha->dvr.eu.async.status = ha->status;
3642 ha->dvr.eu.async.info = ha->info;
3643 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
3644 }
3645 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
3646 gdth_log_event( &ha->dvr, NULL );
3647
3648 /* new host drive from expand? */
3649 if (ha->service == CACHESERVICE && ha->status == 56) {
3650 TRACE2(("gdth_async_event(): new host drive %d created\n",
3651 (ushort)ha->info));
3652 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
3653 }
3654 }
3655 return 1;
3656 }
3657
3658 static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
3659 {
3660 gdth_stackframe stack;
3661 char *f = NULL;
3662 int i,j;
3663
3664 TRACE2(("gdth_log_event()\n"));
3665 if (dvr->size == 0) {
3666 if (buffer == NULL) {
3667 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
3668 } else {
3669 sprintf(buffer,"Adapter %d: %s\n",
3670 dvr->eu.async.ionode,dvr->event_string);
3671 }
3672 } else if (dvr->eu.async.service == CACHESERVICE &&
3673 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
3674 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
3675 dvr->eu.async.status));
3676
3677 f = async_cache_tab[dvr->eu.async.status];
3678
3679 /* i: parameter to push, j: stack element to fill */
3680 for (j=0,i=1; i < f[0]; i+=2) {
3681 switch (f[i+1]) {
3682 case 4:
3683 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
3684 break;
3685 case 2:
3686 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
3687 break;
3688 case 1:
3689 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
3690 break;
3691 default:
3692 break;
3693 }
3694 }
3695
3696 if (buffer == NULL) {
3697 printk(&f[(int)f[0]],stack);
3698 printk("\n");
3699 } else {
3700 sprintf(buffer,&f[(int)f[0]],stack);
3701 }
3702
3703 } else {
3704 if (buffer == NULL) {
3705 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
3706 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3707 } else {
3708 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
3709 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3710 }
3711 }
3712 }
3713
3714 #ifdef GDTH_STATISTICS
3715 static unchar gdth_timer_running;
3716
3717 static void gdth_timeout(ulong data)
3718 {
3719 ulong32 i;
3720 Scsi_Cmnd *nscp;
3721 gdth_ha_str *ha;
3722 ulong flags;
3723
3724 if(unlikely(list_empty(&gdth_instances))) {
3725 gdth_timer_running = 0;
3726 return;
3727 }
3728
3729 ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
3730 spin_lock_irqsave(&ha->smp_lock, flags);
3731
3732 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
3733 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
3734 ++act_stats;
3735
3736 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
3737 ++act_rq;
3738
3739 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
3740 act_ints, act_ios, act_stats, act_rq));
3741 act_ints = act_ios = 0;
3742
3743 gdth_timer.expires = jiffies + 30 * HZ;
3744 add_timer(&gdth_timer);
3745 spin_unlock_irqrestore(&ha->smp_lock, flags);
3746 }
3747
3748 static void gdth_timer_init(void)
3749 {
3750 if (gdth_timer_running)
3751 return;
3752 gdth_timer_running = 1;
3753 TRACE2(("gdth_detect(): Initializing timer !\n"));
3754 gdth_timer.expires = jiffies + HZ;
3755 gdth_timer.data = 0L;
3756 gdth_timer.function = gdth_timeout;
3757 add_timer(&gdth_timer);
3758 }
3759 #else
3760 static inline void gdth_timer_init(void)
3761 {
3762 }
3763 #endif
3764
3765 static void __init internal_setup(char *str,int *ints)
3766 {
3767 int i, argc;
3768 char *cur_str, *argv;
3769
3770 TRACE2(("internal_setup() str %s ints[0] %d\n",
3771 str ? str:"NULL", ints ? ints[0]:0));
3772
3773 /* read irq[] from ints[] */
3774 if (ints) {
3775 argc = ints[0];
3776 if (argc > 0) {
3777 if (argc > MAXHA)
3778 argc = MAXHA;
3779 for (i = 0; i < argc; ++i)
3780 irq[i] = ints[i+1];
3781 }
3782 }
3783
3784 /* analyse string */
3785 argv = str;
3786 while (argv && (cur_str = strchr(argv, ':'))) {
3787 int val = 0, c = *++cur_str;
3788
3789 if (c == 'n' || c == 'N')
3790 val = 0;
3791 else if (c == 'y' || c == 'Y')
3792 val = 1;
3793 else
3794 val = (int)simple_strtoul(cur_str, NULL, 0);
3795
3796 if (!strncmp(argv, "disable:", 8))
3797 disable = val;
3798 else if (!strncmp(argv, "reserve_mode:", 13))
3799 reserve_mode = val;
3800 else if (!strncmp(argv, "reverse_scan:", 13))
3801 reverse_scan = val;
3802 else if (!strncmp(argv, "hdr_channel:", 12))
3803 hdr_channel = val;
3804 else if (!strncmp(argv, "max_ids:", 8))
3805 max_ids = val;
3806 else if (!strncmp(argv, "rescan:", 7))
3807 rescan = val;
3808 else if (!strncmp(argv, "shared_access:", 14))
3809 shared_access = val;
3810 else if (!strncmp(argv, "probe_eisa_isa:", 15))
3811 probe_eisa_isa = val;
3812 else if (!strncmp(argv, "reserve_list:", 13)) {
3813 reserve_list[0] = val;
3814 for (i = 1; i < MAX_RES_ARGS; i++) {
3815 cur_str = strchr(cur_str, ',');
3816 if (!cur_str)
3817 break;
3818 if (!isdigit((int)*++cur_str)) {
3819 --cur_str;
3820 break;
3821 }
3822 reserve_list[i] =
3823 (int)simple_strtoul(cur_str, NULL, 0);
3824 }
3825 if (!cur_str)
3826 break;
3827 argv = ++cur_str;
3828 continue;
3829 }
3830
3831 if ((argv = strchr(argv, ',')))
3832 ++argv;
3833 }
3834 }
3835
3836 int __init option_setup(char *str)
3837 {
3838 int ints[MAXHA];
3839 char *cur = str;
3840 int i = 1;
3841
3842 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
3843
3844 while (cur && isdigit(*cur) && i <= MAXHA) {
3845 ints[i++] = simple_strtoul(cur, NULL, 0);
3846 if ((cur = strchr(cur, ',')) != NULL) cur++;
3847 }
3848
3849 ints[0] = i - 1;
3850 internal_setup(cur, ints);
3851 return 1;
3852 }
3853
3854 static const char *gdth_ctr_name(gdth_ha_str *ha)
3855 {
3856 TRACE2(("gdth_ctr_name()\n"));
3857
3858 if (ha->type == GDT_EISA) {
3859 switch (ha->stype) {
3860 case GDT3_ID:
3861 return("GDT3000/3020");
3862 case GDT3A_ID:
3863 return("GDT3000A/3020A/3050A");
3864 case GDT3B_ID:
3865 return("GDT3000B/3010A");
3866 }
3867 } else if (ha->type == GDT_ISA) {
3868 return("GDT2000/2020");
3869 } else if (ha->type == GDT_PCI) {
3870 switch (ha->pdev->device) {
3871 case PCI_DEVICE_ID_VORTEX_GDT60x0:
3872 return("GDT6000/6020/6050");
3873 case PCI_DEVICE_ID_VORTEX_GDT6000B:
3874 return("GDT6000B/6010");
3875 }
3876 }
3877 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
3878
3879 return("");
3880 }
3881
3882 static const char *gdth_info(struct Scsi_Host *shp)
3883 {
3884 gdth_ha_str *ha = shost_priv(shp);
3885
3886 TRACE2(("gdth_info()\n"));
3887 return ((const char *)ha->binfo.type_string);
3888 }
3889
3890 static enum blk_eh_timer_return gdth_timed_out(struct scsi_cmnd *scp)
3891 {
3892 gdth_ha_str *ha = shost_priv(scp->device->host);
3893 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
3894 unchar b, t;
3895 ulong flags;
3896 enum blk_eh_timer_return retval = BLK_EH_NOT_HANDLED;
3897
3898 TRACE(("%s() cmd 0x%x\n", scp->cmnd[0], __func__));
3899 b = scp->device->channel;
3900 t = scp->device->id;
3901
3902 /*
3903 * We don't really honor the command timeout, but we try to
3904 * honor 6 times of the actual command timeout! So reset the
3905 * timer if this is less than 6th timeout on this command!
3906 */
3907 if (++cmndinfo->timeout_count < 6)
3908 retval = BLK_EH_RESET_TIMER;
3909
3910 /* Reset the timeout if it is locked IO */
3911 spin_lock_irqsave(&ha->smp_lock, flags);
3912 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha, b)].lock) ||
3913 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
3914 TRACE2(("%s(): locked IO, reset timeout\n", __func__));
3915 retval = BLK_EH_RESET_TIMER;
3916 }
3917 spin_unlock_irqrestore(&ha->smp_lock, flags);
3918
3919 return retval;
3920 }
3921
3922
3923 static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
3924 {
3925 gdth_ha_str *ha = shost_priv(scp->device->host);
3926 int i;
3927 ulong flags;
3928 Scsi_Cmnd *cmnd;
3929 unchar b;
3930
3931 TRACE2(("gdth_eh_bus_reset()\n"));
3932
3933 b = scp->device->channel;
3934
3935 /* clear command tab */
3936 spin_lock_irqsave(&ha->smp_lock, flags);
3937 for (i = 0; i < GDTH_MAXCMDS; ++i) {
3938 cmnd = ha->cmd_tab[i].cmnd;
3939 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
3940 ha->cmd_tab[i].cmnd = UNUSED_CMND;
3941 }
3942 spin_unlock_irqrestore(&ha->smp_lock, flags);
3943
3944 if (b == ha->virt_bus) {
3945 /* host drives */
3946 for (i = 0; i < MAX_HDRIVES; ++i) {
3947 if (ha->hdr[i].present) {
3948 spin_lock_irqsave(&ha->smp_lock, flags);
3949 gdth_polling = TRUE;
3950 while (gdth_test_busy(ha))
3951 gdth_delay(0);
3952 if (gdth_internal_cmd(ha, CACHESERVICE,
3953 GDT_CLUST_RESET, i, 0, 0))
3954 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
3955 gdth_polling = FALSE;
3956 spin_unlock_irqrestore(&ha->smp_lock, flags);
3957 }
3958 }
3959 } else {
3960 /* raw devices */
3961 spin_lock_irqsave(&ha->smp_lock, flags);
3962 for (i = 0; i < MAXID; ++i)
3963 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
3964 gdth_polling = TRUE;
3965 while (gdth_test_busy(ha))
3966 gdth_delay(0);
3967 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
3968 BUS_L2P(ha,b), 0, 0);
3969 gdth_polling = FALSE;
3970 spin_unlock_irqrestore(&ha->smp_lock, flags);
3971 }
3972 return SUCCESS;
3973 }
3974
3975 static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
3976 {
3977 unchar b, t;
3978 gdth_ha_str *ha = shost_priv(sdev->host);
3979 struct scsi_device *sd;
3980 unsigned capacity;
3981
3982 sd = sdev;
3983 capacity = cap;
3984 b = sd->channel;
3985 t = sd->id;
3986 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
3987
3988 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
3989 /* raw device or host drive without mapping information */
3990 TRACE2(("Evaluate mapping\n"));
3991 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
3992 } else {
3993 ip[0] = ha->hdr[t].heads;
3994 ip[1] = ha->hdr[t].secs;
3995 ip[2] = capacity / ip[0] / ip[1];
3996 }
3997
3998 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
3999 ip[0],ip[1],ip[2]));
4000 return 0;
4001 }
4002
4003
4004 static int gdth_queuecommand(struct scsi_cmnd *scp,
4005 void (*done)(struct scsi_cmnd *))
4006 {
4007 gdth_ha_str *ha = shost_priv(scp->device->host);
4008 struct gdth_cmndinfo *cmndinfo;
4009
4010 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4011
4012 cmndinfo = gdth_get_cmndinfo(ha);
4013 BUG_ON(!cmndinfo);
4014
4015 scp->scsi_done = done;
4016 cmndinfo->timeout_count = 0;
4017 cmndinfo->priority = DEFAULT_PRI;
4018
4019 return __gdth_queuecommand(ha, scp, cmndinfo);
4020 }
4021
4022 static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
4023 struct gdth_cmndinfo *cmndinfo)
4024 {
4025 scp->host_scribble = (unsigned char *)cmndinfo;
4026 cmndinfo->wait_for_completion = 1;
4027 cmndinfo->phase = -1;
4028 cmndinfo->OpCode = -1;
4029
4030 #ifdef GDTH_STATISTICS
4031 ++act_ios;
4032 #endif
4033
4034 gdth_putq(ha, scp, cmndinfo->priority);
4035 gdth_next(ha);
4036 return 0;
4037 }
4038
4039
4040 static int gdth_open(struct inode *inode, struct file *filep)
4041 {
4042 gdth_ha_str *ha;
4043
4044 lock_kernel();
4045 list_for_each_entry(ha, &gdth_instances, list) {
4046 if (!ha->sdev)
4047 ha->sdev = scsi_get_host_dev(ha->shost);
4048 }
4049 unlock_kernel();
4050
4051 TRACE(("gdth_open()\n"));
4052 return 0;
4053 }
4054
4055 static int gdth_close(struct inode *inode, struct file *filep)
4056 {
4057 TRACE(("gdth_close()\n"));
4058 return 0;
4059 }
4060
4061 static int ioc_event(void __user *arg)
4062 {
4063 gdth_ioctl_event evt;
4064 gdth_ha_str *ha;
4065 ulong flags;
4066
4067 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
4068 return -EFAULT;
4069 ha = gdth_find_ha(evt.ionode);
4070 if (!ha)
4071 return -EFAULT;
4072
4073 if (evt.erase == 0xff) {
4074 if (evt.event.event_source == ES_TEST)
4075 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4076 else if (evt.event.event_source == ES_DRIVER)
4077 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4078 else if (evt.event.event_source == ES_SYNC)
4079 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4080 else
4081 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
4082 spin_lock_irqsave(&ha->smp_lock, flags);
4083 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
4084 &evt.event.event_data);
4085 spin_unlock_irqrestore(&ha->smp_lock, flags);
4086 } else if (evt.erase == 0xfe) {
4087 gdth_clear_events();
4088 } else if (evt.erase == 0) {
4089 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
4090 } else {
4091 gdth_readapp_event(ha, evt.erase, &evt.event);
4092 }
4093 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
4094 return -EFAULT;
4095 return 0;
4096 }
4097
4098 static int ioc_lockdrv(void __user *arg)
4099 {
4100 gdth_ioctl_lockdrv ldrv;
4101 unchar i, j;
4102 ulong flags;
4103 gdth_ha_str *ha;
4104
4105 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
4106 return -EFAULT;
4107 ha = gdth_find_ha(ldrv.ionode);
4108 if (!ha)
4109 return -EFAULT;
4110
4111 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
4112 j = ldrv.drives[i];
4113 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
4114 continue;
4115 if (ldrv.lock) {
4116 spin_lock_irqsave(&ha->smp_lock, flags);
4117 ha->hdr[j].lock = 1;
4118 spin_unlock_irqrestore(&ha->smp_lock, flags);
4119 gdth_wait_completion(ha, ha->bus_cnt, j);
4120 } else {
4121 spin_lock_irqsave(&ha->smp_lock, flags);
4122 ha->hdr[j].lock = 0;
4123 spin_unlock_irqrestore(&ha->smp_lock, flags);
4124 gdth_next(ha);
4125 }
4126 }
4127 return 0;
4128 }
4129
4130 static int ioc_resetdrv(void __user *arg, char *cmnd)
4131 {
4132 gdth_ioctl_reset res;
4133 gdth_cmd_str cmd;
4134 gdth_ha_str *ha;
4135 int rval;
4136
4137 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
4138 res.number >= MAX_HDRIVES)
4139 return -EFAULT;
4140 ha = gdth_find_ha(res.ionode);
4141 if (!ha)
4142 return -EFAULT;
4143
4144 if (!ha->hdr[res.number].present)
4145 return 0;
4146 memset(&cmd, 0, sizeof(gdth_cmd_str));
4147 cmd.Service = CACHESERVICE;
4148 cmd.OpCode = GDT_CLUST_RESET;
4149 if (ha->cache_feat & GDT_64BIT)
4150 cmd.u.cache64.DeviceNo = res.number;
4151 else
4152 cmd.u.cache.DeviceNo = res.number;
4153
4154 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
4155 if (rval < 0)
4156 return rval;
4157 res.status = rval;
4158
4159 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
4160 return -EFAULT;
4161 return 0;
4162 }
4163
4164 static int ioc_general(void __user *arg, char *cmnd)
4165 {
4166 gdth_ioctl_general gen;
4167 char *buf = NULL;
4168 ulong64 paddr;
4169 gdth_ha_str *ha;
4170 int rval;
4171
4172 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
4173 return -EFAULT;
4174 ha = gdth_find_ha(gen.ionode);
4175 if (!ha)
4176 return -EFAULT;
4177 if (gen.data_len + gen.sense_len != 0) {
4178 if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
4179 FALSE, &paddr)))
4180 return -EFAULT;
4181 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4182 gen.data_len + gen.sense_len)) {
4183 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4184 return -EFAULT;
4185 }
4186
4187 if (gen.command.OpCode == GDT_IOCTL) {
4188 gen.command.u.ioctl.p_param = paddr;
4189 } else if (gen.command.Service == CACHESERVICE) {
4190 if (ha->cache_feat & GDT_64BIT) {
4191 /* copy elements from 32-bit IOCTL structure */
4192 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
4193 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
4194 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
4195 /* addresses */
4196 if (ha->cache_feat & SCATTER_GATHER) {
4197 gen.command.u.cache64.DestAddr = (ulong64)-1;
4198 gen.command.u.cache64.sg_canz = 1;
4199 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
4200 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
4201 gen.command.u.cache64.sg_lst[1].sg_len = 0;
4202 } else {
4203 gen.command.u.cache64.DestAddr = paddr;
4204 gen.command.u.cache64.sg_canz = 0;
4205 }
4206 } else {
4207 if (ha->cache_feat & SCATTER_GATHER) {
4208 gen.command.u.cache.DestAddr = 0xffffffff;
4209 gen.command.u.cache.sg_canz = 1;
4210 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
4211 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
4212 gen.command.u.cache.sg_lst[1].sg_len = 0;
4213 } else {
4214 gen.command.u.cache.DestAddr = paddr;
4215 gen.command.u.cache.sg_canz = 0;
4216 }
4217 }
4218 } else if (gen.command.Service == SCSIRAWSERVICE) {
4219 if (ha->raw_feat & GDT_64BIT) {
4220 /* copy elements from 32-bit IOCTL structure */
4221 char cmd[16];
4222 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
4223 gen.command.u.raw64.bus = gen.command.u.raw.bus;
4224 gen.command.u.raw64.lun = gen.command.u.raw.lun;
4225 gen.command.u.raw64.target = gen.command.u.raw.target;
4226 memcpy(cmd, gen.command.u.raw.cmd, 16);
4227 memcpy(gen.command.u.raw64.cmd, cmd, 16);
4228 gen.command.u.raw64.clen = gen.command.u.raw.clen;
4229 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
4230 gen.command.u.raw64.direction = gen.command.u.raw.direction;
4231 /* addresses */
4232 if (ha->raw_feat & SCATTER_GATHER) {
4233 gen.command.u.raw64.sdata = (ulong64)-1;
4234 gen.command.u.raw64.sg_ranz = 1;
4235 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
4236 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
4237 gen.command.u.raw64.sg_lst[1].sg_len = 0;
4238 } else {
4239 gen.command.u.raw64.sdata = paddr;
4240 gen.command.u.raw64.sg_ranz = 0;
4241 }
4242 gen.command.u.raw64.sense_data = paddr + gen.data_len;
4243 } else {
4244 if (ha->raw_feat & SCATTER_GATHER) {
4245 gen.command.u.raw.sdata = 0xffffffff;
4246 gen.command.u.raw.sg_ranz = 1;
4247 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
4248 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
4249 gen.command.u.raw.sg_lst[1].sg_len = 0;
4250 } else {
4251 gen.command.u.raw.sdata = paddr;
4252 gen.command.u.raw.sg_ranz = 0;
4253 }
4254 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
4255 }
4256 } else {
4257 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4258 return -EFAULT;
4259 }
4260 }
4261
4262 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
4263 if (rval < 0)
4264 return rval;
4265 gen.status = rval;
4266
4267 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
4268 gen.data_len + gen.sense_len)) {
4269 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4270 return -EFAULT;
4271 }
4272 if (copy_to_user(arg, &gen,
4273 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
4274 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4275 return -EFAULT;
4276 }
4277 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4278 return 0;
4279 }
4280
4281 static int ioc_hdrlist(void __user *arg, char *cmnd)
4282 {
4283 gdth_ioctl_rescan *rsc;
4284 gdth_cmd_str *cmd;
4285 gdth_ha_str *ha;
4286 unchar i;
4287 int rc = -ENOMEM;
4288 u32 cluster_type = 0;
4289
4290 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4291 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4292 if (!rsc || !cmd)
4293 goto free_fail;
4294
4295 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4296 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
4297 rc = -EFAULT;
4298 goto free_fail;
4299 }
4300 memset(cmd, 0, sizeof(gdth_cmd_str));
4301
4302 for (i = 0; i < MAX_HDRIVES; ++i) {
4303 if (!ha->hdr[i].present) {
4304 rsc->hdr_list[i].bus = 0xff;
4305 continue;
4306 }
4307 rsc->hdr_list[i].bus = ha->virt_bus;
4308 rsc->hdr_list[i].target = i;
4309 rsc->hdr_list[i].lun = 0;
4310 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4311 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
4312 cmd->Service = CACHESERVICE;
4313 cmd->OpCode = GDT_CLUST_INFO;
4314 if (ha->cache_feat & GDT_64BIT)
4315 cmd->u.cache64.DeviceNo = i;
4316 else
4317 cmd->u.cache.DeviceNo = i;
4318 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
4319 rsc->hdr_list[i].cluster_type = cluster_type;
4320 }
4321 }
4322
4323 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4324 rc = -EFAULT;
4325 else
4326 rc = 0;
4327
4328 free_fail:
4329 kfree(rsc);
4330 kfree(cmd);
4331 return rc;
4332 }
4333
4334 static int ioc_rescan(void __user *arg, char *cmnd)
4335 {
4336 gdth_ioctl_rescan *rsc;
4337 gdth_cmd_str *cmd;
4338 ushort i, status, hdr_cnt;
4339 ulong32 info;
4340 int cyls, hds, secs;
4341 int rc = -ENOMEM;
4342 ulong flags;
4343 gdth_ha_str *ha;
4344
4345 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4346 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4347 if (!cmd || !rsc)
4348 goto free_fail;
4349
4350 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4351 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
4352 rc = -EFAULT;
4353 goto free_fail;
4354 }
4355 memset(cmd, 0, sizeof(gdth_cmd_str));
4356
4357 if (rsc->flag == 0) {
4358 /* old method: re-init. cache service */
4359 cmd->Service = CACHESERVICE;
4360 if (ha->cache_feat & GDT_64BIT) {
4361 cmd->OpCode = GDT_X_INIT_HOST;
4362 cmd->u.cache64.DeviceNo = LINUX_OS;
4363 } else {
4364 cmd->OpCode = GDT_INIT;
4365 cmd->u.cache.DeviceNo = LINUX_OS;
4366 }
4367
4368 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4369 i = 0;
4370 hdr_cnt = (status == S_OK ? (ushort)info : 0);
4371 } else {
4372 i = rsc->hdr_no;
4373 hdr_cnt = i + 1;
4374 }
4375
4376 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
4377 cmd->Service = CACHESERVICE;
4378 cmd->OpCode = GDT_INFO;
4379 if (ha->cache_feat & GDT_64BIT)
4380 cmd->u.cache64.DeviceNo = i;
4381 else
4382 cmd->u.cache.DeviceNo = i;
4383
4384 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4385
4386 spin_lock_irqsave(&ha->smp_lock, flags);
4387 rsc->hdr_list[i].bus = ha->virt_bus;
4388 rsc->hdr_list[i].target = i;
4389 rsc->hdr_list[i].lun = 0;
4390 if (status != S_OK) {
4391 ha->hdr[i].present = FALSE;
4392 } else {
4393 ha->hdr[i].present = TRUE;
4394 ha->hdr[i].size = info;
4395 /* evaluate mapping */
4396 ha->hdr[i].size &= ~SECS32;
4397 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
4398 ha->hdr[i].heads = hds;
4399 ha->hdr[i].secs = secs;
4400 /* round size */
4401 ha->hdr[i].size = cyls * hds * secs;
4402 }
4403 spin_unlock_irqrestore(&ha->smp_lock, flags);
4404 if (status != S_OK)
4405 continue;
4406
4407 /* extended info, if GDT_64BIT, for drives > 2 TB */
4408 /* but we need ha->info2, not yet stored in scp->SCp */
4409
4410 /* devtype, cluster info, R/W attribs */
4411 cmd->Service = CACHESERVICE;
4412 cmd->OpCode = GDT_DEVTYPE;
4413 if (ha->cache_feat & GDT_64BIT)
4414 cmd->u.cache64.DeviceNo = i;
4415 else
4416 cmd->u.cache.DeviceNo = i;
4417
4418 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4419
4420 spin_lock_irqsave(&ha->smp_lock, flags);
4421 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
4422 spin_unlock_irqrestore(&ha->smp_lock, flags);
4423
4424 cmd->Service = CACHESERVICE;
4425 cmd->OpCode = GDT_CLUST_INFO;
4426 if (ha->cache_feat & GDT_64BIT)
4427 cmd->u.cache64.DeviceNo = i;
4428 else
4429 cmd->u.cache.DeviceNo = i;
4430
4431 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4432
4433 spin_lock_irqsave(&ha->smp_lock, flags);
4434 ha->hdr[i].cluster_type =
4435 ((status == S_OK && !shared_access) ? (ushort)info : 0);
4436 spin_unlock_irqrestore(&ha->smp_lock, flags);
4437 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4438
4439 cmd->Service = CACHESERVICE;
4440 cmd->OpCode = GDT_RW_ATTRIBS;
4441 if (ha->cache_feat & GDT_64BIT)
4442 cmd->u.cache64.DeviceNo = i;
4443 else
4444 cmd->u.cache.DeviceNo = i;
4445
4446 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4447
4448 spin_lock_irqsave(&ha->smp_lock, flags);
4449 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
4450 spin_unlock_irqrestore(&ha->smp_lock, flags);
4451 }
4452
4453 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4454 rc = -EFAULT;
4455 else
4456 rc = 0;
4457
4458 free_fail:
4459 kfree(rsc);
4460 kfree(cmd);
4461 return rc;
4462 }
4463
4464 static int gdth_ioctl(struct inode *inode, struct file *filep,
4465 unsigned int cmd, unsigned long arg)
4466 {
4467 gdth_ha_str *ha;
4468 Scsi_Cmnd *scp;
4469 ulong flags;
4470 char cmnd[MAX_COMMAND_SIZE];
4471 void __user *argp = (void __user *)arg;
4472
4473 memset(cmnd, 0xff, 12);
4474
4475 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
4476
4477 switch (cmd) {
4478 case GDTIOCTL_CTRCNT:
4479 {
4480 int cnt = gdth_ctr_count;
4481 if (put_user(cnt, (int __user *)argp))
4482 return -EFAULT;
4483 break;
4484 }
4485
4486 case GDTIOCTL_DRVERS:
4487 {
4488 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
4489 if (put_user(ver, (int __user *)argp))
4490 return -EFAULT;
4491 break;
4492 }
4493
4494 case GDTIOCTL_OSVERS:
4495 {
4496 gdth_ioctl_osvers osv;
4497
4498 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
4499 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
4500 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
4501 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
4502 return -EFAULT;
4503 break;
4504 }
4505
4506 case GDTIOCTL_CTRTYPE:
4507 {
4508 gdth_ioctl_ctrtype ctrt;
4509
4510 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
4511 (NULL == (ha = gdth_find_ha(ctrt.ionode))))
4512 return -EFAULT;
4513
4514 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
4515 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
4516 } else {
4517 if (ha->type != GDT_PCIMPR) {
4518 ctrt.type = (unchar)((ha->stype<<4) + 6);
4519 } else {
4520 ctrt.type =
4521 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
4522 if (ha->stype >= 0x300)
4523 ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
4524 else
4525 ctrt.ext_type = 0x6000 | ha->stype;
4526 }
4527 ctrt.device_id = ha->pdev->device;
4528 ctrt.sub_device_id = ha->pdev->subsystem_device;
4529 }
4530 ctrt.info = ha->brd_phys;
4531 ctrt.oem_id = ha->oem_id;
4532 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
4533 return -EFAULT;
4534 break;
4535 }
4536
4537 case GDTIOCTL_GENERAL:
4538 return ioc_general(argp, cmnd);
4539
4540 case GDTIOCTL_EVENT:
4541 return ioc_event(argp);
4542
4543 case GDTIOCTL_LOCKDRV:
4544 return ioc_lockdrv(argp);
4545
4546 case GDTIOCTL_LOCKCHN:
4547 {
4548 gdth_ioctl_lockchn lchn;
4549 unchar i, j;
4550
4551 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
4552 (NULL == (ha = gdth_find_ha(lchn.ionode))))
4553 return -EFAULT;
4554
4555 i = lchn.channel;
4556 if (i < ha->bus_cnt) {
4557 if (lchn.lock) {
4558 spin_lock_irqsave(&ha->smp_lock, flags);
4559 ha->raw[i].lock = 1;
4560 spin_unlock_irqrestore(&ha->smp_lock, flags);
4561 for (j = 0; j < ha->tid_cnt; ++j)
4562 gdth_wait_completion(ha, i, j);
4563 } else {
4564 spin_lock_irqsave(&ha->smp_lock, flags);
4565 ha->raw[i].lock = 0;
4566 spin_unlock_irqrestore(&ha->smp_lock, flags);
4567 for (j = 0; j < ha->tid_cnt; ++j)
4568 gdth_next(ha);
4569 }
4570 }
4571 break;
4572 }
4573
4574 case GDTIOCTL_RESCAN:
4575 return ioc_rescan(argp, cmnd);
4576
4577 case GDTIOCTL_HDRLIST:
4578 return ioc_hdrlist(argp, cmnd);
4579
4580 case GDTIOCTL_RESET_BUS:
4581 {
4582 gdth_ioctl_reset res;
4583 int rval;
4584
4585 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
4586 (NULL == (ha = gdth_find_ha(res.ionode))))
4587 return -EFAULT;
4588
4589 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
4590 if (!scp)
4591 return -ENOMEM;
4592 scp->device = ha->sdev;
4593 scp->cmd_len = 12;
4594 scp->device->channel = res.number;
4595 rval = gdth_eh_bus_reset(scp);
4596 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
4597 kfree(scp);
4598
4599 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
4600 return -EFAULT;
4601 break;
4602 }
4603
4604 case GDTIOCTL_RESET_DRV:
4605 return ioc_resetdrv(argp, cmnd);
4606
4607 default:
4608 break;
4609 }
4610 return 0;
4611 }
4612
4613
4614 /* flush routine */
4615 static void gdth_flush(gdth_ha_str *ha)
4616 {
4617 int i;
4618 gdth_cmd_str gdtcmd;
4619 char cmnd[MAX_COMMAND_SIZE];
4620 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4621
4622 TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
4623
4624 for (i = 0; i < MAX_HDRIVES; ++i) {
4625 if (ha->hdr[i].present) {
4626 gdtcmd.BoardNode = LOCALBOARD;
4627 gdtcmd.Service = CACHESERVICE;
4628 gdtcmd.OpCode = GDT_FLUSH;
4629 if (ha->cache_feat & GDT_64BIT) {
4630 gdtcmd.u.cache64.DeviceNo = i;
4631 gdtcmd.u.cache64.BlockNo = 1;
4632 gdtcmd.u.cache64.sg_canz = 0;
4633 } else {
4634 gdtcmd.u.cache.DeviceNo = i;
4635 gdtcmd.u.cache.BlockNo = 1;
4636 gdtcmd.u.cache.sg_canz = 0;
4637 }
4638 TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
4639
4640 gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
4641 }
4642 }
4643 }
4644
4645 /* configure lun */
4646 static int gdth_slave_configure(struct scsi_device *sdev)
4647 {
4648 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
4649 sdev->skip_ms_page_3f = 1;
4650 sdev->skip_ms_page_8 = 1;
4651 return 0;
4652 }
4653
4654 static struct scsi_host_template gdth_template = {
4655 .name = "GDT SCSI Disk Array Controller",
4656 .info = gdth_info,
4657 .queuecommand = gdth_queuecommand,
4658 .eh_bus_reset_handler = gdth_eh_bus_reset,
4659 .slave_configure = gdth_slave_configure,
4660 .bios_param = gdth_bios_param,
4661 .proc_info = gdth_proc_info,
4662 .eh_timed_out = gdth_timed_out,
4663 .proc_name = "gdth",
4664 .can_queue = GDTH_MAXCMDS,
4665 .this_id = -1,
4666 .sg_tablesize = GDTH_MAXSG,
4667 .cmd_per_lun = GDTH_MAXC_P_L,
4668 .unchecked_isa_dma = 1,
4669 .use_clustering = ENABLE_CLUSTERING,
4670 };
4671
4672 #ifdef CONFIG_ISA
4673 static int __init gdth_isa_probe_one(ulong32 isa_bios)
4674 {
4675 struct Scsi_Host *shp;
4676 gdth_ha_str *ha;
4677 dma_addr_t scratch_dma_handle = 0;
4678 int error, i;
4679
4680 if (!gdth_search_isa(isa_bios))
4681 return -ENXIO;
4682
4683 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4684 if (!shp)
4685 return -ENOMEM;
4686 ha = shost_priv(shp);
4687
4688 error = -ENODEV;
4689 if (!gdth_init_isa(isa_bios,ha))
4690 goto out_host_put;
4691
4692 /* controller found and initialized */
4693 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4694 isa_bios, ha->irq, ha->drq);
4695
4696 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4697 if (error) {
4698 printk("GDT-ISA: Unable to allocate IRQ\n");
4699 goto out_host_put;
4700 }
4701
4702 error = request_dma(ha->drq, "gdth");
4703 if (error) {
4704 printk("GDT-ISA: Unable to allocate DMA channel\n");
4705 goto out_free_irq;
4706 }
4707
4708 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4709 enable_dma(ha->drq);
4710 shp->unchecked_isa_dma = 1;
4711 shp->irq = ha->irq;
4712 shp->dma_channel = ha->drq;
4713
4714 ha->hanum = gdth_ctr_count++;
4715 ha->shost = shp;
4716
4717 ha->pccb = &ha->cmdext;
4718 ha->ccb_phys = 0L;
4719 ha->pdev = NULL;
4720
4721 error = -ENOMEM;
4722
4723 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4724 &scratch_dma_handle);
4725 if (!ha->pscratch)
4726 goto out_dec_counters;
4727 ha->scratch_phys = scratch_dma_handle;
4728
4729 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4730 &scratch_dma_handle);
4731 if (!ha->pmsg)
4732 goto out_free_pscratch;
4733 ha->msg_phys = scratch_dma_handle;
4734
4735 #ifdef INT_COAL
4736 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4737 sizeof(gdth_coal_status) * MAXOFFSETS,
4738 &scratch_dma_handle);
4739 if (!ha->coal_stat)
4740 goto out_free_pmsg;
4741 ha->coal_stat_phys = scratch_dma_handle;
4742 #endif
4743
4744 ha->scratch_busy = FALSE;
4745 ha->req_first = NULL;
4746 ha->tid_cnt = MAX_HDRIVES;
4747 if (max_ids > 0 && max_ids < ha->tid_cnt)
4748 ha->tid_cnt = max_ids;
4749 for (i = 0; i < GDTH_MAXCMDS; ++i)
4750 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4751 ha->scan_mode = rescan ? 0x10 : 0;
4752
4753 error = -ENODEV;
4754 if (!gdth_search_drives(ha)) {
4755 printk("GDT-ISA: Error during device scan\n");
4756 goto out_free_coal_stat;
4757 }
4758
4759 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4760 hdr_channel = ha->bus_cnt;
4761 ha->virt_bus = hdr_channel;
4762
4763 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4764 shp->max_cmd_len = 16;
4765
4766 shp->max_id = ha->tid_cnt;
4767 shp->max_lun = MAXLUN;
4768 shp->max_channel = ha->bus_cnt;
4769
4770 spin_lock_init(&ha->smp_lock);
4771 gdth_enable_int(ha);
4772
4773 error = scsi_add_host(shp, NULL);
4774 if (error)
4775 goto out_free_coal_stat;
4776 list_add_tail(&ha->list, &gdth_instances);
4777 gdth_timer_init();
4778
4779 scsi_scan_host(shp);
4780
4781 return 0;
4782
4783 out_free_coal_stat:
4784 #ifdef INT_COAL
4785 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4786 ha->coal_stat, ha->coal_stat_phys);
4787 out_free_pmsg:
4788 #endif
4789 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4790 ha->pmsg, ha->msg_phys);
4791 out_free_pscratch:
4792 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4793 ha->pscratch, ha->scratch_phys);
4794 out_dec_counters:
4795 gdth_ctr_count--;
4796 out_free_irq:
4797 free_irq(ha->irq, ha);
4798 out_host_put:
4799 scsi_host_put(shp);
4800 return error;
4801 }
4802 #endif /* CONFIG_ISA */
4803
4804 #ifdef CONFIG_EISA
4805 static int __init gdth_eisa_probe_one(ushort eisa_slot)
4806 {
4807 struct Scsi_Host *shp;
4808 gdth_ha_str *ha;
4809 dma_addr_t scratch_dma_handle = 0;
4810 int error, i;
4811
4812 if (!gdth_search_eisa(eisa_slot))
4813 return -ENXIO;
4814
4815 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4816 if (!shp)
4817 return -ENOMEM;
4818 ha = shost_priv(shp);
4819
4820 error = -ENODEV;
4821 if (!gdth_init_eisa(eisa_slot,ha))
4822 goto out_host_put;
4823
4824 /* controller found and initialized */
4825 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4826 eisa_slot >> 12, ha->irq);
4827
4828 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4829 if (error) {
4830 printk("GDT-EISA: Unable to allocate IRQ\n");
4831 goto out_host_put;
4832 }
4833
4834 shp->unchecked_isa_dma = 0;
4835 shp->irq = ha->irq;
4836 shp->dma_channel = 0xff;
4837
4838 ha->hanum = gdth_ctr_count++;
4839 ha->shost = shp;
4840
4841 TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
4842
4843 ha->pccb = &ha->cmdext;
4844 ha->ccb_phys = 0L;
4845
4846 error = -ENOMEM;
4847
4848 ha->pdev = NULL;
4849 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4850 &scratch_dma_handle);
4851 if (!ha->pscratch)
4852 goto out_free_irq;
4853 ha->scratch_phys = scratch_dma_handle;
4854
4855 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4856 &scratch_dma_handle);
4857 if (!ha->pmsg)
4858 goto out_free_pscratch;
4859 ha->msg_phys = scratch_dma_handle;
4860
4861 #ifdef INT_COAL
4862 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4863 sizeof(gdth_coal_status) * MAXOFFSETS,
4864 &scratch_dma_handle);
4865 if (!ha->coal_stat)
4866 goto out_free_pmsg;
4867 ha->coal_stat_phys = scratch_dma_handle;
4868 #endif
4869
4870 ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
4871 sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
4872 if (!ha->ccb_phys)
4873 goto out_free_coal_stat;
4874
4875 ha->scratch_busy = FALSE;
4876 ha->req_first = NULL;
4877 ha->tid_cnt = MAX_HDRIVES;
4878 if (max_ids > 0 && max_ids < ha->tid_cnt)
4879 ha->tid_cnt = max_ids;
4880 for (i = 0; i < GDTH_MAXCMDS; ++i)
4881 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4882 ha->scan_mode = rescan ? 0x10 : 0;
4883
4884 if (!gdth_search_drives(ha)) {
4885 printk("GDT-EISA: Error during device scan\n");
4886 error = -ENODEV;
4887 goto out_free_ccb_phys;
4888 }
4889
4890 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4891 hdr_channel = ha->bus_cnt;
4892 ha->virt_bus = hdr_channel;
4893
4894 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4895 shp->max_cmd_len = 16;
4896
4897 shp->max_id = ha->tid_cnt;
4898 shp->max_lun = MAXLUN;
4899 shp->max_channel = ha->bus_cnt;
4900
4901 spin_lock_init(&ha->smp_lock);
4902 gdth_enable_int(ha);
4903
4904 error = scsi_add_host(shp, NULL);
4905 if (error)
4906 goto out_free_coal_stat;
4907 list_add_tail(&ha->list, &gdth_instances);
4908 gdth_timer_init();
4909
4910 scsi_scan_host(shp);
4911
4912 return 0;
4913
4914 out_free_ccb_phys:
4915 pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
4916 PCI_DMA_BIDIRECTIONAL);
4917 out_free_coal_stat:
4918 #ifdef INT_COAL
4919 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4920 ha->coal_stat, ha->coal_stat_phys);
4921 out_free_pmsg:
4922 #endif
4923 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4924 ha->pmsg, ha->msg_phys);
4925 out_free_pscratch:
4926 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4927 ha->pscratch, ha->scratch_phys);
4928 out_free_irq:
4929 free_irq(ha->irq, ha);
4930 gdth_ctr_count--;
4931 out_host_put:
4932 scsi_host_put(shp);
4933 return error;
4934 }
4935 #endif /* CONFIG_EISA */
4936
4937 #ifdef CONFIG_PCI
4938 static int __devinit gdth_pci_probe_one(gdth_pci_str *pcistr,
4939 gdth_ha_str **ha_out)
4940 {
4941 struct Scsi_Host *shp;
4942 gdth_ha_str *ha;
4943 dma_addr_t scratch_dma_handle = 0;
4944 int error, i;
4945 struct pci_dev *pdev = pcistr->pdev;
4946
4947 *ha_out = NULL;
4948
4949 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4950 if (!shp)
4951 return -ENOMEM;
4952 ha = shost_priv(shp);
4953
4954 error = -ENODEV;
4955 if (!gdth_init_pci(pdev, pcistr, ha))
4956 goto out_host_put;
4957
4958 /* controller found and initialized */
4959 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
4960 pdev->bus->number,
4961 PCI_SLOT(pdev->devfn),
4962 ha->irq);
4963
4964 error = request_irq(ha->irq, gdth_interrupt,
4965 IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
4966 if (error) {
4967 printk("GDT-PCI: Unable to allocate IRQ\n");
4968 goto out_host_put;
4969 }
4970
4971 shp->unchecked_isa_dma = 0;
4972 shp->irq = ha->irq;
4973 shp->dma_channel = 0xff;
4974
4975 ha->hanum = gdth_ctr_count++;
4976 ha->shost = shp;
4977
4978 ha->pccb = &ha->cmdext;
4979 ha->ccb_phys = 0L;
4980
4981 error = -ENOMEM;
4982
4983 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4984 &scratch_dma_handle);
4985 if (!ha->pscratch)
4986 goto out_free_irq;
4987 ha->scratch_phys = scratch_dma_handle;
4988
4989 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4990 &scratch_dma_handle);
4991 if (!ha->pmsg)
4992 goto out_free_pscratch;
4993 ha->msg_phys = scratch_dma_handle;
4994
4995 #ifdef INT_COAL
4996 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4997 sizeof(gdth_coal_status) * MAXOFFSETS,
4998 &scratch_dma_handle);
4999 if (!ha->coal_stat)
5000 goto out_free_pmsg;
5001 ha->coal_stat_phys = scratch_dma_handle;
5002 #endif
5003
5004 ha->scratch_busy = FALSE;
5005 ha->req_first = NULL;
5006 ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
5007 if (max_ids > 0 && max_ids < ha->tid_cnt)
5008 ha->tid_cnt = max_ids;
5009 for (i = 0; i < GDTH_MAXCMDS; ++i)
5010 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5011 ha->scan_mode = rescan ? 0x10 : 0;
5012
5013 error = -ENODEV;
5014 if (!gdth_search_drives(ha)) {
5015 printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
5016 goto out_free_coal_stat;
5017 }
5018
5019 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5020 hdr_channel = ha->bus_cnt;
5021 ha->virt_bus = hdr_channel;
5022
5023 /* 64-bit DMA only supported from FW >= x.43 */
5024 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
5025 !ha->dma64_support) {
5026 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
5027 printk(KERN_WARNING "GDT-PCI %d: "
5028 "Unable to set 32-bit DMA\n", ha->hanum);
5029 goto out_free_coal_stat;
5030 }
5031 } else {
5032 shp->max_cmd_len = 16;
5033 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5034 printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
5035 } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
5036 printk(KERN_WARNING "GDT-PCI %d: "
5037 "Unable to set 64/32-bit DMA\n", ha->hanum);
5038 goto out_free_coal_stat;
5039 }
5040 }
5041
5042 shp->max_id = ha->tid_cnt;
5043 shp->max_lun = MAXLUN;
5044 shp->max_channel = ha->bus_cnt;
5045
5046 spin_lock_init(&ha->smp_lock);
5047 gdth_enable_int(ha);
5048
5049 error = scsi_add_host(shp, &pdev->dev);
5050 if (error)
5051 goto out_free_coal_stat;
5052 list_add_tail(&ha->list, &gdth_instances);
5053
5054 pci_set_drvdata(ha->pdev, ha);
5055 gdth_timer_init();
5056
5057 scsi_scan_host(shp);
5058
5059 *ha_out = ha;
5060
5061 return 0;
5062
5063 out_free_coal_stat:
5064 #ifdef INT_COAL
5065 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5066 ha->coal_stat, ha->coal_stat_phys);
5067 out_free_pmsg:
5068 #endif
5069 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5070 ha->pmsg, ha->msg_phys);
5071 out_free_pscratch:
5072 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5073 ha->pscratch, ha->scratch_phys);
5074 out_free_irq:
5075 free_irq(ha->irq, ha);
5076 gdth_ctr_count--;
5077 out_host_put:
5078 scsi_host_put(shp);
5079 return error;
5080 }
5081 #endif /* CONFIG_PCI */
5082
5083 static void gdth_remove_one(gdth_ha_str *ha)
5084 {
5085 struct Scsi_Host *shp = ha->shost;
5086
5087 TRACE2(("gdth_remove_one()\n"));
5088
5089 scsi_remove_host(shp);
5090
5091 gdth_flush(ha);
5092
5093 if (ha->sdev) {
5094 scsi_free_host_dev(ha->sdev);
5095 ha->sdev = NULL;
5096 }
5097
5098 if (shp->irq)
5099 free_irq(shp->irq,ha);
5100
5101 #ifdef CONFIG_ISA
5102 if (shp->dma_channel != 0xff)
5103 free_dma(shp->dma_channel);
5104 #endif
5105 #ifdef INT_COAL
5106 if (ha->coal_stat)
5107 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
5108 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
5109 #endif
5110 if (ha->pscratch)
5111 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5112 ha->pscratch, ha->scratch_phys);
5113 if (ha->pmsg)
5114 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5115 ha->pmsg, ha->msg_phys);
5116 if (ha->ccb_phys)
5117 pci_unmap_single(ha->pdev,ha->ccb_phys,
5118 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
5119
5120 scsi_host_put(shp);
5121 }
5122
5123 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
5124 {
5125 gdth_ha_str *ha;
5126
5127 TRACE2(("gdth_halt() event %d\n", (int)event));
5128 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5129 return NOTIFY_DONE;
5130
5131 list_for_each_entry(ha, &gdth_instances, list)
5132 gdth_flush(ha);
5133
5134 return NOTIFY_OK;
5135 }
5136
5137 static struct notifier_block gdth_notifier = {
5138 gdth_halt, NULL, 0
5139 };
5140
5141 static int __init gdth_init(void)
5142 {
5143 if (disable) {
5144 printk("GDT-HA: Controller driver disabled from"
5145 " command line !\n");
5146 return 0;
5147 }
5148
5149 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
5150 GDTH_VERSION_STR);
5151
5152 /* initializations */
5153 gdth_polling = TRUE;
5154 gdth_clear_events();
5155 init_timer(&gdth_timer);
5156
5157 /* As default we do not probe for EISA or ISA controllers */
5158 if (probe_eisa_isa) {
5159 /* scanning for controllers, at first: ISA controller */
5160 #ifdef CONFIG_ISA
5161 ulong32 isa_bios;
5162 for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
5163 isa_bios += 0x8000UL)
5164 gdth_isa_probe_one(isa_bios);
5165 #endif
5166 #ifdef CONFIG_EISA
5167 {
5168 ushort eisa_slot;
5169 for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
5170 eisa_slot += 0x1000)
5171 gdth_eisa_probe_one(eisa_slot);
5172 }
5173 #endif
5174 }
5175
5176 #ifdef CONFIG_PCI
5177 /* scanning for PCI controllers */
5178 if (pci_register_driver(&gdth_pci_driver)) {
5179 gdth_ha_str *ha;
5180
5181 list_for_each_entry(ha, &gdth_instances, list)
5182 gdth_remove_one(ha);
5183 return -ENODEV;
5184 }
5185 #endif /* CONFIG_PCI */
5186
5187 TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
5188
5189 major = register_chrdev(0,"gdth", &gdth_fops);
5190 register_reboot_notifier(&gdth_notifier);
5191 gdth_polling = FALSE;
5192 return 0;
5193 }
5194
5195 static void __exit gdth_exit(void)
5196 {
5197 gdth_ha_str *ha;
5198
5199 unregister_chrdev(major, "gdth");
5200 unregister_reboot_notifier(&gdth_notifier);
5201
5202 #ifdef GDTH_STATISTICS
5203 del_timer_sync(&gdth_timer);
5204 #endif
5205
5206 #ifdef CONFIG_PCI
5207 pci_unregister_driver(&gdth_pci_driver);
5208 #endif
5209
5210 list_for_each_entry(ha, &gdth_instances, list)
5211 gdth_remove_one(ha);
5212 }
5213
5214 module_init(gdth_init);
5215 module_exit(gdth_exit);
5216
5217 #ifndef MODULE
5218 __setup("gdth=", option_setup);
5219 #endif
Support for the Chinese Samsung S3C2440 based development boards