1 /* $Id: vac-ops.h,v 1.13 1998/01/30 10:59:59 jj Exp $ */
2 #ifndef _SPARC_VAC_OPS_H
3 #define _SPARC_VAC_OPS_H
5 /* vac-ops.h: Inline assembly routines to do operations on the Sparc
6 * VAC (virtual address cache) for the sun4c.
8 * Copyright (C) 1994, David S. Miller (davem@caip.rutgers.edu)
11 #include <asm/sysen.h>
12 #include <asm/contregs.h>
15 /* The SUN4C models have a virtually addressed write-through
18 * The cache tags are directly accessible through an ASI and
21 * ------------------------------------------------------------
22 * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ |
23 * ------------------------------------------------------------
24 * 31 25 24 22 21 20 19 18 16 15 2 1 0
26 * MBZ: These bits are either unused and/or reserved and should
27 * be written as zeroes.
29 * CONTEXT: Records the context to which this cache line belongs.
31 * WRITE: A copy of the writable bit from the mmu pte access bits.
33 * PRIV: A copy of the privileged bit from the pte access bits.
35 * VALID: If set, this line is valid, else invalid.
37 * TagID: Fourteen bits of tag ID.
39 * Every virtual address is seen by the cache like this:
41 * ----------------------------------------
42 * | RESV | TagID | LINE | BYTE-in-LINE |
43 * ----------------------------------------
44 * 31 30 29 16 15 4 3 0
46 * RESV: Unused/reserved.
48 * TagID: Used to match the Tag-ID in that vac tags.
50 * LINE: Which line within the cache
52 * BYTE-in-LINE: Which byte within the cache line.
56 #define S4CVACTAG_CID 0x01c00000
57 #define S4CVACTAG_W 0x00200000
58 #define S4CVACTAG_P 0x00100000
59 #define S4CVACTAG_V 0x00080000
60 #define S4CVACTAG_TID 0x0000fffc
62 /* Sun4c VAC Virtual Address */
63 /* These aren't used, why bother? (Anton) */
65 #define S4CVACVA_TID 0x3fff0000
66 #define S4CVACVA_LINE 0x0000fff0
67 #define S4CVACVA_BIL 0x0000000f
70 /* The indexing of cache lines creates a problem. Because the line
71 * field of a virtual address extends past the page offset within
72 * the virtual address it is possible to have what are called
73 * 'bad aliases' which will create inconsistencies. So we must make
74 * sure that within a context that if a physical page is mapped
75 * more than once, that 'extra' line bits are the same. If this is
76 * not the case, and thus is a 'bad alias' we must turn off the
77 * cacheable bit in the pte's of all such pages.
81 #define S4CVAC_BADBITS 0x0001e000
83 #define S4CVAC_BADBITS 0x0000f000
86 /* The following is true if vaddr1 and vaddr2 would cause
89 #define S4CVAC_BADALIAS(vaddr1, vaddr2) \
90 ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \
93 /* The following structure describes the characteristics of a sun4c
94 * VAC as probed from the prom during boot time.
96 struct sun4c_vac_props
{
97 unsigned int num_bytes
; /* Size of the cache */
98 unsigned int num_lines
; /* Number of cache lines */
99 unsigned int do_hwflushes
; /* Hardware flushing available? */
100 enum { VAC_NONE
, VAC_WRITE_THROUGH
,
101 VAC_WRITE_BACK
} type
; /* What type of VAC? */
102 unsigned int linesize
; /* Size of each line in bytes */
103 unsigned int log2lsize
; /* log2(linesize) */
104 unsigned int on
; /* VAC is enabled */
107 extern struct sun4c_vac_props sun4c_vacinfo
;
109 /* sun4c_enable_vac() enables the sun4c virtual address cache. */
110 static inline void sun4c_enable_vac(void)
112 __asm__
__volatile__("lduba [%0] %1, %%g1\n\t"
113 "or %%g1, %2, %%g1\n\t"
114 "stba %%g1, [%0] %1\n\t"
116 : "r" ((unsigned int) AC_SENABLE
),
117 "i" (ASI_CONTROL
), "i" (SENABLE_CACHE
)
119 sun4c_vacinfo
.on
= 1;
122 /* sun4c_disable_vac() disables the virtual address cache. */
123 static inline void sun4c_disable_vac(void)
125 __asm__
__volatile__("lduba [%0] %1, %%g1\n\t"
126 "andn %%g1, %2, %%g1\n\t"
127 "stba %%g1, [%0] %1\n\t"
129 : "r" ((unsigned int) AC_SENABLE
),
130 "i" (ASI_CONTROL
), "i" (SENABLE_CACHE
)
132 sun4c_vacinfo
.on
= 0;
135 #endif /* !(_SPARC_VAC_OPS_H) */