arch/x86/kernel/setup_64.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  */
   4
   5 /*
   6  * This file handles the architecture-dependent parts of initialization
   7  */
   8
   9 #include <linux/errno.h>
  10 #include <linux/sched.h>
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/stddef.h>
  14 #include <linux/unistd.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/slab.h>
  17 #include <linux/user.h>
  18 #include <linux/a.out.h>
  19 #include <linux/screen_info.h>
  20 #include <linux/ioport.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/initrd.h>
  24 #include <linux/highmem.h>
  25 #include <linux/bootmem.h>
  26 #include <linux/module.h>
  27 #include <asm/processor.h>
  28 #include <linux/console.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/crash_dump.h>
  31 #include <linux/root_dev.h>
  32 #include <linux/pci.h>
  33 #include <linux/acpi.h>
  34 #include <linux/kallsyms.h>
  35 #include <linux/edd.h>
  36 #include <linux/mmzone.h>
  37 #include <linux/kexec.h>
  38 #include <linux/cpufreq.h>
  39 #include <linux/dmi.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/ctype.h>
  42
  43 #include <asm/mtrr.h>
  44 #include <asm/uaccess.h>
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/smp.h>
  48 #include <asm/msr.h>
  49 #include <asm/desc.h>
  50 #include <video/edid.h>
  51 #include <asm/e820.h>
  52 #include <asm/dma.h>
  53 #include <asm/mpspec.h>
  54 #include <asm/mmu_context.h>
  55 #include <asm/proto.h>
  56 #include <asm/setup.h>
  57 #include <asm/mach_apic.h>
  58 #include <asm/numa.h>
  59 #include <asm/sections.h>
  60 #include <asm/dmi.h>
  61
  62 /*
  63  * Machine setup..
  64  */
  65
  66 struct cpuinfo_x86 boot_cpu_data __read_mostly;
  67 EXPORT_SYMBOL(boot_cpu_data);
  68
  69 unsigned long mmu_cr4_features;
  70
  71 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
  72 int bootloader_type;
  73
  74 unsigned long saved_video_mode;
  75
  76 int force_mwait __cpuinitdata;
  77
  78 /*
  79  * Early DMI memory
  80  */
  81 int dmi_alloc_index;
  82 char dmi_alloc_data[DMI_MAX_DATA];
  83
  84 /*
  85  * Setup options
  86  */
  87 struct screen_info screen_info;
  88 EXPORT_SYMBOL(screen_info);
  89 struct sys_desc_table_struct {
  90         unsigned short length;
  91         unsigned char table[0];
  92 };
  93
  94 struct edid_info edid_info;
  95 EXPORT_SYMBOL_GPL(edid_info);
  96
  97 extern int root_mountflags;
  98
  99 char __initdata command_line[COMMAND_LINE_SIZE];
 100
 101 struct resource standard_io_resources[] = {
 102         { .name = "dma1", .start = 0x00, .end = 0x1f,
 103                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 104         { .name = "pic1", .start = 0x20, .end = 0x21,
 105                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 106         { .name = "timer0", .start = 0x40, .end = 0x43,
 107                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 108         { .name = "timer1", .start = 0x50, .end = 0x53,
 109                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 110         { .name = "keyboard", .start = 0x60, .end = 0x6f,
 111                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 112         { .name = "dma page reg", .start = 0x80, .end = 0x8f,
 113                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 114         { .name = "pic2", .start = 0xa0, .end = 0xa1,
 115                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 116         { .name = "dma2", .start = 0xc0, .end = 0xdf,
 117                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 118         { .name = "fpu", .start = 0xf0, .end = 0xff,
 119                 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
 120 };
 121
 122 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
 123
 124 struct resource data_resource = {
 125         .name = "Kernel data",
 126         .start = 0,
 127         .end = 0,
 128         .flags = IORESOURCE_RAM,
 129 };
 130 struct resource code_resource = {
 131         .name = "Kernel code",
 132         .start = 0,
 133         .end = 0,
 134         .flags = IORESOURCE_RAM,
 135 };
 136
 137 #ifdef CONFIG_PROC_VMCORE
 138 /* elfcorehdr= specifies the location of elf core header
 139  * stored by the crashed kernel. This option will be passed
 140  * by kexec loader to the capture kernel.
 141  */
 142 static int __init setup_elfcorehdr(char *arg)
 143 {
 144         char *end;
 145         if (!arg)
 146                 return -EINVAL;
 147         elfcorehdr_addr = memparse(arg, &end);
 148         return end > arg ? 0 : -EINVAL;
 149 }
 150 early_param("elfcorehdr", setup_elfcorehdr);
 151 #endif
 152
 153 #ifndef CONFIG_NUMA
 154 static void __init
 155 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
 156 {
 157         unsigned long bootmap_size, bootmap;
 158
 159         bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
 160         bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
 161         if (bootmap == -1L)
 162                 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
 163         bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
 164         e820_register_active_regions(0, start_pfn, end_pfn);
 165         free_bootmem_with_active_regions(0, end_pfn);
 166         reserve_bootmem(bootmap, bootmap_size);
 167 }
 168 #endif
 169
 170 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
 171 struct edd edd;
 172 #ifdef CONFIG_EDD_MODULE
 173 EXPORT_SYMBOL(edd);
 174 #endif
 175 /**
 176  * copy_edd() - Copy the BIOS EDD information
 177  *              from boot_params into a safe place.
 178  *
 179  */
 180 static inline void copy_edd(void)
 181 {
 182      memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
 183             sizeof(edd.mbr_signature));
 184      memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
 185      edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
 186      edd.edd_info_nr = boot_params.eddbuf_entries;
 187 }
 188 #else
 189 static inline void copy_edd(void)
 190 {
 191 }
 192 #endif
 193
 194 #define EBDA_ADDR_POINTER 0x40E
 195
 196 unsigned __initdata ebda_addr;
 197 unsigned __initdata ebda_size;
 198
 199 static void discover_ebda(void)
 200 {
 201         /*
 202          * there is a real-mode segmented pointer pointing to the
 203          * 4K EBDA area at 0x40E
 204          */
 205         ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
 206         ebda_addr <<= 4;
 207
 208         ebda_size = *(unsigned short *)__va(ebda_addr);
 209
 210         /* Round EBDA up to pages */
 211         if (ebda_size == 0)
 212                 ebda_size = 1;
 213         ebda_size <<= 10;
 214         ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
 215         if (ebda_size > 64*1024)
 216                 ebda_size = 64*1024;
 217 }
 218
 219 void __init setup_arch(char **cmdline_p)
 220 {
 221         printk(KERN_INFO "Command line: %s\n", boot_command_line);
 222
 223         ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
 224         screen_info = boot_params.screen_info;
 225         edid_info = boot_params.edid_info;
 226         saved_video_mode = boot_params.hdr.vid_mode;
 227         bootloader_type = boot_params.hdr.type_of_loader;
 228
 229 #ifdef CONFIG_BLK_DEV_RAM
 230         rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
 231         rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
 232         rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
 233 #endif
 234         setup_memory_region();
 235         copy_edd();
 236
 237         if (!boot_params.hdr.root_flags)
 238                 root_mountflags &= ~MS_RDONLY;
 239         init_mm.start_code = (unsigned long) &_text;
 240         init_mm.end_code = (unsigned long) &_etext;
 241         init_mm.end_data = (unsigned long) &_edata;
 242         init_mm.brk = (unsigned long) &_end;
 243
 244         code_resource.start = virt_to_phys(&_text);
 245         code_resource.end = virt_to_phys(&_etext)-1;
 246         data_resource.start = virt_to_phys(&_etext);
 247         data_resource.end = virt_to_phys(&_edata)-1;
 248
 249         early_identify_cpu(&boot_cpu_data);
 250
 251         strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 252         *cmdline_p = command_line;
 253
 254         parse_early_param();
 255
 256         finish_e820_parsing();
 257
 258         e820_register_active_regions(0, 0, -1UL);
 259         /*
 260          * partially used pages are not usable - thus
 261          * we are rounding upwards:
 262          */
 263         end_pfn = e820_end_of_ram();
 264         num_physpages = end_pfn;
 265
 266         check_efer();
 267
 268         discover_ebda();
 269
 270         init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
 271
 272         dmi_scan_machine();
 273
 274 #ifdef CONFIG_SMP
 275         /* setup to use the static apicid table during kernel startup */
 276         x86_cpu_to_apicid_ptr = (void *)&x86_cpu_to_apicid_init;
 277 #endif
 278
 279 #ifdef CONFIG_ACPI
 280         /*
 281          * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
 282          * Call this early for SRAT node setup.
 283          */
 284         acpi_boot_table_init();
 285 #endif
 286
 287         /* How many end-of-memory variables you have, grandma! */
 288         max_low_pfn = end_pfn;
 289         max_pfn = end_pfn;
 290         high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
 291
 292         /* Remove active ranges so rediscovery with NUMA-awareness happens */
 293         remove_all_active_ranges();
 294
 295 #ifdef CONFIG_ACPI_NUMA
 296         /*
 297          * Parse SRAT to discover nodes.
 298          */
 299         acpi_numa_init();
 300 #endif
 301
 302 #ifdef CONFIG_NUMA
 303         numa_initmem_init(0, end_pfn);
 304 #else
 305         contig_initmem_init(0, end_pfn);
 306 #endif
 307
 308         /* Reserve direct mapping */
 309         reserve_bootmem_generic(table_start << PAGE_SHIFT,
 310                                 (table_end - table_start) << PAGE_SHIFT);
 311
 312         /* reserve kernel */
 313         reserve_bootmem_generic(__pa_symbol(&_text),
 314                                 __pa_symbol(&_end) - __pa_symbol(&_text));
 315
 316         /*
 317          * reserve physical page 0 - it's a special BIOS page on many boxes,
 318          * enabling clean reboots, SMP operation, laptop functions.
 319          */
 320         reserve_bootmem_generic(0, PAGE_SIZE);
 321
 322         /* reserve ebda region */
 323         if (ebda_addr)
 324                 reserve_bootmem_generic(ebda_addr, ebda_size);
 325 #ifdef CONFIG_NUMA
 326         /* reserve nodemap region */
 327         if (nodemap_addr)
 328                 reserve_bootmem_generic(nodemap_addr, nodemap_size);
 329 #endif
 330
 331 #ifdef CONFIG_SMP
 332         /* Reserve SMP trampoline */
 333         reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
 334 #endif
 335
 336 #ifdef CONFIG_ACPI_SLEEP
 337        /*
 338         * Reserve low memory region for sleep support.
 339         */
 340        acpi_reserve_bootmem();
 341 #endif
 342         /*
 343          * Find and reserve possible boot-time SMP configuration:
 344          */
 345         find_smp_config();
 346 #ifdef CONFIG_BLK_DEV_INITRD
 347         if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
 348                 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
 349                 unsigned long ramdisk_size  = boot_params.hdr.ramdisk_size;
 350                 unsigned long ramdisk_end   = ramdisk_image + ramdisk_size;
 351                 unsigned long end_of_mem    = end_pfn << PAGE_SHIFT;
 352
 353                 if (ramdisk_end <= end_of_mem) {
 354                         reserve_bootmem_generic(ramdisk_image, ramdisk_size);
 355                         initrd_start = ramdisk_image + PAGE_OFFSET;
 356                         initrd_end = initrd_start+ramdisk_size;
 357                 } else {
 358                         printk(KERN_ERR "initrd extends beyond end of memory "
 359                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
 360                                ramdisk_end, end_of_mem);
 361                         initrd_start = 0;
 362                 }
 363         }
 364 #endif
 365 #ifdef CONFIG_KEXEC
 366         if (crashk_res.start != crashk_res.end) {
 367                 reserve_bootmem_generic(crashk_res.start,
 368                         crashk_res.end - crashk_res.start + 1);
 369         }
 370 #endif
 371
 372         paging_init();
 373
 374 #ifdef CONFIG_PCI
 375         early_quirks();
 376 #endif
 377
 378         /*
 379          * set this early, so we dont allocate cpu0
 380          * if MADT list doesnt list BSP first
 381          * mpparse.c/MP_processor_info() allocates logical cpu numbers.
 382          */
 383         cpu_set(0, cpu_present_map);
 384 #ifdef CONFIG_ACPI
 385         /*
 386          * Read APIC and some other early information from ACPI tables.
 387          */
 388         acpi_boot_init();
 389 #endif
 390
 391         init_cpu_to_node();
 392
 393         /*
 394          * get boot-time SMP configuration:
 395          */
 396         if (smp_found_config)
 397                 get_smp_config();
 398         init_apic_mappings();
 399
 400         /*
 401          * We trust e820 completely. No explicit ROM probing in memory.
 402          */
 403         e820_reserve_resources();
 404         e820_mark_nosave_regions();
 405
 406         {
 407         unsigned i;
 408         /* request I/O space for devices used on all i[345]86 PCs */
 409         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
 410                 request_resource(&ioport_resource, &standard_io_resources[i]);
 411         }
 412
 413         e820_setup_gap();
 414
 415 #ifdef CONFIG_VT
 416 #if defined(CONFIG_VGA_CONSOLE)
 417         conswitchp = &vga_con;
 418 #elif defined(CONFIG_DUMMY_CONSOLE)
 419         conswitchp = &dummy_con;
 420 #endif
 421 #endif
 422 }
 423
 424 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
 425 {
 426         unsigned int *v;
 427
 428         if (c->extended_cpuid_level < 0x80000004)
 429                 return 0;
 430
 431         v = (unsigned int *) c->x86_model_id;
 432         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 433         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 434         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 435         c->x86_model_id[48] = 0;
 436         return 1;
 437 }
 438
 439
 440 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 441 {
 442         unsigned int n, dummy, eax, ebx, ecx, edx;
 443
 444         n = c->extended_cpuid_level;
 445
 446         if (n >= 0x80000005) {
 447                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 448                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
 449                         edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
 450                 c->x86_cache_size=(ecx>>24)+(edx>>24);
 451                 /* On K8 L1 TLB is inclusive, so don't count it */
 452                 c->x86_tlbsize = 0;
 453         }
 454
 455         if (n >= 0x80000006) {
 456                 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 457                 ecx = cpuid_ecx(0x80000006);
 458                 c->x86_cache_size = ecx >> 16;
 459                 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 460
 461                 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 462                 c->x86_cache_size, ecx & 0xFF);
 463         }
 464
 465         if (n >= 0x80000007)
 466                 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
 467         if (n >= 0x80000008) {
 468                 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
 469                 c->x86_virt_bits = (eax >> 8) & 0xff;
 470                 c->x86_phys_bits = eax & 0xff;
 471         }
 472 }
 473
 474 #ifdef CONFIG_NUMA
 475 static int nearby_node(int apicid)
 476 {
 477         int i;
 478         for (i = apicid - 1; i >= 0; i--) {
 479                 int node = apicid_to_node[i];
 480                 if (node != NUMA_NO_NODE && node_online(node))
 481                         return node;
 482         }
 483         for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
 484                 int node = apicid_to_node[i];
 485                 if (node != NUMA_NO_NODE && node_online(node))
 486                         return node;
 487         }
 488         return first_node(node_online_map); /* Shouldn't happen */
 489 }
 490 #endif
 491
 492 /*
 493  * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
 494  * Assumes number of cores is a power of two.
 495  */
 496 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
 497 {
 498 #ifdef CONFIG_SMP
 499         unsigned bits;
 500 #ifdef CONFIG_NUMA
 501         int cpu = smp_processor_id();
 502         int node = 0;
 503         unsigned apicid = hard_smp_processor_id();
 504 #endif
 505         unsigned ecx = cpuid_ecx(0x80000008);
 506
 507         c->x86_max_cores = (ecx & 0xff) + 1;
 508
 509         /* CPU telling us the core id bits shift? */
 510         bits = (ecx >> 12) & 0xF;
 511
 512         /* Otherwise recompute */
 513         if (bits == 0) {
 514                 while ((1 << bits) < c->x86_max_cores)
 515                         bits++;
 516         }
 517
 518         /* Low order bits define the core id (index of core in socket) */
 519         c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
 520         /* Convert the APIC ID into the socket ID */
 521         c->phys_proc_id = phys_pkg_id(bits);
 522
 523 #ifdef CONFIG_NUMA
 524         node = c->phys_proc_id;
 525         if (apicid_to_node[apicid] != NUMA_NO_NODE)
 526                 node = apicid_to_node[apicid];
 527         if (!node_online(node)) {
 528                 /* Two possibilities here:
 529                    - The CPU is missing memory and no node was created.
 530                    In that case try picking one from a nearby CPU
 531                    - The APIC IDs differ from the HyperTransport node IDs
 532                    which the K8 northbridge parsing fills in.
 533                    Assume they are all increased by a constant offset,
 534                    but in the same order as the HT nodeids.
 535                    If that doesn't result in a usable node fall back to the
 536                    path for the previous case.  */
 537                 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
 538                 if (ht_nodeid >= 0 &&
 539                     apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
 540                         node = apicid_to_node[ht_nodeid];
 541                 /* Pick a nearby node */
 542                 if (!node_online(node))
 543                         node = nearby_node(apicid);
 544         }
 545         numa_set_node(cpu, node);
 546
 547         printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
 548 #endif
 549 #endif
 550 }
 551
 552 #define ENABLE_C1E_MASK         0x18000000
 553 #define CPUID_PROCESSOR_SIGNATURE       1
 554 #define CPUID_XFAM              0x0ff00000
 555 #define CPUID_XFAM_K8           0x00000000
 556 #define CPUID_XFAM_10H          0x00100000
 557 #define CPUID_XFAM_11H          0x00200000
 558 #define CPUID_XMOD              0x000f0000
 559 #define CPUID_XMOD_REV_F        0x00040000
 560
 561 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
 562 static __cpuinit int amd_apic_timer_broken(void)
 563 {
 564         u32 lo, hi;
 565         u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
 566         switch (eax & CPUID_XFAM) {
 567         case CPUID_XFAM_K8:
 568                 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
 569                         break;
 570         case CPUID_XFAM_10H:
 571         case CPUID_XFAM_11H:
 572                 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
 573                 if (lo & ENABLE_C1E_MASK)
 574                         return 1;
 575                 break;
 576         default:
 577                 /* err on the side of caution */
 578                 return 1;
 579         }
 580         return 0;
 581 }
 582
 583 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 584 {
 585         unsigned level;
 586
 587 #ifdef CONFIG_SMP
 588         unsigned long value;
 589
 590         /*
 591          * Disable TLB flush filter by setting HWCR.FFDIS on K8
 592          * bit 6 of msr C001_0015
 593          *
 594          * Errata 63 for SH-B3 steppings
 595          * Errata 122 for all steppings (F+ have it disabled by default)
 596          */
 597         if (c->x86 == 15) {
 598                 rdmsrl(MSR_K8_HWCR, value);
 599                 value |= 1 << 6;
 600                 wrmsrl(MSR_K8_HWCR, value);
 601         }
 602 #endif
 603
 604         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 605            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
 606         clear_bit(0*32+31, &c->x86_capability);
 607
 608         /* On C+ stepping K8 rep microcode works well for copy/memset */
 609         level = cpuid_eax(1);
 610         if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
 611                 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
 612         if (c->x86 == 0x10 || c->x86 == 0x11)
 613                 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
 614
 615         /* Enable workaround for FXSAVE leak */
 616         if (c->x86 >= 6)
 617                 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
 618
 619         level = get_model_name(c);
 620         if (!level) {
 621                 switch (c->x86) {
 622                 case 15:
 623                         /* Should distinguish Models here, but this is only
 624                            a fallback anyways. */
 625                         strcpy(c->x86_model_id, "Hammer");
 626                         break;
 627                 }
 628         }
 629         display_cacheinfo(c);
 630
 631         /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
 632         if (c->x86_power & (1<<8))
 633                 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
 634
 635         /* Multi core CPU? */
 636         if (c->extended_cpuid_level >= 0x80000008)
 637                 amd_detect_cmp(c);
 638
 639         if (c->extended_cpuid_level >= 0x80000006 &&
 640                 (cpuid_edx(0x80000006) & 0xf000))
 641                 num_cache_leaves = 4;
 642         else
 643                 num_cache_leaves = 3;
 644
 645         if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
 646                 set_bit(X86_FEATURE_K8, &c->x86_capability);
 647
 648         /* RDTSC can be speculated around */
 649         clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
 650
 651         /* Family 10 doesn't support C states in MWAIT so don't use it */
 652         if (c->x86 == 0x10 && !force_mwait)
 653                 clear_bit(X86_FEATURE_MWAIT, &c->x86_capability);
 654
 655         if (amd_apic_timer_broken())
 656                 disable_apic_timer = 1;
 657 }
 658
 659 static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 660 {
 661 #ifdef CONFIG_SMP
 662         u32     eax, ebx, ecx, edx;
 663         int     index_msb, core_bits;
 664
 665         cpuid(1, &eax, &ebx, &ecx, &edx);
 666
 667
 668         if (!cpu_has(c, X86_FEATURE_HT))
 669                 return;
 670         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
 671                 goto out;
 672
 673         smp_num_siblings = (ebx & 0xff0000) >> 16;
 674
 675         if (smp_num_siblings == 1) {
 676                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
 677         } else if (smp_num_siblings > 1 ) {
 678
 679                 if (smp_num_siblings > NR_CPUS) {
 680                         printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
 681                         smp_num_siblings = 1;
 682                         return;
 683                 }
 684
 685                 index_msb = get_count_order(smp_num_siblings);
 686                 c->phys_proc_id = phys_pkg_id(index_msb);
 687
 688                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 689
 690                 index_msb = get_count_order(smp_num_siblings) ;
 691
 692                 core_bits = get_count_order(c->x86_max_cores);
 693
 694                 c->cpu_core_id = phys_pkg_id(index_msb) &
 695                                                ((1 << core_bits) - 1);
 696         }
 697 out:
 698         if ((c->x86_max_cores * smp_num_siblings) > 1) {
 699                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
 700                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n", c->cpu_core_id);
 701         }
 702
 703 #endif
 704 }
 705
 706 /*
 707  * find out the number of processor cores on the die
 708  */
 709 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 710 {
 711         unsigned int eax, t;
 712
 713         if (c->cpuid_level < 4)
 714                 return 1;
 715
 716         cpuid_count(4, 0, &eax, &t, &t, &t);
 717
 718         if (eax & 0x1f)
 719                 return ((eax >> 26) + 1);
 720         else
 721                 return 1;
 722 }
 723
 724 static void srat_detect_node(void)
 725 {
 726 #ifdef CONFIG_NUMA
 727         unsigned node;
 728         int cpu = smp_processor_id();
 729         int apicid = hard_smp_processor_id();
 730
 731         /* Don't do the funky fallback heuristics the AMD version employs
 732            for now. */
 733         node = apicid_to_node[apicid];
 734         if (node == NUMA_NO_NODE)
 735                 node = first_node(node_online_map);
 736         numa_set_node(cpu, node);
 737
 738         printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
 739 #endif
 740 }
 741
 742 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 743 {
 744         /* Cache sizes */
 745         unsigned n;
 746
 747         init_intel_cacheinfo(c);
 748         if (c->cpuid_level > 9 ) {
 749                 unsigned eax = cpuid_eax(10);
 750                 /* Check for version and the number of counters */
 751                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 752                         set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
 753         }
 754
 755         if (cpu_has_ds) {
 756                 unsigned int l1, l2;
 757                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 758                 if (!(l1 & (1<<11)))
 759                         set_bit(X86_FEATURE_BTS, c->x86_capability);
 760                 if (!(l1 & (1<<12)))
 761                         set_bit(X86_FEATURE_PEBS, c->x86_capability);
 762         }
 763
 764         n = c->extended_cpuid_level;
 765         if (n >= 0x80000008) {
 766                 unsigned eax = cpuid_eax(0x80000008);
 767                 c->x86_virt_bits = (eax >> 8) & 0xff;
 768                 c->x86_phys_bits = eax & 0xff;
 769                 /* CPUID workaround for Intel 0F34 CPU */
 770                 if (c->x86_vendor == X86_VENDOR_INTEL &&
 771                     c->x86 == 0xF && c->x86_model == 0x3 &&
 772                     c->x86_mask == 0x4)
 773                         c->x86_phys_bits = 36;
 774         }
 775
 776         if (c->x86 == 15)
 777                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 778         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
 779             (c->x86 == 0x6 && c->x86_model >= 0x0e))
 780                 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
 781         if (c->x86 == 6)
 782                 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
 783         if (c->x86 == 15)
 784                 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
 785         else
 786                 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
 787         c->x86_max_cores = intel_num_cpu_cores(c);
 788
 789         srat_detect_node();
 790 }
 791
 792 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 793 {
 794         char *v = c->x86_vendor_id;
 795
 796         if (!strcmp(v, "AuthenticAMD"))
 797                 c->x86_vendor = X86_VENDOR_AMD;
 798         else if (!strcmp(v, "GenuineIntel"))
 799                 c->x86_vendor = X86_VENDOR_INTEL;
 800         else
 801                 c->x86_vendor = X86_VENDOR_UNKNOWN;
 802 }
 803
 804 struct cpu_model_info {
 805         int vendor;
 806         int family;
 807         char *model_names[16];
 808 };
 809
 810 /* Do some early cpuid on the boot CPU to get some parameter that are
 811    needed before check_bugs. Everything advanced is in identify_cpu
 812    below. */
 813 void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
 814 {
 815         u32 tfms;
 816
 817         c->loops_per_jiffy = loops_per_jiffy;
 818         c->x86_cache_size = -1;
 819         c->x86_vendor = X86_VENDOR_UNKNOWN;
 820         c->x86_model = c->x86_mask = 0; /* So far unknown... */
 821         c->x86_vendor_id[0] = '\0'; /* Unset */
 822         c->x86_model_id[0] = '\0';  /* Unset */
 823         c->x86_clflush_size = 64;
 824         c->x86_cache_alignment = c->x86_clflush_size;
 825         c->x86_max_cores = 1;
 826         c->extended_cpuid_level = 0;
 827         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 828
 829         /* Get vendor name */
 830         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 831               (unsigned int *)&c->x86_vendor_id[0],
 832               (unsigned int *)&c->x86_vendor_id[8],
 833               (unsigned int *)&c->x86_vendor_id[4]);
 834
 835         get_cpu_vendor(c);
 836
 837         /* Initialize the standard set of capabilities */
 838         /* Note that the vendor-specific code below might override */
 839
 840         /* Intel-defined flags: level 0x00000001 */
 841         if (c->cpuid_level >= 0x00000001) {
 842                 __u32 misc;
 843                 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
 844                       &c->x86_capability[0]);
 845                 c->x86 = (tfms >> 8) & 0xf;
 846                 c->x86_model = (tfms >> 4) & 0xf;
 847                 c->x86_mask = tfms & 0xf;
 848                 if (c->x86 == 0xf)
 849                         c->x86 += (tfms >> 20) & 0xff;
 850                 if (c->x86 >= 0x6)
 851                         c->x86_model += ((tfms >> 16) & 0xF) << 4;
 852                 if (c->x86_capability[0] & (1<<19))
 853                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
 854         } else {
 855                 /* Have CPUID level 0 only - unheard of */
 856                 c->x86 = 4;
 857         }
 858
 859 #ifdef CONFIG_SMP
 860         c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
 861 #endif
 862 }
 863
 864 /*
 865  * This does the hard work of actually picking apart the CPU stuff...
 866  */
 867 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 868 {
 869         int i;
 870         u32 xlvl;
 871
 872         early_identify_cpu(c);
 873
 874         /* AMD-defined flags: level 0x80000001 */
 875         xlvl = cpuid_eax(0x80000000);
 876         c->extended_cpuid_level = xlvl;
 877         if ((xlvl & 0xffff0000) == 0x80000000) {
 878                 if (xlvl >= 0x80000001) {
 879                         c->x86_capability[1] = cpuid_edx(0x80000001);
 880                         c->x86_capability[6] = cpuid_ecx(0x80000001);
 881                 }
 882                 if (xlvl >= 0x80000004)
 883                         get_model_name(c); /* Default name */
 884         }
 885
 886         /* Transmeta-defined flags: level 0x80860001 */
 887         xlvl = cpuid_eax(0x80860000);
 888         if ((xlvl & 0xffff0000) == 0x80860000) {
 889                 /* Don't set x86_cpuid_level here for now to not confuse. */
 890                 if (xlvl >= 0x80860001)
 891                         c->x86_capability[2] = cpuid_edx(0x80860001);
 892         }
 893
 894         init_scattered_cpuid_features(c);
 895
 896         c->apicid = phys_pkg_id(0);
 897
 898         /*
 899          * Vendor-specific initialization.  In this section we
 900          * canonicalize the feature flags, meaning if there are
 901          * features a certain CPU supports which CPUID doesn't
 902          * tell us, CPUID claiming incorrect flags, or other bugs,
 903          * we handle them here.
 904          *
 905          * At the end of this section, c->x86_capability better
 906          * indicate the features this CPU genuinely supports!
 907          */
 908         switch (c->x86_vendor) {
 909         case X86_VENDOR_AMD:
 910                 init_amd(c);
 911                 break;
 912
 913         case X86_VENDOR_INTEL:
 914                 init_intel(c);
 915                 break;
 916
 917         case X86_VENDOR_UNKNOWN:
 918         default:
 919                 display_cacheinfo(c);
 920                 break;
 921         }
 922
 923         select_idle_routine(c);
 924         detect_ht(c);
 925
 926         /*
 927          * On SMP, boot_cpu_data holds the common feature set between
 928          * all CPUs; so make sure that we indicate which features are
 929          * common between the CPUs.  The first time this routine gets
 930          * executed, c == &boot_cpu_data.
 931          */
 932         if (c != &boot_cpu_data) {
 933                 /* AND the already accumulated flags with these */
 934                 for (i = 0 ; i < NCAPINTS ; i++)
 935                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
 936         }
 937
 938 #ifdef CONFIG_X86_MCE
 939         mcheck_init(c);
 940 #endif
 941         if (c != &boot_cpu_data)
 942                 mtrr_ap_init();
 943 #ifdef CONFIG_NUMA
 944         numa_add_cpu(smp_processor_id());
 945 #endif
 946 }
 947
 948
 949 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
 950 {
 951         if (c->x86_model_id[0])
 952                 printk("%s", c->x86_model_id);
 953
 954         if (c->x86_mask || c->cpuid_level >= 0)
 955                 printk(" stepping %02x\n", c->x86_mask);
 956         else
 957                 printk("\n");
 958 }
 959
 960 /*
 961  *      Get CPU information for use by the procfs.
 962  */
 963
 964 static int show_cpuinfo(struct seq_file *m, void *v)
 965 {
 966         struct cpuinfo_x86 *c = v;
 967
 968         /*
 969          * These flag bits must match the definitions in <asm/cpufeature.h>.
 970          * NULL means this bit is undefined or reserved; either way it doesn't
 971          * have meaning as far as Linux is concerned.  Note that it's important
 972          * to realize there is a difference between this table and CPUID -- if
 973          * applications want to get the raw CPUID data, they should access
 974          * /dev/cpu/<cpu_nr>/cpuid instead.
 975          */
 976         static const char *const x86_cap_flags[] = {
 977                 /* Intel-defined */
 978                 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
 979                 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
 980                 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
 981                 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
 982
 983                 /* AMD-defined */
 984                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 985                 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
 986                 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
 987                 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
 988                 "3dnowext", "3dnow",
 989
 990                 /* Transmeta-defined */
 991                 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
 992                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 993                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 994                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 995
 996                 /* Other (Linux-defined) */
 997                 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
 998                 NULL, NULL, NULL, NULL,
 999                 "constant_tsc", "up", NULL, "arch_perfmon",
1000                 "pebs", "bts", NULL, "sync_rdtsc",
1001                 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1002                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1003
1004                 /* Intel-defined (#2) */
1005                 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1006                 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1007                 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
1008                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1009
1010                 /* VIA/Cyrix/Centaur-defined */
1011                 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1012                 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1013                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1014                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1015
1016                 /* AMD-defined (#2) */
1017                 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
1018                 "altmovcr8", "abm", "sse4a",
1019                 "misalignsse", "3dnowprefetch",
1020                 "osvw", "ibs", NULL, NULL, NULL, NULL,
1021                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1022                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1023
1024                 /* Auxiliary (Linux-defined) */
1025                 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1026                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1027                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1028                 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1029         };
1030         static const char *const x86_power_flags[] = {
1031                 "ts",   /* temperature sensor */
1032                 "fid",  /* frequency id control */
1033                 "vid",  /* voltage id control */
1034                 "ttp",  /* thermal trip */
1035                 "tm",
1036                 "stc",
1037                 "100mhzsteps",
1038                 "hwpstate",
1039                 "",     /* tsc invariant mapped to constant_tsc */
1040                 /* nothing */
1041         };
1042
1043
1044 #ifdef CONFIG_SMP
1045         if (!cpu_online(c-cpu_data))
1046                 return 0;
1047 #endif
1048
1049         seq_printf(m,"processor\t: %u\n"
1050                      "vendor_id\t: %s\n"
1051                      "cpu family\t: %d\n"
1052                      "model\t\t: %d\n"
1053                      "model name\t: %s\n",
1054                      (unsigned)(c-cpu_data),
1055                      c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1056                      c->x86,
1057                      (int)c->x86_model,
1058                      c->x86_model_id[0] ? c->x86_model_id : "unknown");
1059
1060         if (c->x86_mask || c->cpuid_level >= 0)
1061                 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1062         else
1063                 seq_printf(m, "stepping\t: unknown\n");
1064
1065         if (cpu_has(c,X86_FEATURE_TSC)) {
1066                 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1067                 if (!freq)
1068                         freq = cpu_khz;
1069                 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1070                              freq / 1000, (freq % 1000));
1071         }
1072
1073         /* Cache size */
1074         if (c->x86_cache_size >= 0)
1075                 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1076
1077 #ifdef CONFIG_SMP
1078         if (smp_num_siblings * c->x86_max_cores > 1) {
1079                 int cpu = c - cpu_data;
1080                 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1081                 seq_printf(m, "siblings\t: %d\n",
1082                                cpus_weight(per_cpu(cpu_core_map, cpu)));
1083                 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1084                 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1085         }
1086 #endif
1087
1088         seq_printf(m,
1089                 "fpu\t\t: yes\n"
1090                 "fpu_exception\t: yes\n"
1091                 "cpuid level\t: %d\n"
1092                 "wp\t\t: yes\n"
1093                 "flags\t\t:",
1094                    c->cpuid_level);
1095
1096         {
1097                 int i;
1098                 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1099                         if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1100                                 seq_printf(m, " %s", x86_cap_flags[i]);
1101         }
1102
1103         seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1104                    c->loops_per_jiffy/(500000/HZ),
1105                    (c->loops_per_jiffy/(5000/HZ)) % 100);
1106
1107         if (c->x86_tlbsize > 0)
1108                 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1109         seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1110         seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1111
1112         seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1113                    c->x86_phys_bits, c->x86_virt_bits);
1114
1115         seq_printf(m, "power management:");
1116         {
1117                 unsigned i;
1118                 for (i = 0; i < 32; i++)
1119                         if (c->x86_power & (1 << i)) {
1120                                 if (i < ARRAY_SIZE(x86_power_flags) &&
1121                                         x86_power_flags[i])
1122                                         seq_printf(m, "%s%s",
1123                                                 x86_power_flags[i][0]?" ":"",
1124                                                 x86_power_flags[i]);
1125                                 else
1126                                         seq_printf(m, " [%d]", i);
1127                         }
1128         }
1129
1130         seq_printf(m, "\n\n");
1131
1132         return 0;
1133 }
1134
1135 static void *c_start(struct seq_file *m, loff_t *pos)
1136 {
1137         return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1138 }
1139
1140 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1141 {
1142         ++*pos;
1143         return c_start(m, pos);
1144 }
1145
1146 static void c_stop(struct seq_file *m, void *v)
1147 {
1148 }
1149
1150 struct seq_operations cpuinfo_op = {
1151         .start =c_start,
1152         .next = c_next,
1153         .stop = c_stop,
1154         .show = show_cpuinfo,
1155 };