| blob | 2c8dffdc889f2a32f4212f6b2d603b667cd5f074 |
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/module.h>
30 #include <linux/types.h>
31 #include <linux/init.h>
32 #include <linux/pci.h>
33 #include <linux/vmalloc.h>
34 #include <linux/pagemap.h>
35 #include <linux/delay.h>
36 #include <linux/netdevice.h>
37 #include <linux/tcp.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <linux/cpu.h>
45 #include <linux/smp.h>
46 #include <linux/pm_qos_params.h>
63 };
65 #ifdef DEBUG
66 /**
67 * e1000_get_hw_dev_name - return device name string
68 * used by hardware layer to print debugging information
69 **/
71 {
73 }
74 #endif
76 /**
77 * e1000_desc_unused - calculate if we have unused descriptors
78 **/
80 {
85 }
87 /**
88 * e1000_receive_skb - helper function to handle Rx indications
89 * @adapter: board private structure
90 * @status: descriptor status field as written by hardware
91 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
92 * @skb: pointer to sk_buff to be indicated to stack
93 **/
98 {
104 else
108 }
110 /**
111 * e1000_rx_checksum - Receive Checksum Offload for 82543
112 * @adapter: board private structure
113 * @status_err: receive descriptor status and error fields
114 * @csum: receive descriptor csum field
115 * @sk_buff: socket buffer with received data
116 **/
119 {
124 /* Ignore Checksum bit is set */
127 /* TCP/UDP checksum error bit is set */
129 /* let the stack verify checksum errors */
132 }
134 /* TCP/UDP Checksum has not been calculated */
138 /* It must be a TCP or UDP packet with a valid checksum */
140 /* TCP checksum is good */
143 /*
144 * IP fragment with UDP payload
145 * Hardware complements the payload checksum, so we undo it
146 * and then put the value in host order for further stack use.
147 */
151 }
153 }
155 /**
156 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
157 * @adapter: address of board private structure
158 **/
161 {
179 }
183 /* Better luck next round */
186 }
188 /*
189 * Make buffer alignment 2 beyond a 16 byte boundary
190 * this will result in a 16 byte aligned IP header after
191 * the 14 byte MAC header is removed
192 */
196 map_skb:
199 PCI_DMA_FROMDEVICE);
204 }
209 i++;
213 }
220 /*
221 * Force memory writes to complete before letting h/w
222 * know there are new descriptors to fetch. (Only
223 * applicable for weak-ordered memory model archs,
224 * such as IA-64).
225 */
228 }
229 }
231 /**
232 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
233 * @adapter: address of board private structure
234 **/
237 {
256 /* all unused desc entries get hw null ptr */
259 }
265 }
269 PCI_DMA_FROMDEVICE);
275 }
276 }
277 /*
278 * Refresh the desc even if buffer_addrs
279 * didn't change because each write-back
280 * erases this info.
281 */
284 }
292 }
294 /*
295 * Make buffer alignment 2 beyond a 16 byte boundary
296 * this will result in a 16 byte aligned IP header after
297 * the 14 byte MAC header is removed
298 */
304 PCI_DMA_FROMDEVICE);
308 /* cleanup skb */
312 }
316 i++;
320 }
322 no_buffers:
329 /*
330 * Force memory writes to complete before letting h/w
331 * know there are new descriptors to fetch. (Only
332 * applicable for weak-ordered memory model archs,
333 * such as IA-64).
334 */
336 /*
337 * Hardware increments by 16 bytes, but packet split
338 * descriptors are 32 bytes...so we increment tail
339 * twice as much.
340 */
342 }
343 }
345 /**
346 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
347 * @adapter: address of board private structure
348 * @rx_ring: pointer to receive ring structure
349 * @cleaned_count: number of buffers to allocate this pass
350 **/
354 {
364 NET_IP_ALIGN;
374 }
378 /* Better luck next round */
381 }
383 /* Make buffer alignment 2 beyond a 16 byte boundary
384 * this will result in a 16 byte aligned IP header after
385 * the 14 byte MAC header is removed
386 */
390 check_page:
391 /* allocate a new page if necessary */
397 }
398 }
403 PAGE_SIZE,
404 PCI_DMA_FROMDEVICE);
412 }
419 /* Force memory writes to complete before letting h/w
420 * know there are new descriptors to fetch. (Only
421 * applicable for weak-ordered memory model archs,
422 * such as IA-64). */
425 }
426 }
428 /**
429 * e1000_clean_rx_irq - Send received data up the network stack; legacy
430 * @adapter: board private structure
431 *
432 * the return value indicates whether actual cleaning was done, there
433 * is no guarantee that everything was cleaned
434 **/
437 {
443 u32 length;
455 u8 status;
467 i++;
476 cleaned_count++;
480 PCI_DMA_FROMDEVICE);
485 /* !EOP means multiple descriptors were used to store a single
486 * packet, also make sure the frame isn't just CRC only */
488 /* All receives must fit into a single buffer */
491 /* recycle */
494 }
497 /* recycle */
500 }
503 total_rx_packets++;
505 /*
506 * code added for copybreak, this should improve
507 * performance for small packets with large amounts
508 * of reassembly being done in the stack
509 */
518 NET_IP_ALIGN),
520 NET_IP_ALIGN));
521 /* save the skb in buffer_info as good */
524 }
525 /* else just continue with the old one */
526 }
527 /* end copybreak code */
530 /* Receive Checksum Offload */
538 next_desc:
541 /* return some buffers to hardware, one at a time is too slow */
545 }
547 /* use prefetched values */
550 }
562 }
566 {
571 }
575 }
576 }
579 {
585 /* detected Tx unit hang */
601 eop,
602 jiffies,
604 }
606 /**
607 * e1000_clean_tx_irq - Reclaim resources after transmit completes
608 * @adapter: board private structure
609 *
610 * the return value indicates whether actual cleaning was done, there
611 * is no guarantee that everything was cleaned
612 **/
614 {
639 /* multiply data chunks by size of headers */
644 }
649 i++;
652 }
656 #define E1000_TX_WEIGHT 64
657 /* weight of a sort for tx, to avoid endless transmit cleanup */
660 }
664 #define TX_WAKE_THRESHOLD 32
667 /* Make sure that anybody stopping the queue after this
668 * sees the new next_to_clean.
669 */
676 }
677 }
680 /*
681 * Detect a transmit hang in hardware, this serializes the
682 * check with the clearing of time_stamp and movement of i
683 */
691 }
692 }
698 }
700 /**
701 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
702 * @adapter: board private structure
703 *
704 * the return value indicates whether actual cleaning was done, there
705 * is no guarantee that everything was cleaned
706 **/
709 {
734 /* in the packet split case this is header only */
737 i++;
746 cleaned_count++;
749 PCI_DMA_FROMDEVICE);
757 }
762 }
771 }
773 /* Good Receive */
776 {
777 /*
778 * this looks ugly, but it seems compiler issues make it
779 * more efficient than reusing j
780 */
783 /*
784 * page alloc/put takes too long and effects small packet
785 * throughput, so unsplit small packets and save the alloc/put
786 * only valid in softirq (napi) context to call kmap_*
787 */
794 /*
795 * there is no documentation about how to call
796 * kmap_atomic, so we can't hold the mapping
797 * very long
798 */
810 }
819 PCI_DMA_FROMDEVICE);
826 }
828 copydone:
830 total_rx_packets++;
842 next_desc:
846 /* return some buffers to hardware, one at a time is too slow */
850 }
852 /* use prefetched values */
857 }
869 }
871 /**
872 * e1000_consume_page - helper function
873 **/
875 u16 length)
876 {
881 }
883 /**
884 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
885 * @adapter: board private structure
886 *
887 * the return value indicates whether actual cleaning was done, there
888 * is no guarantee that everything was cleaned
889 **/
893 {
899 u32 length;
911 u8 status;
930 cleaned_count++;
932 PCI_DMA_FROMDEVICE);
937 /* errors is only valid for DD + EOP descriptors */
940 /* recycle both page and skb */
942 /* an error means any chain goes out the window
943 * too */
948 }
950 #define rxtop rx_ring->rx_skb_top
952 /* this descriptor is only the beginning (or middle) */
954 /* this is the beginning of a chain */
959 /* this is the middle of a chain */
963 /* re-use the skb, only consumed the page */
965 }
970 /* end of the chain */
974 /* re-use the current skb, we only consumed the
975 * page */
981 /* no chain, got EOP, this buf is the packet
982 * copybreak to save the put_page/alloc_page */
987 KM_SKB_DATA_SOFTIRQ);
989 length);
991 KM_SKB_DATA_SOFTIRQ);
992 /* re-use the page, so don't erase
993 * buffer_info->page */
998 length);
1000 length);
1001 }
1002 }
1003 }
1005 /* Receive Checksum Offload XXX recompute due to CRC strip? */
1011 /* probably a little skewed due to removing CRC */
1013 total_rx_packets++;
1015 /* eth type trans needs skb->data to point to something */
1020 }
1025 next_desc:
1028 /* return some buffers to hardware, one at a time is too slow */
1032 }
1034 /* use prefetched values */
1037 }
1049 }
1051 /**
1052 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1053 * @adapter: board private structure
1054 **/
1056 {
1063 /* Free all the Rx ring sk_buffs */
1070 PCI_DMA_FROMDEVICE);
1073 PAGE_SIZE,
1074 PCI_DMA_FROMDEVICE);
1078 PCI_DMA_FROMDEVICE);
1080 }
1085 }
1090 }
1097 PCI_DMA_FROMDEVICE);
1101 }
1102 }
1104 /* there also may be some cached data from a chained receive */
1108 }
1110 /* Zero out the descriptor ring */
1118 }
1121 {
1126 }
1128 /**
1129 * e1000_intr_msi - Interrupt Handler
1130 * @irq: interrupt number
1131 * @data: pointer to a network interface device structure
1132 **/
1134 {
1140 /*
1141 * read ICR disables interrupts using IAM
1142 */
1146 /*
1147 * ICH8 workaround-- Call gig speed drop workaround on cable
1148 * disconnect (LSC) before accessing any PHY registers
1149 */
1154 /*
1155 * 80003ES2LAN workaround-- For packet buffer work-around on
1156 * link down event; disable receives here in the ISR and reset
1157 * adapter in watchdog
1158 */
1161 /* disable receives */
1165 }
1166 /* guard against interrupt when we're going down */
1169 }
1177 }
1180 }
1182 /**
1183 * e1000_intr - Interrupt Handler
1184 * @irq: interrupt number
1185 * @data: pointer to a network interface device structure
1186 **/
1188 {
1197 /*
1198 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1199 * not set, then the adapter didn't send an interrupt
1200 */
1204 /*
1205 * Interrupt Auto-Mask...upon reading ICR,
1206 * interrupts are masked. No need for the
1207 * IMC write
1208 */
1212 /*
1213 * ICH8 workaround-- Call gig speed drop workaround on cable
1214 * disconnect (LSC) before accessing any PHY registers
1215 */
1220 /*
1221 * 80003ES2LAN workaround--
1222 * For packet buffer work-around on link down event;
1223 * disable receives here in the ISR and
1224 * reset adapter in watchdog
1225 */
1228 /* disable receives */
1232 }
1233 /* guard against interrupt when we're going down */
1236 }
1244 }
1247 }
1250 {
1259 }
1268 /* guard against interrupt when we're going down */
1271 }
1273 no_link_interrupt:
1277 }
1281 {
1292 /* Ring was not completely cleaned, so fire another interrupt */
1296 }
1299 {
1303 /* Write the ITR value calculated at the end of the
1304 * previous interrupt.
1305 */
1310 }
1316 }
1318 }
1320 /**
1321 * e1000_configure_msix - Configure MSI-X hardware
1322 *
1323 * e1000_configure_msix sets up the hardware to properly
1324 * generate MSI-X interrupts.
1325 **/
1327 {
1336 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1341 }
1343 #define E1000_IVAR_INT_ALLOC_VALID 0x8
1344 /* Configure Rx vector */
1350 else
1354 /* Configure Tx vector */
1356 vector++;
1360 else
1365 /* set vector for Other Causes, e.g. link changes */
1366 vector++;
1371 else
1374 /* Cause Tx interrupts on every write back */
1379 /* enable MSI-X PBA support */
1383 /* Auto-Mask Other interrupts upon ICR read */
1384 #define E1000_EIAC_MASK_82574 0x01F00000
1389 }
1392 {
1400 }
1403 }
1405 /**
1406 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1407 *
1408 * Attempt to configure interrupts using the best available
1409 * capabilities of the hardware and kernel.
1410 **/
1412 {
1423 GFP_KERNEL);
1430 numvecs);
1433 }
1434 /* MSI-X failed, so fall through and try MSI */
1438 }
1440 /* Fall through */
1448 }
1449 /* Fall through */
1451 /* Don't do anything; this is the system default */
1453 }
1456 }
1458 /**
1459 * e1000_request_msix - Initialize MSI-X interrupts
1460 *
1461 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1462 * kernel.
1463 **/
1465 {
1471 else
1475 netdev);
1480 vector++;
1484 else
1488 netdev);
1493 vector++;
1502 out:
1504 }
1506 /**
1507 * e1000_request_irq - initialize interrupts
1508 *
1509 * Attempts to configure interrupts using the best available
1510 * capabilities of the hardware and kernel.
1511 **/
1513 {
1521 /* fall back to MSI */
1525 }
1532 /* fall back to legacy interrupt */
1535 }
1543 }
1546 {
1553 vector++;
1556 vector++;
1558 /* Other Causes interrupt vector */
1561 }
1564 }
1566 /**
1567 * e1000_irq_disable - Mask off interrupt generation on the NIC
1568 **/
1570 {
1578 }
1580 /**
1581 * e1000_irq_enable - Enable default interrupt generation settings
1582 **/
1584 {
1592 }
1594 }
1596 /**
1597 * e1000_get_hw_control - get control of the h/w from f/w
1598 * @adapter: address of board private structure
1599 *
1600 * e1000_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
1601 * For ASF and Pass Through versions of f/w this means that
1602 * the driver is loaded. For AMT version (only with 82573)
1603 * of the f/w this means that the network i/f is open.
1604 **/
1606 {
1608 u32 ctrl_ext;
1609 u32 swsm;
1611 /* Let firmware know the driver has taken over */
1618 }
1619 }
1621 /**
1622 * e1000_release_hw_control - release control of the h/w to f/w
1623 * @adapter: address of board private structure
1624 *
1625 * e1000_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
1626 * For ASF and Pass Through versions of f/w this means that the
1627 * driver is no longer loaded. For AMT version (only with 82573) i
1628 * of the f/w this means that the network i/f is closed.
1629 *
1630 **/
1632 {
1634 u32 ctrl_ext;
1635 u32 swsm;
1637 /* Let firmware taken over control of h/w */
1644 }
1645 }
1647 /**
1648 * @e1000_alloc_ring - allocate memory for a ring structure
1649 **/
1652 {
1656 GFP_KERNEL);
1661 }
1663 /**
1664 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
1665 * @adapter: board private structure
1666 *
1667 * Return 0 on success, negative on failure
1668 **/
1670 {
1680 /* round up to nearest 4K */
1693 err:
1697 }
1699 /**
1700 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
1701 * @adapter: board private structure
1702 *
1703 * Returns 0 on success, negative on failure
1704 **/
1706 {
1721 GFP_KERNEL);
1724 }
1728 /* Round up to nearest 4K */
1742 err_pages:
1746 }
1747 err:
1751 }
1753 /**
1754 * e1000_clean_tx_ring - Free Tx Buffers
1755 * @adapter: board private structure
1756 **/
1758 {
1767 }
1779 }
1781 /**
1782 * e1000e_free_tx_resources - Free Tx Resources per Queue
1783 * @adapter: board private structure
1784 *
1785 * Free all transmit software resources
1786 **/
1788 {
1800 }
1802 /**
1803 * e1000e_free_rx_resources - Free Rx Resources
1804 * @adapter: board private structure
1805 *
1806 * Free all receive software resources
1807 **/
1810 {
1819 }
1827 }
1829 /**
1830 * e1000_update_itr - update the dynamic ITR value based on statistics
1831 * @adapter: pointer to adapter
1832 * @itr_setting: current adapter->itr
1833 * @packets: the number of packets during this measurement interval
1834 * @bytes: the number of bytes during this measurement interval
1835 *
1836 * Stores a new ITR value based on packets and byte
1837 * counts during the last interrupt. The advantage of per interrupt
1838 * computation is faster updates and more accurate ITR for the current
1839 * traffic pattern. Constants in this function were computed
1840 * based on theoretical maximum wire speed and thresholds were set based
1841 * on testing data as well as attempting to minimize response time
1842 * while increasing bulk throughput. This functionality is controlled
1843 * by the InterruptThrottleRate module parameter.
1844 **/
1848 {
1856 /* handle TSO and jumbo frames */
1861 }
1865 /* this if handles the TSO accounting */
1872 }
1877 }
1883 }
1886 }
1888 }
1890 update_itr_done:
1892 }
1895 {
1897 u16 current_itr;
1900 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
1905 }
1911 /* conservative mode (itr 3) eliminates the lowest_latency setting */
1919 /* conservative mode (itr 3) eliminates the lowest_latency setting */
1926 /* counts and packets in update_itr are dependent on these numbers */
1938 }
1940 set_itr_now:
1942 /*
1943 * this attempts to bias the interrupt rate towards Bulk
1944 * by adding intermediate steps when interrupt rate is
1945 * increasing
1946 */
1949 new_itr;
1954 else
1956 }
1957 }
1959 /**
1960 * e1000_alloc_queues - Allocate memory for all rings
1961 * @adapter: board private structure to initialize
1962 **/
1964 {
1974 err:
1979 }
1981 /**
1982 * e1000_clean - NAPI Rx polling callback
1983 * @napi: struct associated with this polling callback
1984 * @budget: amount of packets driver is allowed to process this poll
1985 **/
1987 {
1993 /* Must NOT use netdev_priv macro here. */
2000 /*
2001 * e1000_clean is called per-cpu. This lock protects
2002 * tx_ring from being cleaned by multiple cpus
2003 * simultaneously. A failure obtaining the lock means
2004 * tx_ring is currently being cleaned anyway.
2005 */
2009 }
2011 clean_rx:
2017 /* If budget not fully consumed, exit the polling mode */
2024 else
2026 }
2029 }
2032 {
2037 /* don't update vlan cookie if already programmed */
2039 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2042 /* add VID to filter table */
2047 }
2050 {
2063 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2065 /* release control to f/w */
2068 }
2070 /* remove VID from filter table */
2075 }
2078 {
2089 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2092 }
2100 }
2101 }
2106 {
2116 /* enable VLAN tag insert/strip */
2122 /* enable VLAN receive filtering */
2127 }
2129 /* disable VLAN tag insert/strip */
2140 }
2141 }
2142 }
2146 }
2149 {
2150 u16 vid;
2161 }
2162 }
2165 {
2174 /*
2175 * enable receiving management packets to the host. this will probably
2176 * generate destination unreachable messages from the host OS, but
2177 * the packets will be handled on SMBUS
2178 */
2181 #define E1000_MNG2HOST_PORT_623 (1 << 5)
2182 #define E1000_MNG2HOST_PORT_664 (1 << 6)
2187 }
2189 /**
2190 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
2191 * @adapter: board private structure
2192 *
2193 * Configure the Tx unit of the MAC after a reset.
2194 **/
2196 {
2199 u64 tdba;
2203 /* Setup the HW Tx Head and Tail descriptor pointers */
2214 /* Set the default values for the Tx Inter Packet Gap timer */
2226 /* Set the Tx Interrupt Delay register */
2228 /* Tx irq moderation */
2231 /* Program the Transmit Control Register */
2239 /*
2240 * set the speed mode bit, we'll clear it if we're not at
2241 * gigabit link later
2242 */
2243 #define SPEED_MODE_BIT (1 << 21)
2246 }
2248 /* errata: program both queues to unweighted RR */
2256 }
2260 /* Setup Transmit Descriptor Settings for eop descriptor */
2263 /* only set IDE if we are delaying interrupts using the timers */
2267 /* enable Report Status bit */
2273 }
2275 /**
2276 * e1000_setup_rctl - configure the receive control registers
2277 * @adapter: Board private structure
2278 **/
2279 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2280 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2282 {
2288 /* Program MC offset vector base */
2295 /* Do not Store bad packets */
2298 /* Enable Long Packet receive */
2301 else
2304 /* Enable hardware CRC frame stripping */
2307 /* Setup buffer sizes */
2337 }
2339 /*
2340 * 82571 and greater support packet-split where the protocol
2341 * header is placed in skb->data and the packet data is
2342 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2343 * In the case of a non-split, skb->data is linearly filled,
2344 * followed by the page buffers. Therefore, skb->data is
2345 * sized to hold the largest protocol header.
2346 *
2347 * allocations using alloc_page take too long for regular MTU
2348 * so only enable packet split for jumbo frames
2349 *
2350 * Using pages when the page size is greater than 16k wastes
2351 * a lot of memory, since we allocate 3 pages at all times
2352 * per packet.
2353 */
2358 else
2362 /* Configure extra packet-split registers */
2365 /*
2366 * disable packet split support for IPv6 extension headers,
2367 * because some malformed IPv6 headers can hang the Rx
2368 */
2370 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2374 /* Enable Packet split descriptors */
2378 E1000_PSRCTL_BSIZE0_SHIFT;
2383 E1000_PSRCTL_BSIZE3_SHIFT;
2386 E1000_PSRCTL_BSIZE2_SHIFT;
2389 E1000_PSRCTL_BSIZE1_SHIFT;
2391 }
2394 }
2397 /* just started the receive unit, no need to restart */
2399 }
2401 /**
2402 * e1000_configure_rx - Configure Receive Unit after Reset
2403 * @adapter: board private structure
2404 *
2405 * Configure the Rx unit of the MAC after a reset.
2406 **/
2408 {
2411 u64 rdba;
2415 /* this is a 32 byte descriptor */
2428 }
2430 /* disable receives while setting up the descriptors */
2436 /* set the Receive Delay Timer Register */
2439 /* irq moderation */
2445 /* Reset delay timers after every interrupt */
2447 /* Auto-Mask interrupts upon ICR access */
2453 /*
2454 * Setup the HW Rx Head and Tail Descriptor Pointers and
2455 * the Base and Length of the Rx Descriptor Ring
2456 */
2466 /* Enable Receive Checksum Offload for TCP and UDP */
2471 /*
2472 * IPv4 payload checksum for UDP fragments must be
2473 * used in conjunction with packet-split.
2474 */
2479 /* no need to clear IPPCSE as it defaults to 0 */
2480 }
2483 /*
2484 * Enable early receives on supported devices, only takes effect when
2485 * packet size is equal or larger than the specified value (in 8 byte
2486 * units), e.g. using jumbo frames when setting to E1000_ERT_2048
2487 */
2493 /*
2494 * With jumbo frames and early-receive enabled, excessive
2495 * C4->C2 latencies result in dropped transactions.
2496 */
2501 e1000e_driver_name,
2502 PM_QOS_DEFAULT_VALUE);
2503 }
2505 /* Enable Receives */
2507 }
2509 /**
2510 * e1000_update_mc_addr_list - Update Multicast addresses
2511 * @hw: pointer to the HW structure
2512 * @mc_addr_list: array of multicast addresses to program
2513 * @mc_addr_count: number of multicast addresses to program
2514 * @rar_used_count: the first RAR register free to program
2515 * @rar_count: total number of supported Receive Address Registers
2516 *
2517 * Updates the Receive Address Registers and Multicast Table Array.
2518 * The caller must have a packed mc_addr_list of multicast addresses.
2519 * The parameter rar_count will usually be hw->mac.rar_entry_count
2520 * unless there are workarounds that change this. Currently no func pointer
2521 * exists and all implementations are handled in the generic version of this
2522 * function.
2523 **/
2526 u32 rar_count)
2527 {
2530 }
2532 /**
2533 * e1000_set_multi - Multicast and Promiscuous mode set
2534 * @netdev: network interface device structure
2535 *
2536 * The set_multi entry point is called whenever the multicast address
2537 * list or the network interface flags are updated. This routine is
2538 * responsible for configuring the hardware for proper multicast,
2539 * promiscuous mode, and all-multi behavior.
2540 **/
2542 {
2548 u32 rctl;
2551 /* Check for Promiscuous and All Multicast modes */
2564 }
2567 }
2576 /* prepare a packed array of only addresses. */
2583 ETH_ALEN);
2585 }
2591 /*
2592 * if we're called from probe, we might not have
2593 * anything to do here, so clear out the list
2594 */
2596 }
2597 }
2599 /**
2600 * e1000_configure - configure the hardware for Rx and Tx
2601 * @adapter: private board structure
2602 **/
2604 {
2614 }
2616 /**
2617 * e1000e_power_up_phy - restore link in case the phy was powered down
2618 * @adapter: address of board private structure
2619 *
2620 * The phy may be powered down to save power and turn off link when the
2621 * driver is unloaded and wake on lan is not enabled (among others)
2622 * *** this routine MUST be followed by a call to e1000e_reset ***
2623 **/
2625 {
2628 /* Just clear the power down bit to wake the phy back up */
2630 /*
2631 * According to the manual, the phy will retain its
2632 * settings across a power-down/up cycle
2633 */
2637 }
2640 }
2642 /**
2643 * e1000_power_down_phy - Power down the PHY
2644 *
2645 * Power down the PHY so no link is implied when interface is down
2646 * The PHY cannot be powered down is management or WoL is active
2647 */
2649 {
2651 u16 mii_reg;
2653 /* WoL is enabled */
2657 /* non-copper PHY? */
2661 /* reset is blocked because of a SoL/IDER session */
2665 /* manageability (AMT) is enabled */
2669 /* power down the PHY */
2674 }
2676 /**
2677 * e1000e_reset - bring the hardware into a known good state
2678 *
2679 * This function boots the hardware and enables some settings that
2680 * require a configuration cycle of the hardware - those cannot be
2681 * set/changed during runtime. After reset the device needs to be
2682 * properly configured for Rx, Tx etc.
2683 */
2685 {
2691 u16 hwm;
2693 /* reset Packet Buffer Allocation to default */
2697 /*
2698 * To maintain wire speed transmits, the Tx FIFO should be
2699 * large enough to accommodate two full transmit packets,
2700 * rounded up to the next 1KB and expressed in KB. Likewise,
2701 * the Rx FIFO should be large enough to accommodate at least
2702 * one full receive packet and is similarly rounded up and
2703 * expressed in KB.
2704 */
2706 /* upper 16 bits has Tx packet buffer allocation size in KB */
2708 /* lower 16 bits has Rx packet buffer allocation size in KB */
2710 /*
2711 * the Tx fifo also stores 16 bytes of information about the tx
2712 * but don't include ethernet FCS because hardware appends it
2713 */
2719 /* software strips receive CRC, so leave room for it */
2724 /*
2725 * If current Tx allocation is less than the min Tx FIFO size,
2726 * and the min Tx FIFO size is less than the current Rx FIFO
2727 * allocation, take space away from current Rx allocation
2728 */
2733 /*
2734 * if short on Rx space, Rx wins and must trump tx
2735 * adjustment or use Early Receive if available
2736 */
2739 /* ERT enabled in e1000_configure_rx */
2741 }
2744 }
2747 /*
2748 * flow control settings
2749 *
2750 * The high water mark must be low enough to fit one full frame
2751 * (or the size used for early receive) above it in the Rx FIFO.
2752 * Set it to the lower of:
2753 * - 90% of the Rx FIFO size, and
2754 * - the full Rx FIFO size minus the early receive size (for parts
2755 * with ERT support assuming ERT set to E1000_ERT_2048), or
2756 * - the full Rx FIFO size minus one full frame
2757 */
2761 else
2770 else
2775 /* Allow time for pending master requests to run */
2778 /*
2779 * For parts with AMT enabled, let the firmware know
2780 * that the network interface is in control
2781 */
2792 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2800 /*
2801 * speed up time to link by disabling smart power down, ignore
2802 * the return value of this function because there is nothing
2803 * different we would do if it failed
2804 */
2808 }
2809 }
2812 {
2815 /* hardware has been reset, we need to reload some things */
2825 /* fire a link change interrupt to start the watchdog */
2828 }
2831 {
2836 /*
2837 * signal that we're down so the interrupt handler does not
2838 * reschedule our watchdog timer
2839 */
2842 /* disable receives in the hardware */
2845 /* flush and sleep below */
2849 /* disable transmits in the hardware */
2853 /* flush both disables and wait for them to finish */
2873 /*
2874 * TODO: for power management, we could drop the link and
2875 * pci_disable_device here.
2876 */
2877 }
2880 {
2887 }
2889 /**
2890 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
2891 * @adapter: board private structure to initialize
2892 *
2893 * e1000_sw_init initializes the Adapter private data structure.
2894 * Fields are initialized based on PCI device information and
2895 * OS network device settings (MTU size).
2896 **/
2898 {
2913 /* Explicitly disable IRQ since the NIC can be in any state. */
2918 }
2920 /**
2921 * e1000_intr_msi_test - Interrupt Handler
2922 * @irq: interrupt number
2923 * @data: pointer to a network interface device structure
2924 **/
2926 {
2936 }
2939 }
2941 /**
2942 * e1000_test_msi_interrupt - Returns 0 for successful test
2943 * @adapter: board private struct
2944 *
2945 * code flow taken from tg3.c
2946 **/
2948 {
2953 /* poll_enable hasn't been called yet, so don't need disable */
2954 /* clear any pending events */
2957 /* free the real vector and request a test handler */
2961 /* Assume that the test fails, if it succeeds then the test
2962 * MSI irq handler will unset this flag */
2974 }
2980 /* fire an unusual interrupt on the test handler */
2993 }
3001 /* okay so the test worked, restore settings */
3003 msi_test_failed:
3007 }
3009 /**
3010 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3011 * @adapter: board private struct
3012 *
3013 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3014 **/
3016 {
3018 u16 pci_cmd;
3023 /* disable SERR in case the MSI write causes a master abort */
3030 /* restore previous setting of command word */
3033 /* success ! */
3037 /* EIO means MSI test failed */
3041 /* back to INTx mode */
3049 }
3051 /**
3052 * e1000_open - Called when a network interface is made active
3053 * @netdev: network interface device structure
3054 *
3055 * Returns 0 on success, negative value on failure
3056 *
3057 * The open entry point is called when a network interface is made
3058 * active by the system (IFF_UP). At this point all resources needed
3059 * for transmit and receive operations are allocated, the interrupt
3060 * handler is registered with the OS, the watchdog timer is started,
3061 * and the stack is notified that the interface is ready.
3062 **/
3064 {
3069 /* disallow open during test */
3073 /* allocate transmit descriptors */
3078 /* allocate receive descriptors */
3087 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3090 /*
3091 * If AMT is enabled, let the firmware know that the network
3092 * interface is now open
3093 */
3097 /*
3098 * before we allocate an interrupt, we must be ready to handle it.
3099 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3100 * as soon as we call pci_request_irq, so we have to setup our
3101 * clean_rx handler before we do so.
3102 */
3109 /*
3110 * Work around PCIe errata with MSI interrupts causing some chipsets to
3111 * ignore e1000e MSI messages, which means we need to test our MSI
3112 * interrupt now
3113 */
3119 }
3120 }
3122 /* From here on the code is the same as e1000e_up() */
3131 /* fire a link status change interrupt to start the watchdog */
3136 err_req_irq:
3140 err_setup_rx:
3142 err_setup_tx:
3146 }
3148 /**
3149 * e1000_close - Disables a network interface
3150 * @netdev: network interface device structure
3151 *
3152 * Returns 0, this is not allowed to fail
3153 *
3154 * The close entry point is called when an interface is de-activated
3155 * by the OS. The hardware is still under the drivers control, but
3156 * needs to be disabled. A global MAC reset is issued to stop the
3157 * hardware, and all transmit and receive resources are freed.
3158 **/
3160 {
3171 /*
3172 * kill manageability vlan ID if supported, but not if a vlan with
3173 * the same ID is registered on the host OS (let 8021q kill it)
3174 */
3176 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3181 /*
3182 * If AMT is enabled, let the firmware know that the network
3183 * interface is now closed
3184 */
3189 }
3190 /**
3191 * e1000_set_mac - Change the Ethernet Address of the NIC
3192 * @netdev: network interface device structure
3193 * @p: pointer to an address structure
3194 *
3195 * Returns 0 on success, negative on failure
3196 **/
3198 {
3211 /* activate the work around */
3214 /*
3215 * Hold a copy of the LAA in RAR[14] This is done so that
3216 * between the time RAR[0] gets clobbered and the time it
3217 * gets fixed (in e1000_watchdog), the actual LAA is in one
3218 * of the RARs and no incoming packets directed to this port
3219 * are dropped. Eventually the LAA will be in RAR[0] and
3220 * RAR[14]
3221 */
3225 }
3228 }
3230 /**
3231 * e1000e_update_phy_task - work thread to update phy
3232 * @work: pointer to our work struct
3233 *
3234 * this worker thread exists because we must acquire a
3235 * semaphore to read the phy, which we could msleep while
3236 * waiting for it, and we can't msleep in a timer.
3237 **/
3239 {
3243 }
3245 /*
3246 * Need to wait a few seconds after link up to get diagnostic information from
3247 * the phy
3248 */
3250 {
3253 }
3255 /**
3256 * e1000e_update_stats - Update the board statistics counters
3257 * @adapter: board private structure
3258 **/
3260 {
3264 /*
3265 * Prevent stats update while adapter is being reset, or if the pci
3266 * connection is down.
3267 */
3300 /* used for adaptive IFS */
3315 /* Fill out the OS statistics structure */
3319 /* Rx Errors */
3321 /*
3322 * RLEC on some newer hardware can be incorrect so build
3323 * our own version based on RUC and ROC
3324 */
3335 /* Tx Errors */
3342 /* Tx Dropped needs to be maintained elsewhere */
3344 /* Management Stats */
3348 }
3350 /**
3351 * e1000_phy_read_status - Update the PHY register status snapshot
3352 * @adapter: board private structure
3353 **/
3355 {
3373 /*
3374 * Do not read PHY registers if link is not up
3375 * Set values to typical power-on defaults
3376 */
3380 BMSR_ERCAP);
3388 }
3389 }
3392 {
3404 }
3407 {
3412 /*
3413 * get_link_status is set on LSC (link status) interrupt or
3414 * Rx sequence error interrupt. get_link_status will stay
3415 * false until the check_for_link establishes link
3416 * for copper adapters ONLY
3417 */
3425 }
3438 }
3442 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
3444 }
3447 }
3450 {
3451 /* make sure the receive unit is started */
3458 }
3459 }
3461 /**
3462 * e1000_watchdog - Timer Call-back
3463 * @data: pointer to adapter cast into an unsigned long
3464 **/
3466 {
3469 /* Do the rest outside of interrupt context */
3472 /* TODO: make this use queue_delayed_work() */
3473 }
3476 {
3490 }
3499 /* update snapshot of PHY registers on LSC */
3505 /*
3506 * On supported PHYs, check for duplex mismatch only
3507 * if link has autonegotiated at 10/100 half
3508 */
3515 u16 autoneg_exp;
3521 " link partner cannot autoneg. "
3522 " Try forcing full duplex if "
3524 }
3526 /*
3527 * tweak tx_queue_len according to speed/duplex
3528 * and adjust the timeout factor
3529 */
3541 /* maybe add some timeout factor ? */
3543 }
3545 /*
3546 * workaround: re-program speed mode bit after
3547 * link-up event
3548 */
3551 u32 tarc0;
3555 }
3557 /*
3558 * disable TSO for pcie and 10/100 speeds, to avoid
3559 * some hardware issues
3560 */
3574 /* oops */
3576 }
3577 }
3579 /*
3580 * enable transmits in the hardware, need to do this
3581 * after setting TARC(0)
3582 */
3593 }
3607 }
3608 }
3610 link_up:
3629 /*
3630 * We've lost link, so the controller stops DMA,
3631 * but we've got queued Tx work that's never going
3632 * to get done, so reset controller to flush Tx.
3633 * (Do the reset outside of interrupt context).
3634 */
3637 }
3638 }
3640 /* Cause software interrupt to ensure Rx ring is cleaned */
3643 else
3646 /* Force detection of hung controller every watchdog period */
3649 /*
3650 * With 82571 controllers, LAA may be overwritten due to controller
3651 * reset from the other port. Set the appropriate LAA in RAR[0]
3652 */
3656 /* Reset the timer */
3660 }
3662 #define E1000_TX_FLAGS_CSUM 0x00000001
3663 #define E1000_TX_FLAGS_VLAN 0x00000002
3664 #define E1000_TX_FLAGS_TSO 0x00000004
3665 #define E1000_TX_FLAGS_IPV4 0x00000008
3666 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
3667 #define E1000_TX_FLAGS_VLAN_SHIFT 16
3671 {
3686 }
3696 IPPROTO_TCP,
3707 }
3734 i++;
3740 }
3743 }
3746 {
3751 u8 css;
3763 /* XXX not handling all IPV6 headers */
3771 }
3790 i++;
3796 }
3798 #define E1000_MAX_PER_TXD 8192
3799 #define E1000_MAX_TXD_PWR 12
3805 {
3818 /* Workaround for premature desc write-backs
3819 * in TSO mode. Append 4-byte sentinel desc */
3824 /* set time_stamp *before* dma to help avoid a possible race */
3829 size,
3830 PCI_DMA_TODEVICE);
3835 }
3840 count++;
3841 i++;
3844 }
3856 /* Workaround for premature desc write-backs
3857 * in TSO mode. Append 4-byte sentinel desc */
3866 offset,
3867 size,
3868 PCI_DMA_TODEVICE);
3875 }
3881 count++;
3883 i++;
3886 }
3887 }
3891 else
3892 i--;
3898 }
3902 {
3911 E1000_TXD_CMD_TSE;
3916 }
3921 }
3926 }
3938 i++;
3941 }
3945 /*
3946 * Force memory writes to complete before letting h/w
3947 * know there are new descriptors to fetch. (Only
3948 * applicable for weak-ordered memory model archs,
3949 * such as IA-64).
3950 */
3955 /*
3956 * we need this if more than one processor can write to our tail
3957 * at a time, it synchronizes IO on IA64/Altix systems
3958 */
3960 }
3962 #define MINIMUM_DHCP_PACKET_SIZE 282
3965 {
3972 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
3974 }
3982 {
3996 }
3999 }
4002 {
4006 /*
4007 * Herbert's original patch had:
4008 * smp_mb__after_netif_stop_queue();
4009 * but since that doesn't exist yet, just open code it.
4010 */
4013 /*
4014 * We need to check again in a case another CPU has just
4015 * made room available.
4016 */
4020 /* A reprieve! */
4024 }
4027 {
4033 }
4035 #define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
4037 {
4055 }
4060 }
4063 /*
4064 * The controller does a simple calculation to
4065 * make sure there is enough room in the FIFO before
4066 * initiating the DMA for each buffer. The calc is:
4067 * 4 = ceil(buffer len/mss). To make sure we don't
4068 * overrun the FIFO, adjust the max buffer len if mss
4069 * drops.
4070 */
4072 u8 hdr_len;
4076 /*
4077 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
4078 * points to just header, pull a few bytes of payload from
4079 * frags into skb->data
4080 */
4082 /*
4083 * we do this workaround for ES2LAN, but it is un-necessary,
4084 * avoiding it could save a lot of cycles
4085 */
4094 }
4096 }
4097 }
4099 /* reserve a descriptor for the offload context */
4101 count++;
4102 count++;
4109 max_txd_pwr);
4115 /* Collision - tell upper layer to requeue */
4118 /*
4119 * need: count + 2 desc gap to keep tail from touching
4120 * head, otherwise try next time
4121 */
4125 }
4130 }
4139 }
4146 /*
4147 * Old method was to assume IPv4 packet by default if TSO was enabled.
4148 * 82571 hardware supports TSO capabilities for IPv6 as well...
4149 * no longer assume, we must.
4150 */
4156 /* handle pci_map_single() error in e1000_tx_map */
4160 }
4166 /* Make sure there is space in the ring for the next send. */
4171 }
4173 /**
4174 * e1000_tx_timeout - Respond to a Tx Hang
4175 * @netdev: network interface device structure
4176 **/
4178 {
4181 /* Do the reset outside of interrupt context */
4184 }
4187 {
4192 }
4194 /**
4195 * e1000_get_stats - Get System Network Statistics
4196 * @netdev: network interface device structure
4197 *
4198 * Returns the address of the device statistics structure.
4199 * The statistics are actually updated from the timer callback.
4200 **/
4202 {
4205 /* only return the current stats */
4207 }
4209 /**
4210 * e1000_change_mtu - Change the Maximum Transfer Unit
4211 * @netdev: network interface device structure
4212 * @new_mtu: new value for maximum frame size
4213 *
4214 * Returns 0 on success, negative on failure
4215 **/
4217 {
4225 }
4227 /* Jumbo frame size limits */
4232 }
4236 }
4237 }
4239 #define MAX_STD_JUMBO_FRAME_SIZE 9234
4243 }
4247 /* e1000e_down has a dependency on max_frame_size */
4252 /*
4253 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
4254 * means we reserve 2 more, this pushes us to allocate from the next
4255 * larger slab size.
4256 * i.e. RXBUFFER_2048 --> size-4096 slab
4257 * However with the new *_jumbo_rx* routines, jumbo receives will use
4258 * fragmented skbs
4259 */
4269 else
4272 /* adjust allocation if LPE protects us, and we aren't using SBP */
4283 else
4289 }
4293 {
4340 }
4345 }
4347 }
4350 {
4358 }
4359 }
4362 {
4376 }
4391 /* turn on all-multi mode if wake on multicast is enabled */
4396 }
4399 /* advertise wake from D3Cold */
4400 #define E1000_CTRL_ADVD3WUC 0x00100000
4401 /* phy power management enable */
4402 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4404 E1000_CTRL_EN_PHY_PWR_MGMT;
4409 e1000_media_type_internal_serdes) {
4410 /* keep the laser running in D3 */
4414 }
4419 /* Allow time for pending master requests to run */
4431 }
4433 /* make sure adapter isn't asleep if manageability is enabled */
4437 }
4442 /*
4443 * Release control of h/w to f/w. If f/w is AMT enabled, this
4444 * would have already happened in close and is redundant.
4445 */
4453 }
4456 {
4458 u16 val;
4460 /*
4461 * 82573 workaround - disable L1 ASPM on mobile chipsets
4462 *
4463 * L1 ASPM on various mobile (ich7) chipsets do not behave properly
4464 * resulting in lost data or garbage information on the pci-e link
4465 * level. This could result in (false) bad EEPROM checksum errors,
4466 * long ping times (up to 2s) or even a system freeze/hang.
4467 *
4468 * Unfortunately this feature saves about 1W power consumption when
4469 * active.
4470 */
4477 }
4478 }
4480 #ifdef CONFIG_PM
4482 {
4486 u32 err;
4497 }
4509 }
4522 /*
4523 * If the controller has AMT, do not set DRV_LOAD until the interface
4524 * is up. For all other cases, let the f/w know that the h/w is now
4525 * under the control of the driver.
4526 */
4531 }
4532 #endif
4535 {
4537 }
4539 #ifdef CONFIG_NET_POLL_CONTROLLER
4540 /*
4541 * Polling 'interrupt' - used by things like netconsole to send skbs
4542 * without having to re-enable interrupts. It's not called while
4543 * the interrupt routine is executing.
4544 */
4546 {
4553 }
4554 #endif
4556 /**
4557 * e1000_io_error_detected - called when PCI error is detected
4558 * @pdev: Pointer to PCI device
4559 * @state: The current pci connection state
4560 *
4561 * This function is called after a PCI bus error affecting
4562 * this device has been detected.
4563 */
4565 pci_channel_state_t state)
4566 {
4576 /* Request a slot slot reset. */
4578 }
4580 /**
4581 * e1000_io_slot_reset - called after the pci bus has been reset.
4582 * @pdev: Pointer to PCI device
4583 *
4584 * Restart the card from scratch, as if from a cold-boot. Implementation
4585 * resembles the first-half of the e1000_resume routine.
4586 */
4588 {
4600 }
4611 }
4613 /**
4614 * e1000_io_resume - called when traffic can start flowing again.
4615 * @pdev: Pointer to PCI device
4616 *
4617 * This callback is called when the error recovery driver tells us that
4618 * its OK to resume normal operation. Implementation resembles the
4619 * second-half of the e1000_resume routine.
4620 */
4622 {
4633 }
4634 }
4638 /*
4639 * If the controller has AMT, do not set DRV_LOAD until the interface
4640 * is up. For all other cases, let the f/w know that the h/w is now
4641 * under the control of the driver.
4642 */
4646 }
4649 {
4652 u32 pba_num;
4654 /* print bus type/speed/width info */
4656 /* bus width */
4659 /* MAC address */
4668 }
4671 {
4681 /* Deep Smart Power Down (DSPD) */
4684 }
4688 /* ASPM enable */
4691 }
4692 }
4694 /**
4695 * e1000_probe - Device Initialization Routine
4696 * @pdev: PCI device information struct
4697 * @ent: entry in e1000_pci_tbl
4698 *
4699 * Returns 0 on success, negative on failure
4700 *
4701 * e1000_probe initializes an adapter identified by a pci_dev structure.
4702 * The OS initialization, configuring of the adapter private structure,
4703 * and a hardware reset occur.
4704 **/
4707 {
4736 DMA_32BIT_MASK);
4741 }
4742 }
4743 }
4747 e1000e_driver_name);
4788 }
4790 /* construct the net_device struct */
4806 #ifdef CONFIG_NET_POLL_CONTROLLER
4808 #endif
4818 /* setup adapter struct */
4841 /* Copper options */
4846 }
4852 NETIF_F_HW_CSUM |
4853 NETIF_F_HW_VLAN_TX |
4854 NETIF_F_HW_VLAN_RX;
4870 /*
4871 * We should not be using LLTX anymore, but we are still Tx faster with
4872 * it.
4873 */
4879 /*
4880 * before reading the NVM, reset the controller to
4881 * put the device in a known good starting state
4882 */
4885 /*
4886 * systems with ASPM and others may see the checksum fail on the first
4887 * attempt. Let's give it a few tries
4888 */
4896 }
4897 }
4901 /* copy the MAC address out of the NVM */
4915 }
4930 /* Initialize link parameters. User can change them with ethtool */
4937 /* ring size defaults */
4941 /*
4942 * Initial Wake on LAN setting - If APM wake is enabled in
4943 * the EEPROM, enable the ACPI Magic Packet filter
4944 */
4946 /* APME bit in EEPROM is mapped to WUC.APME */
4954 else
4957 }
4959 /* fetch WoL from EEPROM */
4963 /*
4964 * now that we have the eeprom settings, apply the special cases
4965 * where the eeprom may be wrong or the board simply won't support
4966 * wake on lan on a particular port
4967 */
4971 /* initialize the wol settings based on the eeprom settings */
4975 /* reset the hardware with the new settings */
4978 /*
4979 * If the controller has AMT, do not set DRV_LOAD until the interface
4980 * is up. For all other cases, let the f/w know that the h/w is now
4981 * under the control of the driver.
4982 */
4986 /* tell the stack to leave us alone until e1000_open() is called */
4999 err_register:
5002 err_eeprom:
5005 err_hw_init:
5009 err_sw_init:
5012 err_flashmap:
5014 err_ioremap:
5016 err_alloc_etherdev:
5019 err_pci_reg:
5020 err_dma:
5023 }
5025 /**
5026 * e1000_remove - Device Removal Routine
5027 * @pdev: PCI device information struct
5028 *
5029 * e1000_remove is called by the PCI subsystem to alert the driver
5030 * that it should release a PCI device. The could be caused by a
5031 * Hot-Plug event, or because the driver is going to be removed from
5032 * memory.
5033 **/
5035 {
5039 /*
5040 * flush_scheduled work may reschedule our watchdog task, so
5041 * explicitly disable watchdog tasks from being rescheduled
5042 */
5049 /*
5050 * Release control of h/w to f/w. If f/w is AMT enabled, this
5051 * would have already happened in close and is redundant.
5052 */
5073 }
5075 /* PCI Error Recovery (ERS) */
5080 };
5105 board_80003es2lan },
5107 board_80003es2lan },
5109 board_80003es2lan },
5111 board_80003es2lan },
5139 };
5142 /* PCI Device API Driver */
5148 #ifdef CONFIG_PM
5149 /* Power Management Hooks */
5152 #endif
5155 };
5157 /**
5158 * e1000_init_module - Driver Registration Routine
5159 *
5160 * e1000_init_module is the first routine called when the driver is
5161 * loaded. All it does is register with the PCI subsystem.
5162 **/
5164 {
5169 e1000e_driver_name);
5172 PM_QOS_DEFAULT_VALUE);
5175 }
5178 /**
5179 * e1000_exit_module - Driver Exit Cleanup Routine
5180 *
5181 * e1000_exit_module is called just before the driver is removed
5182 * from memory.
5183 **/
5185 {
5188 }
5197 /* e1000_main.c */