?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
fec: use linux/*.h instead of asm/*.h
[linux-2.6/mini2440.git] / drivers / net / fec.c
bloba44b4eef180895262ae1a50d8f625557b82f8d3e
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
39 #include <linux/io.h>
40 #include <linux/irq.h>
41
42 #include <asm/cacheflush.h>
43 #include <asm/coldfire.h>
44 #include <asm/mcfsim.h>
45
46 #include "fec.h"
47
48 #if defined(CONFIG_FEC2)
49 #define FEC_MAX_PORTS 2
50 #else
51 #define FEC_MAX_PORTS 1
52 #endif
53
54 #if defined(CONFIG_M5272)
55 #define HAVE_mii_link_interrupt
56 #endif
57
58 /*
59 * Define the fixed address of the FEC hardware.
60 */
61 static unsigned int fec_hw[] = {
62 #if defined(CONFIG_M5272)
63 (MCF_MBAR + 0x840),
64 #elif defined(CONFIG_M527x)
65 (MCF_MBAR + 0x1000),
66 (MCF_MBAR + 0x1800),
67 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
68 (MCF_MBAR + 0x1000),
69 #elif defined(CONFIG_M520x)
70 (MCF_MBAR+0x30000),
71 #elif defined(CONFIG_M532x)
72 (MCF_MBAR+0xfc030000),
73 #endif
74 };
75
76 static unsigned char fec_mac_default[] = {
77 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
78 };
79
80 /*
81 * Some hardware gets it MAC address out of local flash memory.
82 * if this is non-zero then assume it is the address to get MAC from.
83 */
84 #if defined(CONFIG_NETtel)
85 #define FEC_FLASHMAC 0xf0006006
86 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
87 #define FEC_FLASHMAC 0xf0006000
88 #elif defined(CONFIG_CANCam)
89 #define FEC_FLASHMAC 0xf0020000
90 #elif defined (CONFIG_M5272C3)
91 #define FEC_FLASHMAC (0xffe04000 + 4)
92 #elif defined(CONFIG_MOD5272)
93 #define FEC_FLASHMAC 0xffc0406b
94 #else
95 #define FEC_FLASHMAC 0
96 #endif
97
98 /* Forward declarations of some structures to support different PHYs
99 */
100
101 typedef struct {
102 uint mii_data;
103 void (*funct)(uint mii_reg, struct net_device *dev);
104 } phy_cmd_t;
105
106 typedef struct {
107 uint id;
108 char *name;
109
110 const phy_cmd_t *config;
111 const phy_cmd_t *startup;
112 const phy_cmd_t *ack_int;
113 const phy_cmd_t *shutdown;
114 } phy_info_t;
115
116 /* The number of Tx and Rx buffers. These are allocated from the page
117 * pool. The code may assume these are power of two, so it it best
118 * to keep them that size.
119 * We don't need to allocate pages for the transmitter. We just use
120 * the skbuffer directly.
121 */
122 #define FEC_ENET_RX_PAGES 8
123 #define FEC_ENET_RX_FRSIZE 2048
124 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
125 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
126 #define FEC_ENET_TX_FRSIZE 2048
127 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
128 #define TX_RING_SIZE 16 /* Must be power of two */
129 #define TX_RING_MOD_MASK 15 /* for this to work */
130
131 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
132 #error "FEC: descriptor ring size constants too large"
133 #endif
134
135 /* Interrupt events/masks.
136 */
137 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
138 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
139 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
140 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
141 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
142 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
143 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
144 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
145 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
146 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
147
148 /* The FEC stores dest/src/type, data, and checksum for receive packets.
149 */
150 #define PKT_MAXBUF_SIZE 1518
151 #define PKT_MINBUF_SIZE 64
152 #define PKT_MAXBLR_SIZE 1520
153
154
155 /*
156 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
157 * size bits. Other FEC hardware does not, so we need to take that into
158 * account when setting it.
159 */
160 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
161 defined(CONFIG_M520x) || defined(CONFIG_M532x)
162 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
163 #else
164 #define OPT_FRAME_SIZE 0
165 #endif
166
167 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
168 * tx_bd_base always point to the base of the buffer descriptors. The
169 * cur_rx and cur_tx point to the currently available buffer.
170 * The dirty_tx tracks the current buffer that is being sent by the
171 * controller. The cur_tx and dirty_tx are equal under both completely
172 * empty and completely full conditions. The empty/ready indicator in
173 * the buffer descriptor determines the actual condition.
174 */
175 struct fec_enet_private {
176 /* Hardware registers of the FEC device */
177 volatile fec_t *hwp;
178
179 struct net_device *netdev;
180
181 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
182 unsigned char *tx_bounce[TX_RING_SIZE];
183 struct sk_buff* tx_skbuff[TX_RING_SIZE];
184 ushort skb_cur;
185 ushort skb_dirty;
186
187 /* CPM dual port RAM relative addresses.
188 */
189 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
190 cbd_t *tx_bd_base;
191 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
192 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
193 uint tx_full;
194 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
195 spinlock_t hw_lock;
196 /* hold while accessing the mii_list_t() elements */
197 spinlock_t mii_lock;
198
199 uint phy_id;
200 uint phy_id_done;
201 uint phy_status;
202 uint phy_speed;
203 phy_info_t const *phy;
204 struct work_struct phy_task;
205
206 uint sequence_done;
207 uint mii_phy_task_queued;
208
209 uint phy_addr;
210
211 int index;
212 int opened;
213 int link;
214 int old_link;
215 int full_duplex;
216 };
217
218 static int fec_enet_open(struct net_device *dev);
219 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
220 static void fec_enet_mii(struct net_device *dev);
221 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
222 static void fec_enet_tx(struct net_device *dev);
223 static void fec_enet_rx(struct net_device *dev);
224 static int fec_enet_close(struct net_device *dev);
225 static void set_multicast_list(struct net_device *dev);
226 static void fec_restart(struct net_device *dev, int duplex);
227 static void fec_stop(struct net_device *dev);
228 static void fec_set_mac_address(struct net_device *dev);
229
230
231 /* MII processing. We keep this as simple as possible. Requests are
232 * placed on the list (if there is room). When the request is finished
233 * by the MII, an optional function may be called.
234 */
235 typedef struct mii_list {
236 uint mii_regval;
237 void (*mii_func)(uint val, struct net_device *dev);
238 struct mii_list *mii_next;
239 } mii_list_t;
240
241 #define NMII 20
242 static mii_list_t mii_cmds[NMII];
243 static mii_list_t *mii_free;
244 static mii_list_t *mii_head;
245 static mii_list_t *mii_tail;
246
247 static int mii_queue(struct net_device *dev, int request,
248 void (*func)(uint, struct net_device *));
249
250 /* Make MII read/write commands for the FEC.
251 */
252 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
253 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
254 (VAL & 0xffff))
255 #define mk_mii_end 0
256
257 /* Transmitter timeout.
258 */
259 #define TX_TIMEOUT (2*HZ)
260
261 /* Register definitions for the PHY.
262 */
263
264 #define MII_REG_CR 0 /* Control Register */
265 #define MII_REG_SR 1 /* Status Register */
266 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
267 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
268 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
269 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
270 #define MII_REG_ANER 6 /* A-N Expansion Register */
271 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
272 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
273
274 /* values for phy_status */
275
276 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
277 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
278 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
279 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
280 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
281 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
282 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
283
284 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
285 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
286 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
287 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
288 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
289 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
290 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
291 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
292
293
294 static int
295 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
296 {
297 struct fec_enet_private *fep;
298 volatile fec_t *fecp;
299 volatile cbd_t *bdp;
300 unsigned short status;
301 unsigned long flags;
302
303 fep = netdev_priv(dev);
304 fecp = (volatile fec_t*)dev->base_addr;
305
306 if (!fep->link) {
307 /* Link is down or autonegotiation is in progress. */
308 return 1;
309 }
310
311 spin_lock_irqsave(&fep->hw_lock, flags);
312 /* Fill in a Tx ring entry */
313 bdp = fep->cur_tx;
314
315 status = bdp->cbd_sc;
316 #ifndef final_version
317 if (status & BD_ENET_TX_READY) {
318 /* Ooops. All transmit buffers are full. Bail out.
319 * This should not happen, since dev->tbusy should be set.
320 */
321 printk("%s: tx queue full!.\n", dev->name);
322 spin_unlock_irqrestore(&fep->hw_lock, flags);
323 return 1;
324 }
325 #endif
326
327 /* Clear all of the status flags.
328 */
329 status &= ~BD_ENET_TX_STATS;
330
331 /* Set buffer length and buffer pointer.
332 */
333 bdp->cbd_bufaddr = __pa(skb->data);
334 bdp->cbd_datlen = skb->len;
335
336 /*
337 * On some FEC implementations data must be aligned on
338 * 4-byte boundaries. Use bounce buffers to copy data
339 * and get it aligned. Ugh.
340 */
341 if (bdp->cbd_bufaddr & 0x3) {
342 unsigned int index;
343 index = bdp - fep->tx_bd_base;
344 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
345 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
346 }
347
348 /* Save skb pointer.
349 */
350 fep->tx_skbuff[fep->skb_cur] = skb;
351
352 dev->stats.tx_bytes += skb->len;
353 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
354
355 /* Push the data cache so the CPM does not get stale memory
356 * data.
357 */
358 flush_dcache_range((unsigned long)skb->data,
359 (unsigned long)skb->data + skb->len);
360
361 /* Send it on its way. Tell FEC it's ready, interrupt when done,
362 * it's the last BD of the frame, and to put the CRC on the end.
363 */
364
365 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
366 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
367 bdp->cbd_sc = status;
368
369 dev->trans_start = jiffies;
370
371 /* Trigger transmission start */
372 fecp->fec_x_des_active = 0;
373
374 /* If this was the last BD in the ring, start at the beginning again.
375 */
376 if (status & BD_ENET_TX_WRAP) {
377 bdp = fep->tx_bd_base;
378 } else {
379 bdp++;
380 }
381
382 if (bdp == fep->dirty_tx) {
383 fep->tx_full = 1;
384 netif_stop_queue(dev);
385 }
386
387 fep->cur_tx = (cbd_t *)bdp;
388
389 spin_unlock_irqrestore(&fep->hw_lock, flags);
390
391 return 0;
392 }
393
394 static void
395 fec_timeout(struct net_device *dev)
396 {
397 struct fec_enet_private *fep = netdev_priv(dev);
398
399 printk("%s: transmit timed out.\n", dev->name);
400 dev->stats.tx_errors++;
401 #ifndef final_version
402 {
403 int i;
404 cbd_t *bdp;
405
406 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
407 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
408 (unsigned long)fep->dirty_tx,
409 (unsigned long)fep->cur_rx);
410
411 bdp = fep->tx_bd_base;
412 printk(" tx: %u buffers\n", TX_RING_SIZE);
413 for (i = 0 ; i < TX_RING_SIZE; i++) {
414 printk(" %08x: %04x %04x %08x\n",
415 (uint) bdp,
416 bdp->cbd_sc,
417 bdp->cbd_datlen,
418 (int) bdp->cbd_bufaddr);
419 bdp++;
420 }
421
422 bdp = fep->rx_bd_base;
423 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
424 for (i = 0 ; i < RX_RING_SIZE; i++) {
425 printk(" %08x: %04x %04x %08x\n",
426 (uint) bdp,
427 bdp->cbd_sc,
428 bdp->cbd_datlen,
429 (int) bdp->cbd_bufaddr);
430 bdp++;
431 }
432 }
433 #endif
434 fec_restart(dev, fep->full_duplex);
435 netif_wake_queue(dev);
436 }
437
438 /* The interrupt handler.
439 * This is called from the MPC core interrupt.
440 */
441 static irqreturn_t
442 fec_enet_interrupt(int irq, void * dev_id)
443 {
444 struct net_device *dev = dev_id;
445 volatile fec_t *fecp;
446 uint int_events;
447 irqreturn_t ret = IRQ_NONE;
448
449 fecp = (volatile fec_t*)dev->base_addr;
450
451 /* Get the interrupt events that caused us to be here.
452 */
453 do {
454 int_events = fecp->fec_ievent;
455 fecp->fec_ievent = int_events;
456
457 /* Handle receive event in its own function.
458 */
459 if (int_events & FEC_ENET_RXF) {
460 ret = IRQ_HANDLED;
461 fec_enet_rx(dev);
462 }
463
464 /* Transmit OK, or non-fatal error. Update the buffer
465 descriptors. FEC handles all errors, we just discover
466 them as part of the transmit process.
467 */
468 if (int_events & FEC_ENET_TXF) {
469 ret = IRQ_HANDLED;
470 fec_enet_tx(dev);
471 }
472
473 if (int_events & FEC_ENET_MII) {
474 ret = IRQ_HANDLED;
475 fec_enet_mii(dev);
476 }
477
478 } while (int_events);
479
480 return ret;
481 }
482
483
484 static void
485 fec_enet_tx(struct net_device *dev)
486 {
487 struct fec_enet_private *fep;
488 volatile cbd_t *bdp;
489 unsigned short status;
490 struct sk_buff *skb;
491
492 fep = netdev_priv(dev);
493 spin_lock_irq(&fep->hw_lock);
494 bdp = fep->dirty_tx;
495
496 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
497 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
498
499 skb = fep->tx_skbuff[fep->skb_dirty];
500 /* Check for errors. */
501 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
502 BD_ENET_TX_RL | BD_ENET_TX_UN |
503 BD_ENET_TX_CSL)) {
504 dev->stats.tx_errors++;
505 if (status & BD_ENET_TX_HB) /* No heartbeat */
506 dev->stats.tx_heartbeat_errors++;
507 if (status & BD_ENET_TX_LC) /* Late collision */
508 dev->stats.tx_window_errors++;
509 if (status & BD_ENET_TX_RL) /* Retrans limit */
510 dev->stats.tx_aborted_errors++;
511 if (status & BD_ENET_TX_UN) /* Underrun */
512 dev->stats.tx_fifo_errors++;
513 if (status & BD_ENET_TX_CSL) /* Carrier lost */
514 dev->stats.tx_carrier_errors++;
515 } else {
516 dev->stats.tx_packets++;
517 }
518
519 #ifndef final_version
520 if (status & BD_ENET_TX_READY)
521 printk("HEY! Enet xmit interrupt and TX_READY.\n");
522 #endif
523 /* Deferred means some collisions occurred during transmit,
524 * but we eventually sent the packet OK.
525 */
526 if (status & BD_ENET_TX_DEF)
527 dev->stats.collisions++;
528
529 /* Free the sk buffer associated with this last transmit.
530 */
531 dev_kfree_skb_any(skb);
532 fep->tx_skbuff[fep->skb_dirty] = NULL;
533 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
534
535 /* Update pointer to next buffer descriptor to be transmitted.
536 */
537 if (status & BD_ENET_TX_WRAP)
538 bdp = fep->tx_bd_base;
539 else
540 bdp++;
541
542 /* Since we have freed up a buffer, the ring is no longer
543 * full.
544 */
545 if (fep->tx_full) {
546 fep->tx_full = 0;
547 if (netif_queue_stopped(dev))
548 netif_wake_queue(dev);
549 }
550 }
551 fep->dirty_tx = (cbd_t *)bdp;
552 spin_unlock_irq(&fep->hw_lock);
553 }
554
555
556 /* During a receive, the cur_rx points to the current incoming buffer.
557 * When we update through the ring, if the next incoming buffer has
558 * not been given to the system, we just set the empty indicator,
559 * effectively tossing the packet.
560 */
561 static void
562 fec_enet_rx(struct net_device *dev)
563 {
564 struct fec_enet_private *fep;
565 volatile fec_t *fecp;
566 volatile cbd_t *bdp;
567 unsigned short status;
568 struct sk_buff *skb;
569 ushort pkt_len;
570 __u8 *data;
571
572 #ifdef CONFIG_M532x
573 flush_cache_all();
574 #endif
575
576 fep = netdev_priv(dev);
577 fecp = (volatile fec_t*)dev->base_addr;
578
579 spin_lock_irq(&fep->hw_lock);
580
581 /* First, grab all of the stats for the incoming packet.
582 * These get messed up if we get called due to a busy condition.
583 */
584 bdp = fep->cur_rx;
585
586 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
587
588 #ifndef final_version
589 /* Since we have allocated space to hold a complete frame,
590 * the last indicator should be set.
591 */
592 if ((status & BD_ENET_RX_LAST) == 0)
593 printk("FEC ENET: rcv is not +last\n");
594 #endif
595
596 if (!fep->opened)
597 goto rx_processing_done;
598
599 /* Check for errors. */
600 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
601 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
602 dev->stats.rx_errors++;
603 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
604 /* Frame too long or too short. */
605 dev->stats.rx_length_errors++;
606 }
607 if (status & BD_ENET_RX_NO) /* Frame alignment */
608 dev->stats.rx_frame_errors++;
609 if (status & BD_ENET_RX_CR) /* CRC Error */
610 dev->stats.rx_crc_errors++;
611 if (status & BD_ENET_RX_OV) /* FIFO overrun */
612 dev->stats.rx_fifo_errors++;
613 }
614
615 /* Report late collisions as a frame error.
616 * On this error, the BD is closed, but we don't know what we
617 * have in the buffer. So, just drop this frame on the floor.
618 */
619 if (status & BD_ENET_RX_CL) {
620 dev->stats.rx_errors++;
621 dev->stats.rx_frame_errors++;
622 goto rx_processing_done;
623 }
624
625 /* Process the incoming frame.
626 */
627 dev->stats.rx_packets++;
628 pkt_len = bdp->cbd_datlen;
629 dev->stats.rx_bytes += pkt_len;
630 data = (__u8*)__va(bdp->cbd_bufaddr);
631
632 /* This does 16 byte alignment, exactly what we need.
633 * The packet length includes FCS, but we don't want to
634 * include that when passing upstream as it messes up
635 * bridging applications.
636 */
637 skb = dev_alloc_skb(pkt_len-4);
638
639 if (skb == NULL) {
640 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
641 dev->stats.rx_dropped++;
642 } else {
643 skb_put(skb,pkt_len-4); /* Make room */
644 skb_copy_to_linear_data(skb, data, pkt_len-4);
645 skb->protocol=eth_type_trans(skb,dev);
646 netif_rx(skb);
647 }
648 rx_processing_done:
649
650 /* Clear the status flags for this buffer.
651 */
652 status &= ~BD_ENET_RX_STATS;
653
654 /* Mark the buffer empty.
655 */
656 status |= BD_ENET_RX_EMPTY;
657 bdp->cbd_sc = status;
658
659 /* Update BD pointer to next entry.
660 */
661 if (status & BD_ENET_RX_WRAP)
662 bdp = fep->rx_bd_base;
663 else
664 bdp++;
665
666 #if 1
667 /* Doing this here will keep the FEC running while we process
668 * incoming frames. On a heavily loaded network, we should be
669 * able to keep up at the expense of system resources.
670 */
671 fecp->fec_r_des_active = 0;
672 #endif
673 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
674 fep->cur_rx = (cbd_t *)bdp;
675
676 #if 0
677 /* Doing this here will allow us to process all frames in the
678 * ring before the FEC is allowed to put more there. On a heavily
679 * loaded network, some frames may be lost. Unfortunately, this
680 * increases the interrupt overhead since we can potentially work
681 * our way back to the interrupt return only to come right back
682 * here.
683 */
684 fecp->fec_r_des_active = 0;
685 #endif
686
687 spin_unlock_irq(&fep->hw_lock);
688 }
689
690
691 /* called from interrupt context */
692 static void
693 fec_enet_mii(struct net_device *dev)
694 {
695 struct fec_enet_private *fep;
696 volatile fec_t *ep;
697 mii_list_t *mip;
698 uint mii_reg;
699
700 fep = netdev_priv(dev);
701 spin_lock_irq(&fep->mii_lock);
702
703 ep = fep->hwp;
704 mii_reg = ep->fec_mii_data;
705
706 if ((mip = mii_head) == NULL) {
707 printk("MII and no head!\n");
708 goto unlock;
709 }
710
711 if (mip->mii_func != NULL)
712 (*(mip->mii_func))(mii_reg, dev);
713
714 mii_head = mip->mii_next;
715 mip->mii_next = mii_free;
716 mii_free = mip;
717
718 if ((mip = mii_head) != NULL)
719 ep->fec_mii_data = mip->mii_regval;
720
721 unlock:
722 spin_unlock_irq(&fep->mii_lock);
723 }
724
725 static int
726 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
727 {
728 struct fec_enet_private *fep;
729 unsigned long flags;
730 mii_list_t *mip;
731 int retval;
732
733 /* Add PHY address to register command.
734 */
735 fep = netdev_priv(dev);
736 spin_lock_irqsave(&fep->mii_lock, flags);
737
738 regval |= fep->phy_addr << 23;
739 retval = 0;
740
741 if ((mip = mii_free) != NULL) {
742 mii_free = mip->mii_next;
743 mip->mii_regval = regval;
744 mip->mii_func = func;
745 mip->mii_next = NULL;
746 if (mii_head) {
747 mii_tail->mii_next = mip;
748 mii_tail = mip;
749 } else {
750 mii_head = mii_tail = mip;
751 fep->hwp->fec_mii_data = regval;
752 }
753 } else {
754 retval = 1;
755 }
756
757 spin_unlock_irqrestore(&fep->mii_lock, flags);
758 return retval;
759 }
760
761 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
762 {
763 if(!c)
764 return;
765
766 for (; c->mii_data != mk_mii_end; c++)
767 mii_queue(dev, c->mii_data, c->funct);
768 }
769
770 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
771 {
772 struct fec_enet_private *fep = netdev_priv(dev);
773 volatile uint *s = &(fep->phy_status);
774 uint status;
775
776 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
777
778 if (mii_reg & 0x0004)
779 status |= PHY_STAT_LINK;
780 if (mii_reg & 0x0010)
781 status |= PHY_STAT_FAULT;
782 if (mii_reg & 0x0020)
783 status |= PHY_STAT_ANC;
784 *s = status;
785 }
786
787 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
788 {
789 struct fec_enet_private *fep = netdev_priv(dev);
790 volatile uint *s = &(fep->phy_status);
791 uint status;
792
793 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
794
795 if (mii_reg & 0x1000)
796 status |= PHY_CONF_ANE;
797 if (mii_reg & 0x4000)
798 status |= PHY_CONF_LOOP;
799 *s = status;
800 }
801
802 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
803 {
804 struct fec_enet_private *fep = netdev_priv(dev);
805 volatile uint *s = &(fep->phy_status);
806 uint status;
807
808 status = *s & ~(PHY_CONF_SPMASK);
809
810 if (mii_reg & 0x0020)
811 status |= PHY_CONF_10HDX;
812 if (mii_reg & 0x0040)
813 status |= PHY_CONF_10FDX;
814 if (mii_reg & 0x0080)
815 status |= PHY_CONF_100HDX;
816 if (mii_reg & 0x00100)
817 status |= PHY_CONF_100FDX;
818 *s = status;
819 }
820
821 /* ------------------------------------------------------------------------- */
822 /* The Level one LXT970 is used by many boards */
823
824 #define MII_LXT970_MIRROR 16 /* Mirror register */
825 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
826 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
827 #define MII_LXT970_CONFIG 19 /* Configuration Register */
828 #define MII_LXT970_CSR 20 /* Chip Status Register */
829
830 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
831 {
832 struct fec_enet_private *fep = netdev_priv(dev);
833 volatile uint *s = &(fep->phy_status);
834 uint status;
835
836 status = *s & ~(PHY_STAT_SPMASK);
837 if (mii_reg & 0x0800) {
838 if (mii_reg & 0x1000)
839 status |= PHY_STAT_100FDX;
840 else
841 status |= PHY_STAT_100HDX;
842 } else {
843 if (mii_reg & 0x1000)
844 status |= PHY_STAT_10FDX;
845 else
846 status |= PHY_STAT_10HDX;
847 }
848 *s = status;
849 }
850
851 static phy_cmd_t const phy_cmd_lxt970_config[] = {
852 { mk_mii_read(MII_REG_CR), mii_parse_cr },
853 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
854 { mk_mii_end, }
855 };
856 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
857 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
858 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
859 { mk_mii_end, }
860 };
861 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
862 /* read SR and ISR to acknowledge */
863 { mk_mii_read(MII_REG_SR), mii_parse_sr },
864 { mk_mii_read(MII_LXT970_ISR), NULL },
865
866 /* find out the current status */
867 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
868 { mk_mii_end, }
869 };
870 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
871 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
872 { mk_mii_end, }
873 };
874 static phy_info_t const phy_info_lxt970 = {
875 .id = 0x07810000,
876 .name = "LXT970",
877 .config = phy_cmd_lxt970_config,
878 .startup = phy_cmd_lxt970_startup,
879 .ack_int = phy_cmd_lxt970_ack_int,
880 .shutdown = phy_cmd_lxt970_shutdown
881 };
882
883 /* ------------------------------------------------------------------------- */
884 /* The Level one LXT971 is used on some of my custom boards */
885
886 /* register definitions for the 971 */
887
888 #define MII_LXT971_PCR 16 /* Port Control Register */
889 #define MII_LXT971_SR2 17 /* Status Register 2 */
890 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
891 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
892 #define MII_LXT971_LCR 20 /* LED Control Register */
893 #define MII_LXT971_TCR 30 /* Transmit Control Register */
894
895 /*
896 * I had some nice ideas of running the MDIO faster...
897 * The 971 should support 8MHz and I tried it, but things acted really
898 * weird, so 2.5 MHz ought to be enough for anyone...
899 */
900
901 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
902 {
903 struct fec_enet_private *fep = netdev_priv(dev);
904 volatile uint *s = &(fep->phy_status);
905 uint status;
906
907 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
908
909 if (mii_reg & 0x0400) {
910 fep->link = 1;
911 status |= PHY_STAT_LINK;
912 } else {
913 fep->link = 0;
914 }
915 if (mii_reg & 0x0080)
916 status |= PHY_STAT_ANC;
917 if (mii_reg & 0x4000) {
918 if (mii_reg & 0x0200)
919 status |= PHY_STAT_100FDX;
920 else
921 status |= PHY_STAT_100HDX;
922 } else {
923 if (mii_reg & 0x0200)
924 status |= PHY_STAT_10FDX;
925 else
926 status |= PHY_STAT_10HDX;
927 }
928 if (mii_reg & 0x0008)
929 status |= PHY_STAT_FAULT;
930
931 *s = status;
932 }
933
934 static phy_cmd_t const phy_cmd_lxt971_config[] = {
935 /* limit to 10MBit because my prototype board
936 * doesn't work with 100. */
937 { mk_mii_read(MII_REG_CR), mii_parse_cr },
938 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
939 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
940 { mk_mii_end, }
941 };
942 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
943 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
944 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
945 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
946 /* Somehow does the 971 tell me that the link is down
947 * the first read after power-up.
948 * read here to get a valid value in ack_int */
949 { mk_mii_read(MII_REG_SR), mii_parse_sr },
950 { mk_mii_end, }
951 };
952 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
953 /* acknowledge the int before reading status ! */
954 { mk_mii_read(MII_LXT971_ISR), NULL },
955 /* find out the current status */
956 { mk_mii_read(MII_REG_SR), mii_parse_sr },
957 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
958 { mk_mii_end, }
959 };
960 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
961 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
962 { mk_mii_end, }
963 };
964 static phy_info_t const phy_info_lxt971 = {
965 .id = 0x0001378e,
966 .name = "LXT971",
967 .config = phy_cmd_lxt971_config,
968 .startup = phy_cmd_lxt971_startup,
969 .ack_int = phy_cmd_lxt971_ack_int,
970 .shutdown = phy_cmd_lxt971_shutdown
971 };
972
973 /* ------------------------------------------------------------------------- */
974 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
975
976 /* register definitions */
977
978 #define MII_QS6612_MCR 17 /* Mode Control Register */
979 #define MII_QS6612_FTR 27 /* Factory Test Register */
980 #define MII_QS6612_MCO 28 /* Misc. Control Register */
981 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
982 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
983 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
984
985 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
986 {
987 struct fec_enet_private *fep = netdev_priv(dev);
988 volatile uint *s = &(fep->phy_status);
989 uint status;
990
991 status = *s & ~(PHY_STAT_SPMASK);
992
993 switch((mii_reg >> 2) & 7) {
994 case 1: status |= PHY_STAT_10HDX; break;
995 case 2: status |= PHY_STAT_100HDX; break;
996 case 5: status |= PHY_STAT_10FDX; break;
997 case 6: status |= PHY_STAT_100FDX; break;
998 }
999
1000 *s = status;
1001 }
1002
1003 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1004 /* The PHY powers up isolated on the RPX,
1005 * so send a command to allow operation.
1006 */
1007 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1008
1009 /* parse cr and anar to get some info */
1010 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1011 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1012 { mk_mii_end, }
1013 };
1014 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1015 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1016 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1017 { mk_mii_end, }
1018 };
1019 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1020 /* we need to read ISR, SR and ANER to acknowledge */
1021 { mk_mii_read(MII_QS6612_ISR), NULL },
1022 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1023 { mk_mii_read(MII_REG_ANER), NULL },
1024
1025 /* read pcr to get info */
1026 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1027 { mk_mii_end, }
1028 };
1029 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1030 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1031 { mk_mii_end, }
1032 };
1033 static phy_info_t const phy_info_qs6612 = {
1034 .id = 0x00181440,
1035 .name = "QS6612",
1036 .config = phy_cmd_qs6612_config,
1037 .startup = phy_cmd_qs6612_startup,
1038 .ack_int = phy_cmd_qs6612_ack_int,
1039 .shutdown = phy_cmd_qs6612_shutdown
1040 };
1041
1042 /* ------------------------------------------------------------------------- */
1043 /* AMD AM79C874 phy */
1044
1045 /* register definitions for the 874 */
1046
1047 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1048 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1049 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1050 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1051 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1052 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1053 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1054
1055 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1056 {
1057 struct fec_enet_private *fep = netdev_priv(dev);
1058 volatile uint *s = &(fep->phy_status);
1059 uint status;
1060
1061 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1062
1063 if (mii_reg & 0x0080)
1064 status |= PHY_STAT_ANC;
1065 if (mii_reg & 0x0400)
1066 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1067 else
1068 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1069
1070 *s = status;
1071 }
1072
1073 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1074 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1075 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1076 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1077 { mk_mii_end, }
1078 };
1079 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1080 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1081 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1082 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1083 { mk_mii_end, }
1084 };
1085 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1086 /* find out the current status */
1087 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1088 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1089 /* we only need to read ISR to acknowledge */
1090 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1091 { mk_mii_end, }
1092 };
1093 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1094 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1095 { mk_mii_end, }
1096 };
1097 static phy_info_t const phy_info_am79c874 = {
1098 .id = 0x00022561,
1099 .name = "AM79C874",
1100 .config = phy_cmd_am79c874_config,
1101 .startup = phy_cmd_am79c874_startup,
1102 .ack_int = phy_cmd_am79c874_ack_int,
1103 .shutdown = phy_cmd_am79c874_shutdown
1104 };
1105
1106
1107 /* ------------------------------------------------------------------------- */
1108 /* Kendin KS8721BL phy */
1109
1110 /* register definitions for the 8721 */
1111
1112 #define MII_KS8721BL_RXERCR 21
1113 #define MII_KS8721BL_ICSR 22
1114 #define MII_KS8721BL_PHYCR 31
1115
1116 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1117 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1118 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1119 { mk_mii_end, }
1120 };
1121 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1122 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1123 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1124 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1125 { mk_mii_end, }
1126 };
1127 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1128 /* find out the current status */
1129 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1130 /* we only need to read ISR to acknowledge */
1131 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1132 { mk_mii_end, }
1133 };
1134 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1135 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1136 { mk_mii_end, }
1137 };
1138 static phy_info_t const phy_info_ks8721bl = {
1139 .id = 0x00022161,
1140 .name = "KS8721BL",
1141 .config = phy_cmd_ks8721bl_config,
1142 .startup = phy_cmd_ks8721bl_startup,
1143 .ack_int = phy_cmd_ks8721bl_ack_int,
1144 .shutdown = phy_cmd_ks8721bl_shutdown
1145 };
1146
1147 /* ------------------------------------------------------------------------- */
1148 /* register definitions for the DP83848 */
1149
1150 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1151
1152 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1153 {
1154 struct fec_enet_private *fep = netdev_priv(dev);
1155 volatile uint *s = &(fep->phy_status);
1156
1157 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1158
1159 /* Link up */
1160 if (mii_reg & 0x0001) {
1161 fep->link = 1;
1162 *s |= PHY_STAT_LINK;
1163 } else
1164 fep->link = 0;
1165 /* Status of link */
1166 if (mii_reg & 0x0010) /* Autonegotioation complete */
1167 *s |= PHY_STAT_ANC;
1168 if (mii_reg & 0x0002) { /* 10MBps? */
1169 if (mii_reg & 0x0004) /* Full Duplex? */
1170 *s |= PHY_STAT_10FDX;
1171 else
1172 *s |= PHY_STAT_10HDX;
1173 } else { /* 100 Mbps? */
1174 if (mii_reg & 0x0004) /* Full Duplex? */
1175 *s |= PHY_STAT_100FDX;
1176 else
1177 *s |= PHY_STAT_100HDX;
1178 }
1179 if (mii_reg & 0x0008)
1180 *s |= PHY_STAT_FAULT;
1181 }
1182
1183 static phy_info_t phy_info_dp83848= {
1184 0x020005c9,
1185 "DP83848",
1186
1187 (const phy_cmd_t []) { /* config */
1188 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1189 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1190 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1191 { mk_mii_end, }
1192 },
1193 (const phy_cmd_t []) { /* startup - enable interrupts */
1194 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1195 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1196 { mk_mii_end, }
1197 },
1198 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1199 { mk_mii_end, }
1200 },
1201 (const phy_cmd_t []) { /* shutdown */
1202 { mk_mii_end, }
1203 },
1204 };
1205
1206 /* ------------------------------------------------------------------------- */
1207
1208 static phy_info_t const * const phy_info[] = {
1209 &phy_info_lxt970,
1210 &phy_info_lxt971,
1211 &phy_info_qs6612,
1212 &phy_info_am79c874,
1213 &phy_info_ks8721bl,
1214 &phy_info_dp83848,
1215 NULL
1216 };
1217
1218 /* ------------------------------------------------------------------------- */
1219 #ifdef HAVE_mii_link_interrupt
1220 static irqreturn_t
1221 mii_link_interrupt(int irq, void * dev_id);
1222 #endif
1223
1224 #if defined(CONFIG_M5272)
1225 /*
1226 * Code specific to Coldfire 5272 setup.
1227 */
1228 static void __inline__ fec_request_intrs(struct net_device *dev)
1229 {
1230 volatile unsigned long *icrp;
1231 static const struct idesc {
1232 char *name;
1233 unsigned short irq;
1234 irq_handler_t handler;
1235 } *idp, id[] = {
1236 { "fec(RX)", 86, fec_enet_interrupt },
1237 { "fec(TX)", 87, fec_enet_interrupt },
1238 { "fec(OTHER)", 88, fec_enet_interrupt },
1239 { "fec(MII)", 66, mii_link_interrupt },
1240 { NULL },
1241 };
1242
1243 /* Setup interrupt handlers. */
1244 for (idp = id; idp->name; idp++) {
1245 if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0)
1246 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1247 }
1248
1249 /* Unmask interrupt at ColdFire 5272 SIM */
1250 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1251 *icrp = 0x00000ddd;
1252 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1253 *icrp = 0x0d000000;
1254 }
1255
1256 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1257 {
1258 volatile fec_t *fecp;
1259
1260 fecp = fep->hwp;
1261 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1262 fecp->fec_x_cntrl = 0x00;
1263
1264 /*
1265 * Set MII speed to 2.5 MHz
1266 * See 5272 manual section 11.5.8: MSCR
1267 */
1268 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1269 fecp->fec_mii_speed = fep->phy_speed;
1270
1271 fec_restart(dev, 0);
1272 }
1273
1274 static void __inline__ fec_get_mac(struct net_device *dev)
1275 {
1276 struct fec_enet_private *fep = netdev_priv(dev);
1277 volatile fec_t *fecp;
1278 unsigned char *iap, tmpaddr[ETH_ALEN];
1279
1280 fecp = fep->hwp;
1281
1282 if (FEC_FLASHMAC) {
1283 /*
1284 * Get MAC address from FLASH.
1285 * If it is all 1's or 0's, use the default.
1286 */
1287 iap = (unsigned char *)FEC_FLASHMAC;
1288 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1289 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1290 iap = fec_mac_default;
1291 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1292 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1293 iap = fec_mac_default;
1294 } else {
1295 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1296 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1297 iap = &tmpaddr[0];
1298 }
1299
1300 memcpy(dev->dev_addr, iap, ETH_ALEN);
1301
1302 /* Adjust MAC if using default MAC address */
1303 if (iap == fec_mac_default)
1304 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1305 }
1306
1307 static void __inline__ fec_disable_phy_intr(void)
1308 {
1309 volatile unsigned long *icrp;
1310 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1311 *icrp = 0x08000000;
1312 }
1313
1314 static void __inline__ fec_phy_ack_intr(void)
1315 {
1316 volatile unsigned long *icrp;
1317 /* Acknowledge the interrupt */
1318 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1319 *icrp = 0x0d000000;
1320 }
1321
1322 /* ------------------------------------------------------------------------- */
1323
1324 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1325
1326 /*
1327 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1328 * the 5270/5271/5274/5275 and 5280/5282 setups.
1329 */
1330 static void __inline__ fec_request_intrs(struct net_device *dev)
1331 {
1332 struct fec_enet_private *fep;
1333 int b;
1334 static const struct idesc {
1335 char *name;
1336 unsigned short irq;
1337 } *idp, id[] = {
1338 { "fec(TXF)", 23 },
1339 { "fec(RXF)", 27 },
1340 { "fec(MII)", 29 },
1341 { NULL },
1342 };
1343
1344 fep = netdev_priv(dev);
1345 b = (fep->index) ? 128 : 64;
1346
1347 /* Setup interrupt handlers. */
1348 for (idp = id; idp->name; idp++) {
1349 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0)
1350 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1351 }
1352
1353 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1354 {
1355 volatile unsigned char *icrp;
1356 volatile unsigned long *imrp;
1357 int i, ilip;
1358
1359 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1360 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1361 MCFINTC_ICR0);
1362 for (i = 23, ilip = 0x28; (i < 36); i++)
1363 icrp[i] = ilip--;
1364
1365 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1366 MCFINTC_IMRH);
1367 *imrp &= ~0x0000000f;
1368 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1369 MCFINTC_IMRL);
1370 *imrp &= ~0xff800001;
1371 }
1372
1373 #if defined(CONFIG_M528x)
1374 /* Set up gpio outputs for MII lines */
1375 {
1376 volatile u16 *gpio_paspar;
1377 volatile u8 *gpio_pehlpar;
1378
1379 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1380 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1381 *gpio_paspar |= 0x0f00;
1382 *gpio_pehlpar = 0xc0;
1383 }
1384 #endif
1385
1386 #if defined(CONFIG_M527x)
1387 /* Set up gpio outputs for MII lines */
1388 {
1389 volatile u8 *gpio_par_fec;
1390 volatile u16 *gpio_par_feci2c;
1391
1392 gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
1393 /* Set up gpio outputs for FEC0 MII lines */
1394 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
1395
1396 *gpio_par_feci2c |= 0x0f00;
1397 *gpio_par_fec |= 0xc0;
1398
1399 #if defined(CONFIG_FEC2)
1400 /* Set up gpio outputs for FEC1 MII lines */
1401 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
1402
1403 *gpio_par_feci2c |= 0x00a0;
1404 *gpio_par_fec |= 0xc0;
1405 #endif /* CONFIG_FEC2 */
1406 }
1407 #endif /* CONFIG_M527x */
1408 }
1409
1410 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1411 {
1412 volatile fec_t *fecp;
1413
1414 fecp = fep->hwp;
1415 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1416 fecp->fec_x_cntrl = 0x00;
1417
1418 /*
1419 * Set MII speed to 2.5 MHz
1420 * See 5282 manual section 17.5.4.7: MSCR
1421 */
1422 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1423 fecp->fec_mii_speed = fep->phy_speed;
1424
1425 fec_restart(dev, 0);
1426 }
1427
1428 static void __inline__ fec_get_mac(struct net_device *dev)
1429 {
1430 struct fec_enet_private *fep = netdev_priv(dev);
1431 volatile fec_t *fecp;
1432 unsigned char *iap, tmpaddr[ETH_ALEN];
1433
1434 fecp = fep->hwp;
1435
1436 if (FEC_FLASHMAC) {
1437 /*
1438 * Get MAC address from FLASH.
1439 * If it is all 1's or 0's, use the default.
1440 */
1441 iap = FEC_FLASHMAC;
1442 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1443 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1444 iap = fec_mac_default;
1445 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1446 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1447 iap = fec_mac_default;
1448 } else {
1449 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1450 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1451 iap = &tmpaddr[0];
1452 }
1453
1454 memcpy(dev->dev_addr, iap, ETH_ALEN);
1455
1456 /* Adjust MAC if using default MAC address */
1457 if (iap == fec_mac_default)
1458 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1459 }
1460
1461 static void __inline__ fec_disable_phy_intr(void)
1462 {
1463 }
1464
1465 static void __inline__ fec_phy_ack_intr(void)
1466 {
1467 }
1468
1469 /* ------------------------------------------------------------------------- */
1470
1471 #elif defined(CONFIG_M520x)
1472
1473 /*
1474 * Code specific to Coldfire 520x
1475 */
1476 static void __inline__ fec_request_intrs(struct net_device *dev)
1477 {
1478 struct fec_enet_private *fep;
1479 int b;
1480 static const struct idesc {
1481 char *name;
1482 unsigned short irq;
1483 } *idp, id[] = {
1484 { "fec(TXF)", 23 },
1485 { "fec(RXF)", 27 },
1486 { "fec(MII)", 29 },
1487 { NULL },
1488 };
1489
1490 fep = netdev_priv(dev);
1491 b = 64 + 13;
1492
1493 /* Setup interrupt handlers. */
1494 for (idp = id; idp->name; idp++) {
1495 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1496 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1497 }
1498
1499 /* Unmask interrupts at ColdFire interrupt controller */
1500 {
1501 volatile unsigned char *icrp;
1502 volatile unsigned long *imrp;
1503
1504 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1505 MCFINTC_ICR0);
1506 for (b = 36; (b < 49); b++)
1507 icrp[b] = 0x04;
1508 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1509 MCFINTC_IMRH);
1510 *imrp &= ~0x0001FFF0;
1511 }
1512 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1513 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1514 }
1515
1516 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1517 {
1518 volatile fec_t *fecp;
1519
1520 fecp = fep->hwp;
1521 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1522 fecp->fec_x_cntrl = 0x00;
1523
1524 /*
1525 * Set MII speed to 2.5 MHz
1526 * See 5282 manual section 17.5.4.7: MSCR
1527 */
1528 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1529 fecp->fec_mii_speed = fep->phy_speed;
1530
1531 fec_restart(dev, 0);
1532 }
1533
1534 static void __inline__ fec_get_mac(struct net_device *dev)
1535 {
1536 struct fec_enet_private *fep = netdev_priv(dev);
1537 volatile fec_t *fecp;
1538 unsigned char *iap, tmpaddr[ETH_ALEN];
1539
1540 fecp = fep->hwp;
1541
1542 if (FEC_FLASHMAC) {
1543 /*
1544 * Get MAC address from FLASH.
1545 * If it is all 1's or 0's, use the default.
1546 */
1547 iap = FEC_FLASHMAC;
1548 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1549 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1550 iap = fec_mac_default;
1551 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1552 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1553 iap = fec_mac_default;
1554 } else {
1555 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1556 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1557 iap = &tmpaddr[0];
1558 }
1559
1560 memcpy(dev->dev_addr, iap, ETH_ALEN);
1561
1562 /* Adjust MAC if using default MAC address */
1563 if (iap == fec_mac_default)
1564 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1565 }
1566
1567 static void __inline__ fec_disable_phy_intr(void)
1568 {
1569 }
1570
1571 static void __inline__ fec_phy_ack_intr(void)
1572 {
1573 }
1574
1575 /* ------------------------------------------------------------------------- */
1576
1577 #elif defined(CONFIG_M532x)
1578 /*
1579 * Code specific for M532x
1580 */
1581 static void __inline__ fec_request_intrs(struct net_device *dev)
1582 {
1583 struct fec_enet_private *fep;
1584 int b;
1585 static const struct idesc {
1586 char *name;
1587 unsigned short irq;
1588 } *idp, id[] = {
1589 { "fec(TXF)", 36 },
1590 { "fec(RXF)", 40 },
1591 { "fec(MII)", 42 },
1592 { NULL },
1593 };
1594
1595 fep = netdev_priv(dev);
1596 b = (fep->index) ? 128 : 64;
1597
1598 /* Setup interrupt handlers. */
1599 for (idp = id; idp->name; idp++) {
1600 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1601 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1602 idp->name, b+idp->irq);
1603 }
1604
1605 /* Unmask interrupts */
1606 MCF_INTC0_ICR36 = 0x2;
1607 MCF_INTC0_ICR37 = 0x2;
1608 MCF_INTC0_ICR38 = 0x2;
1609 MCF_INTC0_ICR39 = 0x2;
1610 MCF_INTC0_ICR40 = 0x2;
1611 MCF_INTC0_ICR41 = 0x2;
1612 MCF_INTC0_ICR42 = 0x2;
1613 MCF_INTC0_ICR43 = 0x2;
1614 MCF_INTC0_ICR44 = 0x2;
1615 MCF_INTC0_ICR45 = 0x2;
1616 MCF_INTC0_ICR46 = 0x2;
1617 MCF_INTC0_ICR47 = 0x2;
1618 MCF_INTC0_ICR48 = 0x2;
1619
1620 MCF_INTC0_IMRH &= ~(
1621 MCF_INTC_IMRH_INT_MASK36 |
1622 MCF_INTC_IMRH_INT_MASK37 |
1623 MCF_INTC_IMRH_INT_MASK38 |
1624 MCF_INTC_IMRH_INT_MASK39 |
1625 MCF_INTC_IMRH_INT_MASK40 |
1626 MCF_INTC_IMRH_INT_MASK41 |
1627 MCF_INTC_IMRH_INT_MASK42 |
1628 MCF_INTC_IMRH_INT_MASK43 |
1629 MCF_INTC_IMRH_INT_MASK44 |
1630 MCF_INTC_IMRH_INT_MASK45 |
1631 MCF_INTC_IMRH_INT_MASK46 |
1632 MCF_INTC_IMRH_INT_MASK47 |
1633 MCF_INTC_IMRH_INT_MASK48 );
1634
1635 /* Set up gpio outputs for MII lines */
1636 MCF_GPIO_PAR_FECI2C |= (0 |
1637 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1638 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1639 MCF_GPIO_PAR_FEC = (0 |
1640 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1641 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1642 }
1643
1644 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1645 {
1646 volatile fec_t *fecp;
1647
1648 fecp = fep->hwp;
1649 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1650 fecp->fec_x_cntrl = 0x00;
1651
1652 /*
1653 * Set MII speed to 2.5 MHz
1654 */
1655 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1656 fecp->fec_mii_speed = fep->phy_speed;
1657
1658 fec_restart(dev, 0);
1659 }
1660
1661 static void __inline__ fec_get_mac(struct net_device *dev)
1662 {
1663 struct fec_enet_private *fep = netdev_priv(dev);
1664 volatile fec_t *fecp;
1665 unsigned char *iap, tmpaddr[ETH_ALEN];
1666
1667 fecp = fep->hwp;
1668
1669 if (FEC_FLASHMAC) {
1670 /*
1671 * Get MAC address from FLASH.
1672 * If it is all 1's or 0's, use the default.
1673 */
1674 iap = FEC_FLASHMAC;
1675 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1676 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1677 iap = fec_mac_default;
1678 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1679 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1680 iap = fec_mac_default;
1681 } else {
1682 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1683 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1684 iap = &tmpaddr[0];
1685 }
1686
1687 memcpy(dev->dev_addr, iap, ETH_ALEN);
1688
1689 /* Adjust MAC if using default MAC address */
1690 if (iap == fec_mac_default)
1691 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1692 }
1693
1694 static void __inline__ fec_disable_phy_intr(void)
1695 {
1696 }
1697
1698 static void __inline__ fec_phy_ack_intr(void)
1699 {
1700 }
1701
1702 #endif
1703
1704 /* ------------------------------------------------------------------------- */
1705
1706 static void mii_display_status(struct net_device *dev)
1707 {
1708 struct fec_enet_private *fep = netdev_priv(dev);
1709 volatile uint *s = &(fep->phy_status);
1710
1711 if (!fep->link && !fep->old_link) {
1712 /* Link is still down - don't print anything */
1713 return;
1714 }
1715
1716 printk("%s: status: ", dev->name);
1717
1718 if (!fep->link) {
1719 printk("link down");
1720 } else {
1721 printk("link up");
1722
1723 switch(*s & PHY_STAT_SPMASK) {
1724 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1725 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1726 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1727 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1728 default:
1729 printk(", Unknown speed/duplex");
1730 }
1731
1732 if (*s & PHY_STAT_ANC)
1733 printk(", auto-negotiation complete");
1734 }
1735
1736 if (*s & PHY_STAT_FAULT)
1737 printk(", remote fault");
1738
1739 printk(".\n");
1740 }
1741
1742 static void mii_display_config(struct work_struct *work)
1743 {
1744 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1745 struct net_device *dev = fep->netdev;
1746 uint status = fep->phy_status;
1747
1748 /*
1749 ** When we get here, phy_task is already removed from
1750 ** the workqueue. It is thus safe to allow to reuse it.
1751 */
1752 fep->mii_phy_task_queued = 0;
1753 printk("%s: config: auto-negotiation ", dev->name);
1754
1755 if (status & PHY_CONF_ANE)
1756 printk("on");
1757 else
1758 printk("off");
1759
1760 if (status & PHY_CONF_100FDX)
1761 printk(", 100FDX");
1762 if (status & PHY_CONF_100HDX)
1763 printk(", 100HDX");
1764 if (status & PHY_CONF_10FDX)
1765 printk(", 10FDX");
1766 if (status & PHY_CONF_10HDX)
1767 printk(", 10HDX");
1768 if (!(status & PHY_CONF_SPMASK))
1769 printk(", No speed/duplex selected?");
1770
1771 if (status & PHY_CONF_LOOP)
1772 printk(", loopback enabled");
1773
1774 printk(".\n");
1775
1776 fep->sequence_done = 1;
1777 }
1778
1779 static void mii_relink(struct work_struct *work)
1780 {
1781 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1782 struct net_device *dev = fep->netdev;
1783 int duplex;
1784
1785 /*
1786 ** When we get here, phy_task is already removed from
1787 ** the workqueue. It is thus safe to allow to reuse it.
1788 */
1789 fep->mii_phy_task_queued = 0;
1790 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1791 mii_display_status(dev);
1792 fep->old_link = fep->link;
1793
1794 if (fep->link) {
1795 duplex = 0;
1796 if (fep->phy_status
1797 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1798 duplex = 1;
1799 fec_restart(dev, duplex);
1800 } else
1801 fec_stop(dev);
1802
1803 #if 0
1804 enable_irq(fep->mii_irq);
1805 #endif
1806
1807 }
1808
1809 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1810 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1811 {
1812 struct fec_enet_private *fep = netdev_priv(dev);
1813
1814 /*
1815 ** We cannot queue phy_task twice in the workqueue. It
1816 ** would cause an endless loop in the workqueue.
1817 ** Fortunately, if the last mii_relink entry has not yet been
1818 ** executed now, it will do the job for the current interrupt,
1819 ** which is just what we want.
1820 */
1821 if (fep->mii_phy_task_queued)
1822 return;
1823
1824 fep->mii_phy_task_queued = 1;
1825 INIT_WORK(&fep->phy_task, mii_relink);
1826 schedule_work(&fep->phy_task);
1827 }
1828
1829 /* mii_queue_config is called in interrupt context from fec_enet_mii */
1830 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1831 {
1832 struct fec_enet_private *fep = netdev_priv(dev);
1833
1834 if (fep->mii_phy_task_queued)
1835 return;
1836
1837 fep->mii_phy_task_queued = 1;
1838 INIT_WORK(&fep->phy_task, mii_display_config);
1839 schedule_work(&fep->phy_task);
1840 }
1841
1842 phy_cmd_t const phy_cmd_relink[] = {
1843 { mk_mii_read(MII_REG_CR), mii_queue_relink },
1844 { mk_mii_end, }
1845 };
1846 phy_cmd_t const phy_cmd_config[] = {
1847 { mk_mii_read(MII_REG_CR), mii_queue_config },
1848 { mk_mii_end, }
1849 };
1850
1851 /* Read remainder of PHY ID.
1852 */
1853 static void
1854 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1855 {
1856 struct fec_enet_private *fep;
1857 int i;
1858
1859 fep = netdev_priv(dev);
1860 fep->phy_id |= (mii_reg & 0xffff);
1861 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
1862
1863 for(i = 0; phy_info[i]; i++) {
1864 if(phy_info[i]->id == (fep->phy_id >> 4))
1865 break;
1866 }
1867
1868 if (phy_info[i])
1869 printk(" -- %s\n", phy_info[i]->name);
1870 else
1871 printk(" -- unknown PHY!\n");
1872
1873 fep->phy = phy_info[i];
1874 fep->phy_id_done = 1;
1875 }
1876
1877 /* Scan all of the MII PHY addresses looking for someone to respond
1878 * with a valid ID. This usually happens quickly.
1879 */
1880 static void
1881 mii_discover_phy(uint mii_reg, struct net_device *dev)
1882 {
1883 struct fec_enet_private *fep;
1884 volatile fec_t *fecp;
1885 uint phytype;
1886
1887 fep = netdev_priv(dev);
1888 fecp = fep->hwp;
1889
1890 if (fep->phy_addr < 32) {
1891 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
1892
1893 /* Got first part of ID, now get remainder.
1894 */
1895 fep->phy_id = phytype << 16;
1896 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
1897 mii_discover_phy3);
1898 } else {
1899 fep->phy_addr++;
1900 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1901 mii_discover_phy);
1902 }
1903 } else {
1904 printk("FEC: No PHY device found.\n");
1905 /* Disable external MII interface */
1906 fecp->fec_mii_speed = fep->phy_speed = 0;
1907 fec_disable_phy_intr();
1908 }
1909 }
1910
1911 /* This interrupt occurs when the PHY detects a link change.
1912 */
1913 #ifdef HAVE_mii_link_interrupt
1914 static irqreturn_t
1915 mii_link_interrupt(int irq, void * dev_id)
1916 {
1917 struct net_device *dev = dev_id;
1918 struct fec_enet_private *fep = netdev_priv(dev);
1919
1920 fec_phy_ack_intr();
1921
1922 #if 0
1923 disable_irq(fep->mii_irq); /* disable now, enable later */
1924 #endif
1925
1926 mii_do_cmd(dev, fep->phy->ack_int);
1927 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1928
1929 return IRQ_HANDLED;
1930 }
1931 #endif
1932
1933 static int
1934 fec_enet_open(struct net_device *dev)
1935 {
1936 struct fec_enet_private *fep = netdev_priv(dev);
1937
1938 /* I should reset the ring buffers here, but I don't yet know
1939 * a simple way to do that.
1940 */
1941 fec_set_mac_address(dev);
1942
1943 fep->sequence_done = 0;
1944 fep->link = 0;
1945
1946 if (fep->phy) {
1947 mii_do_cmd(dev, fep->phy->ack_int);
1948 mii_do_cmd(dev, fep->phy->config);
1949 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1950
1951 /* Poll until the PHY tells us its configuration
1952 * (not link state).
1953 * Request is initiated by mii_do_cmd above, but answer
1954 * comes by interrupt.
1955 * This should take about 25 usec per register at 2.5 MHz,
1956 * and we read approximately 5 registers.
1957 */
1958 while(!fep->sequence_done)
1959 schedule();
1960
1961 mii_do_cmd(dev, fep->phy->startup);
1962
1963 /* Set the initial link state to true. A lot of hardware
1964 * based on this device does not implement a PHY interrupt,
1965 * so we are never notified of link change.
1966 */
1967 fep->link = 1;
1968 } else {
1969 fep->link = 1; /* lets just try it and see */
1970 /* no phy, go full duplex, it's most likely a hub chip */
1971 fec_restart(dev, 1);
1972 }
1973
1974 netif_start_queue(dev);
1975 fep->opened = 1;
1976 return 0; /* Success */
1977 }
1978
1979 static int
1980 fec_enet_close(struct net_device *dev)
1981 {
1982 struct fec_enet_private *fep = netdev_priv(dev);
1983
1984 /* Don't know what to do yet.
1985 */
1986 fep->opened = 0;
1987 netif_stop_queue(dev);
1988 fec_stop(dev);
1989
1990 return 0;
1991 }
1992
1993 /* Set or clear the multicast filter for this adaptor.
1994 * Skeleton taken from sunlance driver.
1995 * The CPM Ethernet implementation allows Multicast as well as individual
1996 * MAC address filtering. Some of the drivers check to make sure it is
1997 * a group multicast address, and discard those that are not. I guess I
1998 * will do the same for now, but just remove the test if you want
1999 * individual filtering as well (do the upper net layers want or support
2000 * this kind of feature?).
2001 */
2002
2003 #define HASH_BITS 6 /* #bits in hash */
2004 #define CRC32_POLY 0xEDB88320
2005
2006 static void set_multicast_list(struct net_device *dev)
2007 {
2008 struct fec_enet_private *fep;
2009 volatile fec_t *ep;
2010 struct dev_mc_list *dmi;
2011 unsigned int i, j, bit, data, crc;
2012 unsigned char hash;
2013
2014 fep = netdev_priv(dev);
2015 ep = fep->hwp;
2016
2017 if (dev->flags&IFF_PROMISC) {
2018 ep->fec_r_cntrl |= 0x0008;
2019 } else {
2020
2021 ep->fec_r_cntrl &= ~0x0008;
2022
2023 if (dev->flags & IFF_ALLMULTI) {
2024 /* Catch all multicast addresses, so set the
2025 * filter to all 1's.
2026 */
2027 ep->fec_grp_hash_table_high = 0xffffffff;
2028 ep->fec_grp_hash_table_low = 0xffffffff;
2029 } else {
2030 /* Clear filter and add the addresses in hash register.
2031 */
2032 ep->fec_grp_hash_table_high = 0;
2033 ep->fec_grp_hash_table_low = 0;
2034
2035 dmi = dev->mc_list;
2036
2037 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2038 {
2039 /* Only support group multicast for now.
2040 */
2041 if (!(dmi->dmi_addr[0] & 1))
2042 continue;
2043
2044 /* calculate crc32 value of mac address
2045 */
2046 crc = 0xffffffff;
2047
2048 for (i = 0; i < dmi->dmi_addrlen; i++)
2049 {
2050 data = dmi->dmi_addr[i];
2051 for (bit = 0; bit < 8; bit++, data >>= 1)
2052 {
2053 crc = (crc >> 1) ^
2054 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2055 }
2056 }
2057
2058 /* only upper 6 bits (HASH_BITS) are used
2059 which point to specific bit in he hash registers
2060 */
2061 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2062
2063 if (hash > 31)
2064 ep->fec_grp_hash_table_high |= 1 << (hash - 32);
2065 else
2066 ep->fec_grp_hash_table_low |= 1 << hash;
2067 }
2068 }
2069 }
2070 }
2071
2072 /* Set a MAC change in hardware.
2073 */
2074 static void
2075 fec_set_mac_address(struct net_device *dev)
2076 {
2077 volatile fec_t *fecp;
2078
2079 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2080
2081 /* Set station address. */
2082 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2083 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2084 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2085 (dev->dev_addr[4] << 24);
2086
2087 }
2088
2089 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2090 */
2091 /*
2092 * XXX: We need to clean up on failure exits here.
2093 */
2094 int __init fec_enet_init(struct net_device *dev)
2095 {
2096 struct fec_enet_private *fep = netdev_priv(dev);
2097 unsigned long mem_addr;
2098 volatile cbd_t *bdp;
2099 cbd_t *cbd_base;
2100 volatile fec_t *fecp;
2101 int i, j;
2102 static int index = 0;
2103
2104 /* Only allow us to be probed once. */
2105 if (index >= FEC_MAX_PORTS)
2106 return -ENXIO;
2107
2108 /* Allocate memory for buffer descriptors.
2109 */
2110 mem_addr = __get_free_page(GFP_KERNEL);
2111 if (mem_addr == 0) {
2112 printk("FEC: allocate descriptor memory failed?\n");
2113 return -ENOMEM;
2114 }
2115
2116 spin_lock_init(&fep->hw_lock);
2117 spin_lock_init(&fep->mii_lock);
2118
2119 /* Create an Ethernet device instance.
2120 */
2121 fecp = (volatile fec_t *) fec_hw[index];
2122
2123 fep->index = index;
2124 fep->hwp = fecp;
2125 fep->netdev = dev;
2126
2127 /* Whack a reset. We should wait for this.
2128 */
2129 fecp->fec_ecntrl = 1;
2130 udelay(10);
2131
2132 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2133 * this needs some work to get unique addresses.
2134 *
2135 * This is our default MAC address unless the user changes
2136 * it via eth_mac_addr (our dev->set_mac_addr handler).
2137 */
2138 fec_get_mac(dev);
2139
2140 cbd_base = (cbd_t *)mem_addr;
2141 /* XXX: missing check for allocation failure */
2142
2143 /* Set receive and transmit descriptor base.
2144 */
2145 fep->rx_bd_base = cbd_base;
2146 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2147
2148 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2149 fep->cur_rx = fep->rx_bd_base;
2150
2151 fep->skb_cur = fep->skb_dirty = 0;
2152
2153 /* Initialize the receive buffer descriptors.
2154 */
2155 bdp = fep->rx_bd_base;
2156 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2157
2158 /* Allocate a page.
2159 */
2160 mem_addr = __get_free_page(GFP_KERNEL);
2161 /* XXX: missing check for allocation failure */
2162
2163 /* Initialize the BD for every fragment in the page.
2164 */
2165 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2166 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2167 bdp->cbd_bufaddr = __pa(mem_addr);
2168 mem_addr += FEC_ENET_RX_FRSIZE;
2169 bdp++;
2170 }
2171 }
2172
2173 /* Set the last buffer to wrap.
2174 */
2175 bdp--;
2176 bdp->cbd_sc |= BD_SC_WRAP;
2177
2178 /* ...and the same for transmmit.
2179 */
2180 bdp = fep->tx_bd_base;
2181 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2182 if (j >= FEC_ENET_TX_FRPPG) {
2183 mem_addr = __get_free_page(GFP_KERNEL);
2184 j = 1;
2185 } else {
2186 mem_addr += FEC_ENET_TX_FRSIZE;
2187 j++;
2188 }
2189 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2190
2191 /* Initialize the BD for every fragment in the page.
2192 */
2193 bdp->cbd_sc = 0;
2194 bdp->cbd_bufaddr = 0;
2195 bdp++;
2196 }
2197
2198 /* Set the last buffer to wrap.
2199 */
2200 bdp--;
2201 bdp->cbd_sc |= BD_SC_WRAP;
2202
2203 /* Set receive and transmit descriptor base.
2204 */
2205 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2206 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2207
2208 /* Install our interrupt handlers. This varies depending on
2209 * the architecture.
2210 */
2211 fec_request_intrs(dev);
2212
2213 fecp->fec_grp_hash_table_high = 0;
2214 fecp->fec_grp_hash_table_low = 0;
2215 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2216 fecp->fec_ecntrl = 2;
2217 fecp->fec_r_des_active = 0;
2218 #ifndef CONFIG_M5272
2219 fecp->fec_hash_table_high = 0;
2220 fecp->fec_hash_table_low = 0;
2221 #endif
2222
2223 dev->base_addr = (unsigned long)fecp;
2224
2225 /* The FEC Ethernet specific entries in the device structure. */
2226 dev->open = fec_enet_open;
2227 dev->hard_start_xmit = fec_enet_start_xmit;
2228 dev->tx_timeout = fec_timeout;
2229 dev->watchdog_timeo = TX_TIMEOUT;
2230 dev->stop = fec_enet_close;
2231 dev->set_multicast_list = set_multicast_list;
2232
2233 for (i=0; i<NMII-1; i++)
2234 mii_cmds[i].mii_next = &mii_cmds[i+1];
2235 mii_free = mii_cmds;
2236
2237 /* setup MII interface */
2238 fec_set_mii(dev, fep);
2239
2240 /* Clear and enable interrupts */
2241 fecp->fec_ievent = 0xffc00000;
2242 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2243
2244 /* Queue up command to detect the PHY and initialize the
2245 * remainder of the interface.
2246 */
2247 fep->phy_id_done = 0;
2248 fep->phy_addr = 0;
2249 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2250
2251 index++;
2252 return 0;
2253 }
2254
2255 /* This function is called to start or restart the FEC during a link
2256 * change. This only happens when switching between half and full
2257 * duplex.
2258 */
2259 static void
2260 fec_restart(struct net_device *dev, int duplex)
2261 {
2262 struct fec_enet_private *fep;
2263 volatile cbd_t *bdp;
2264 volatile fec_t *fecp;
2265 int i;
2266
2267 fep = netdev_priv(dev);
2268 fecp = fep->hwp;
2269
2270 /* Whack a reset. We should wait for this.
2271 */
2272 fecp->fec_ecntrl = 1;
2273 udelay(10);
2274
2275 /* Clear any outstanding interrupt.
2276 */
2277 fecp->fec_ievent = 0xffc00000;
2278
2279 /* Set station address.
2280 */
2281 fec_set_mac_address(dev);
2282
2283 /* Reset all multicast.
2284 */
2285 fecp->fec_grp_hash_table_high = 0;
2286 fecp->fec_grp_hash_table_low = 0;
2287
2288 /* Set maximum receive buffer size.
2289 */
2290 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2291
2292 /* Set receive and transmit descriptor base.
2293 */
2294 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2295 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2296
2297 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2298 fep->cur_rx = fep->rx_bd_base;
2299
2300 /* Reset SKB transmit buffers.
2301 */
2302 fep->skb_cur = fep->skb_dirty = 0;
2303 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2304 if (fep->tx_skbuff[i] != NULL) {
2305 dev_kfree_skb_any(fep->tx_skbuff[i]);
2306 fep->tx_skbuff[i] = NULL;
2307 }
2308 }
2309
2310 /* Initialize the receive buffer descriptors.
2311 */
2312 bdp = fep->rx_bd_base;
2313 for (i=0; i<RX_RING_SIZE; i++) {
2314
2315 /* Initialize the BD for every fragment in the page.
2316 */
2317 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2318 bdp++;
2319 }
2320
2321 /* Set the last buffer to wrap.
2322 */
2323 bdp--;
2324 bdp->cbd_sc |= BD_SC_WRAP;
2325
2326 /* ...and the same for transmmit.
2327 */
2328 bdp = fep->tx_bd_base;
2329 for (i=0; i<TX_RING_SIZE; i++) {
2330
2331 /* Initialize the BD for every fragment in the page.
2332 */
2333 bdp->cbd_sc = 0;
2334 bdp->cbd_bufaddr = 0;
2335 bdp++;
2336 }
2337
2338 /* Set the last buffer to wrap.
2339 */
2340 bdp--;
2341 bdp->cbd_sc |= BD_SC_WRAP;
2342
2343 /* Enable MII mode.
2344 */
2345 if (duplex) {
2346 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2347 fecp->fec_x_cntrl = 0x04; /* FD enable */
2348 } else {
2349 /* MII enable|No Rcv on Xmit */
2350 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2351 fecp->fec_x_cntrl = 0x00;
2352 }
2353 fep->full_duplex = duplex;
2354
2355 /* Set MII speed.
2356 */
2357 fecp->fec_mii_speed = fep->phy_speed;
2358
2359 /* And last, enable the transmit and receive processing.
2360 */
2361 fecp->fec_ecntrl = 2;
2362 fecp->fec_r_des_active = 0;
2363
2364 /* Enable interrupts we wish to service.
2365 */
2366 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2367 }
2368
2369 static void
2370 fec_stop(struct net_device *dev)
2371 {
2372 volatile fec_t *fecp;
2373 struct fec_enet_private *fep;
2374
2375 fep = netdev_priv(dev);
2376 fecp = fep->hwp;
2377
2378 /*
2379 ** We cannot expect a graceful transmit stop without link !!!
2380 */
2381 if (fep->link)
2382 {
2383 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2384 udelay(10);
2385 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2386 printk("fec_stop : Graceful transmit stop did not complete !\n");
2387 }
2388
2389 /* Whack a reset. We should wait for this.
2390 */
2391 fecp->fec_ecntrl = 1;
2392 udelay(10);
2393
2394 /* Clear outstanding MII command interrupts.
2395 */
2396 fecp->fec_ievent = FEC_ENET_MII;
2397
2398 fecp->fec_imask = FEC_ENET_MII;
2399 fecp->fec_mii_speed = fep->phy_speed;
2400 }
2401
2402 static int __init fec_enet_module_init(void)
2403 {
2404 struct net_device *dev;
2405 int i, err;
2406
2407 printk("FEC ENET Version 0.2\n");
2408
2409 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2410 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2411 if (!dev)
2412 return -ENOMEM;
2413 err = fec_enet_init(dev);
2414 if (err) {
2415 free_netdev(dev);
2416 continue;
2417 }
2418 if (register_netdev(dev) != 0) {
2419 /* XXX: missing cleanup here */
2420 free_netdev(dev);
2421 return -EIO;
2422 }
2423
2424 printk("%s: ethernet %pM\n", dev->name, dev->dev_addr);
2425 }
2426 return 0;
2427 }
2428
2429 module_init(fec_enet_module_init);
2430
2431 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards