1 /* ffb.c: Creator/Elite3D frame buffer driver
3 * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz)
6 * Driver layout based loosely on tgafb.c, see that file for credits.
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/errno.h>
12 #include <linux/string.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
15 #include <linux/init.h>
18 #include <linux/timer.h>
23 #include <asm/of_device.h>
32 static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned,
33 unsigned, struct fb_info
*);
34 static int ffb_blank(int, struct fb_info
*);
35 static void ffb_init_fix(struct fb_info
*);
37 static void ffb_imageblit(struct fb_info
*, const struct fb_image
*);
38 static void ffb_fillrect(struct fb_info
*, const struct fb_fillrect
*);
39 static void ffb_copyarea(struct fb_info
*, const struct fb_copyarea
*);
40 static int ffb_sync(struct fb_info
*);
41 static int ffb_mmap(struct fb_info
*, struct vm_area_struct
*);
42 static int ffb_ioctl(struct fb_info
*, unsigned int, unsigned long);
43 static int ffb_pan_display(struct fb_var_screeninfo
*, struct fb_info
*);
46 * Frame buffer operations
49 static struct fb_ops ffb_ops
= {
51 .fb_setcolreg
= ffb_setcolreg
,
52 .fb_blank
= ffb_blank
,
53 .fb_pan_display
= ffb_pan_display
,
54 .fb_fillrect
= ffb_fillrect
,
55 .fb_copyarea
= ffb_copyarea
,
56 .fb_imageblit
= ffb_imageblit
,
59 .fb_ioctl
= ffb_ioctl
,
61 .fb_compat_ioctl
= sbusfb_compat_ioctl
,
65 /* Register layout and definitions */
66 #define FFB_SFB8R_VOFF 0x00000000
67 #define FFB_SFB8G_VOFF 0x00400000
68 #define FFB_SFB8B_VOFF 0x00800000
69 #define FFB_SFB8X_VOFF 0x00c00000
70 #define FFB_SFB32_VOFF 0x01000000
71 #define FFB_SFB64_VOFF 0x02000000
72 #define FFB_FBC_REGS_VOFF 0x04000000
73 #define FFB_BM_FBC_REGS_VOFF 0x04002000
74 #define FFB_DFB8R_VOFF 0x04004000
75 #define FFB_DFB8G_VOFF 0x04404000
76 #define FFB_DFB8B_VOFF 0x04804000
77 #define FFB_DFB8X_VOFF 0x04c04000
78 #define FFB_DFB24_VOFF 0x05004000
79 #define FFB_DFB32_VOFF 0x06004000
80 #define FFB_DFB422A_VOFF 0x07004000 /* DFB 422 mode write to A */
81 #define FFB_DFB422AD_VOFF 0x07804000 /* DFB 422 mode with line doubling */
82 #define FFB_DFB24B_VOFF 0x08004000 /* DFB 24bit mode write to B */
83 #define FFB_DFB422B_VOFF 0x09004000 /* DFB 422 mode write to B */
84 #define FFB_DFB422BD_VOFF 0x09804000 /* DFB 422 mode with line doubling */
85 #define FFB_SFB16Z_VOFF 0x0a004000 /* 16bit mode Z planes */
86 #define FFB_SFB8Z_VOFF 0x0a404000 /* 8bit mode Z planes */
87 #define FFB_SFB422_VOFF 0x0ac04000 /* SFB 422 mode write to A/B */
88 #define FFB_SFB422D_VOFF 0x0b404000 /* SFB 422 mode with line doubling */
89 #define FFB_FBC_KREGS_VOFF 0x0bc04000
90 #define FFB_DAC_VOFF 0x0bc06000
91 #define FFB_PROM_VOFF 0x0bc08000
92 #define FFB_EXP_VOFF 0x0bc18000
94 #define FFB_SFB8R_POFF 0x04000000UL
95 #define FFB_SFB8G_POFF 0x04400000UL
96 #define FFB_SFB8B_POFF 0x04800000UL
97 #define FFB_SFB8X_POFF 0x04c00000UL
98 #define FFB_SFB32_POFF 0x05000000UL
99 #define FFB_SFB64_POFF 0x06000000UL
100 #define FFB_FBC_REGS_POFF 0x00600000UL
101 #define FFB_BM_FBC_REGS_POFF 0x00600000UL
102 #define FFB_DFB8R_POFF 0x01000000UL
103 #define FFB_DFB8G_POFF 0x01400000UL
104 #define FFB_DFB8B_POFF 0x01800000UL
105 #define FFB_DFB8X_POFF 0x01c00000UL
106 #define FFB_DFB24_POFF 0x02000000UL
107 #define FFB_DFB32_POFF 0x03000000UL
108 #define FFB_FBC_KREGS_POFF 0x00610000UL
109 #define FFB_DAC_POFF 0x00400000UL
110 #define FFB_PROM_POFF 0x00000000UL
111 #define FFB_EXP_POFF 0x00200000UL
112 #define FFB_DFB422A_POFF 0x09000000UL
113 #define FFB_DFB422AD_POFF 0x09800000UL
114 #define FFB_DFB24B_POFF 0x0a000000UL
115 #define FFB_DFB422B_POFF 0x0b000000UL
116 #define FFB_DFB422BD_POFF 0x0b800000UL
117 #define FFB_SFB16Z_POFF 0x0c800000UL
118 #define FFB_SFB8Z_POFF 0x0c000000UL
119 #define FFB_SFB422_POFF 0x0d000000UL
120 #define FFB_SFB422D_POFF 0x0d800000UL
122 /* Draw operations */
123 #define FFB_DRAWOP_DOT 0x00
124 #define FFB_DRAWOP_AADOT 0x01
125 #define FFB_DRAWOP_BRLINECAP 0x02
126 #define FFB_DRAWOP_BRLINEOPEN 0x03
127 #define FFB_DRAWOP_DDLINE 0x04
128 #define FFB_DRAWOP_AALINE 0x05
129 #define FFB_DRAWOP_TRIANGLE 0x06
130 #define FFB_DRAWOP_POLYGON 0x07
131 #define FFB_DRAWOP_RECTANGLE 0x08
132 #define FFB_DRAWOP_FASTFILL 0x09
133 #define FFB_DRAWOP_BCOPY 0x0a
134 #define FFB_DRAWOP_VSCROLL 0x0b
136 /* Pixel processor control */
138 #define FFB_PPC_FW_DISABLE 0x800000
139 #define FFB_PPC_FW_ENABLE 0xc00000
141 #define FFB_PPC_ACE_DISABLE 0x040000
142 #define FFB_PPC_ACE_AUX_SUB 0x080000
143 #define FFB_PPC_ACE_AUX_ADD 0x0c0000
145 #define FFB_PPC_DCE_DISABLE 0x020000
146 #define FFB_PPC_DCE_ENABLE 0x030000
148 #define FFB_PPC_ABE_DISABLE 0x008000
149 #define FFB_PPC_ABE_ENABLE 0x00c000
151 #define FFB_PPC_VCE_DISABLE 0x001000
152 #define FFB_PPC_VCE_2D 0x002000
153 #define FFB_PPC_VCE_3D 0x003000
155 #define FFB_PPC_APE_DISABLE 0x000800
156 #define FFB_PPC_APE_ENABLE 0x000c00
157 /* Transparent background */
158 #define FFB_PPC_TBE_OPAQUE 0x000200
159 #define FFB_PPC_TBE_TRANSPARENT 0x000300
161 #define FFB_PPC_ZS_VAR 0x000080
162 #define FFB_PPC_ZS_CONST 0x0000c0
164 #define FFB_PPC_YS_VAR 0x000020
165 #define FFB_PPC_YS_CONST 0x000030
167 #define FFB_PPC_XS_WID 0x000004
168 #define FFB_PPC_XS_VAR 0x000008
169 #define FFB_PPC_XS_CONST 0x00000c
170 /* Color (BGR) source */
171 #define FFB_PPC_CS_VAR 0x000002
172 #define FFB_PPC_CS_CONST 0x000003
174 #define FFB_ROP_NEW 0x83
175 #define FFB_ROP_OLD 0x85
176 #define FFB_ROP_NEW_XOR_OLD 0x86
178 #define FFB_UCSR_FIFO_MASK 0x00000fff
179 #define FFB_UCSR_FB_BUSY 0x01000000
180 #define FFB_UCSR_RP_BUSY 0x02000000
181 #define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
182 #define FFB_UCSR_READ_ERR 0x40000000
183 #define FFB_UCSR_FIFO_OVFL 0x80000000
184 #define FFB_UCSR_ALL_ERRORS (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL)
187 /* Next vertex registers */
217 /* Setup unit vertex state register */
221 /* Control registers */
273 /* New 3dRAM III support regs */
339 #define FFB_DAC_UCTRL 0x1001 /* User Control */
340 #define FFB_DAC_UCTRL_MANREV 0x00000f00 /* 4-bit Manufacturing Revision */
341 #define FFB_DAC_UCTRL_MANREV_SHIFT 8
342 #define FFB_DAC_TGEN 0x6000 /* Timing Generator */
343 #define FFB_DAC_TGEN_VIDE 0x00000001 /* Video Enable */
344 #define FFB_DAC_DID 0x8000 /* Device Identification */
345 #define FFB_DAC_DID_PNUM 0x0ffff000 /* Device Part Number */
346 #define FFB_DAC_DID_PNUM_SHIFT 12
347 #define FFB_DAC_DID_REV 0xf0000000 /* Device Revision */
348 #define FFB_DAC_DID_REV_SHIFT 28
350 #define FFB_DAC_CUR_CTRL 0x100
351 #define FFB_DAC_CUR_CTRL_P0 0x00000001
352 #define FFB_DAC_CUR_CTRL_P1 0x00000002
356 struct ffb_fbc __iomem
*fbc
;
357 struct ffb_dac __iomem
*dac
;
360 #define FFB_FLAG_AFB 0x00000001 /* AFB m3 or m6 */
361 #define FFB_FLAG_BLANKED 0x00000002 /* screen is blanked */
362 #define FFB_FLAG_INVCURSOR 0x00000004 /* DAC has inverted cursor logic */
364 u32 fg_cache
__attribute__((aligned (8)));
370 unsigned long physbase
;
371 unsigned long fbsize
;
375 u32 pseudo_palette
[16];
378 static void FFBFifo(struct ffb_par
*par
, int n
)
380 struct ffb_fbc __iomem
*fbc
;
381 int cache
= par
->fifo_cache
;
385 do { cache
= (upa_readl(&fbc
->ucsr
) & FFB_UCSR_FIFO_MASK
) - 8;
386 } while (cache
- n
< 0);
388 par
->fifo_cache
= cache
- n
;
391 static void FFBWait(struct ffb_par
*par
)
393 struct ffb_fbc __iomem
*fbc
;
398 if ((upa_readl(&fbc
->ucsr
) & FFB_UCSR_ALL_BUSY
) == 0)
400 if ((upa_readl(&fbc
->ucsr
) & FFB_UCSR_ALL_ERRORS
) != 0) {
401 upa_writel(FFB_UCSR_ALL_ERRORS
, &fbc
->ucsr
);
404 } while(--limit
> 0);
407 static int ffb_sync(struct fb_info
*p
)
409 struct ffb_par
*par
= (struct ffb_par
*) p
->par
;
415 static __inline__
void ffb_rop(struct ffb_par
*par
, u32 rop
)
417 if (par
->rop_cache
!= rop
) {
419 upa_writel(rop
, &par
->fbc
->rop
);
420 par
->rop_cache
= rop
;
424 static void ffb_switch_from_graph(struct ffb_par
*par
)
426 struct ffb_fbc __iomem
*fbc
= par
->fbc
;
427 struct ffb_dac __iomem
*dac
= par
->dac
;
430 spin_lock_irqsave(&par
->lock
, flags
);
434 upa_writel(FFB_PPC_VCE_DISABLE
|FFB_PPC_TBE_OPAQUE
|
435 FFB_PPC_APE_DISABLE
|FFB_PPC_CS_CONST
,
437 upa_writel(0x2000707f, &fbc
->fbc
);
438 upa_writel(par
->rop_cache
, &fbc
->rop
);
439 upa_writel(0xffffffff, &fbc
->pmask
);
440 upa_writel((1 << 16) | (0 << 0), &fbc
->fontinc
);
441 upa_writel(par
->fg_cache
, &fbc
->fg
);
442 upa_writel(par
->bg_cache
, &fbc
->bg
);
445 /* Disable cursor. */
446 upa_writel(FFB_DAC_CUR_CTRL
, &dac
->type2
);
447 if (par
->flags
& FFB_FLAG_INVCURSOR
)
448 upa_writel(0, &dac
->value2
);
450 upa_writel((FFB_DAC_CUR_CTRL_P0
|
451 FFB_DAC_CUR_CTRL_P1
), &dac
->value2
);
453 spin_unlock_irqrestore(&par
->lock
, flags
);
456 static int ffb_pan_display(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
458 struct ffb_par
*par
= (struct ffb_par
*) info
->par
;
460 /* We just use this to catch switches out of
463 ffb_switch_from_graph(par
);
465 if (var
->xoffset
|| var
->yoffset
|| var
->vmode
)
471 * ffb_fillrect - REQUIRED function. Can use generic routines if
472 * non acclerated hardware and packed pixel based.
473 * Draws a rectangle on the screen.
475 * @info: frame buffer structure that represents a single frame buffer
476 * @rect: structure defining the rectagle and operation.
478 static void ffb_fillrect(struct fb_info
*info
, const struct fb_fillrect
*rect
)
480 struct ffb_par
*par
= (struct ffb_par
*) info
->par
;
481 struct ffb_fbc __iomem
*fbc
= par
->fbc
;
485 BUG_ON(rect
->rop
!= ROP_COPY
&& rect
->rop
!= ROP_XOR
);
487 fg
= ((u32
*)info
->pseudo_palette
)[rect
->color
];
489 spin_lock_irqsave(&par
->lock
, flags
);
491 if (fg
!= par
->fg_cache
) {
493 upa_writel(fg
, &fbc
->fg
);
497 ffb_rop(par
, (rect
->rop
== ROP_COPY
?
499 FFB_ROP_NEW_XOR_OLD
));
502 upa_writel(FFB_DRAWOP_RECTANGLE
, &fbc
->drawop
);
503 upa_writel(rect
->dy
, &fbc
->by
);
504 upa_writel(rect
->dx
, &fbc
->bx
);
505 upa_writel(rect
->height
, &fbc
->bh
);
506 upa_writel(rect
->width
, &fbc
->bw
);
508 spin_unlock_irqrestore(&par
->lock
, flags
);
512 * ffb_copyarea - REQUIRED function. Can use generic routines if
513 * non acclerated hardware and packed pixel based.
514 * Copies on area of the screen to another area.
516 * @info: frame buffer structure that represents a single frame buffer
517 * @area: structure defining the source and destination.
521 ffb_copyarea(struct fb_info
*info
, const struct fb_copyarea
*area
)
523 struct ffb_par
*par
= (struct ffb_par
*) info
->par
;
524 struct ffb_fbc __iomem
*fbc
= par
->fbc
;
527 if (area
->dx
!= area
->sx
||
528 area
->dy
== area
->sy
) {
529 cfb_copyarea(info
, area
);
533 spin_lock_irqsave(&par
->lock
, flags
);
535 ffb_rop(par
, FFB_ROP_OLD
);
538 upa_writel(FFB_DRAWOP_VSCROLL
, &fbc
->drawop
);
539 upa_writel(area
->sy
, &fbc
->by
);
540 upa_writel(area
->sx
, &fbc
->bx
);
541 upa_writel(area
->dy
, &fbc
->dy
);
542 upa_writel(area
->dx
, &fbc
->dx
);
543 upa_writel(area
->height
, &fbc
->bh
);
544 upa_writel(area
->width
, &fbc
->bw
);
546 spin_unlock_irqrestore(&par
->lock
, flags
);
550 * ffb_imageblit - REQUIRED function. Can use generic routines if
551 * non acclerated hardware and packed pixel based.
552 * Copies a image from system memory to the screen.
554 * @info: frame buffer structure that represents a single frame buffer
555 * @image: structure defining the image.
557 static void ffb_imageblit(struct fb_info
*info
, const struct fb_image
*image
)
559 struct ffb_par
*par
= (struct ffb_par
*) info
->par
;
560 struct ffb_fbc __iomem
*fbc
= par
->fbc
;
561 const u8
*data
= image
->data
;
565 int i
, width
, stride
;
567 if (image
->depth
> 1) {
568 cfb_imageblit(info
, image
);
572 fg
= ((u32
*)info
->pseudo_palette
)[image
->fg_color
];
573 bg
= ((u32
*)info
->pseudo_palette
)[image
->bg_color
];
574 fgbg
= ((u64
) fg
<< 32) | (u64
) bg
;
575 xy
= (image
->dy
<< 16) | image
->dx
;
576 width
= image
->width
;
577 stride
= ((width
+ 7) >> 3);
579 spin_lock_irqsave(&par
->lock
, flags
);
581 if (fgbg
!= *(u64
*)&par
->fg_cache
) {
583 upa_writeq(fgbg
, &fbc
->fg
);
584 *(u64
*)&par
->fg_cache
= fgbg
;
589 upa_writel(32, &fbc
->fontw
);
592 while (width
>= 32) {
593 const u8
*next_data
= data
+ 4;
596 upa_writel(xy
, &fbc
->fontxy
);
599 for (i
= 0; i
< image
->height
; i
++) {
600 u32 val
= (((u32
)data
[0] << 24) |
601 ((u32
)data
[1] << 16) |
602 ((u32
)data
[2] << 8) |
603 ((u32
)data
[3] << 0));
605 upa_writel(val
, &fbc
->font
);
616 upa_writel(width
, &fbc
->fontw
);
617 upa_writel(xy
, &fbc
->fontxy
);
619 for (i
= 0; i
< image
->height
; i
++) {
620 u32 val
= (((u32
)data
[0] << 24) |
621 ((u32
)data
[1] << 16) |
622 ((u32
)data
[2] << 8) |
623 ((u32
)data
[3] << 0));
625 upa_writel(val
, &fbc
->font
);
631 spin_unlock_irqrestore(&par
->lock
, flags
);
634 static void ffb_fixup_var_rgb(struct fb_var_screeninfo
*var
)
638 var
->green
.offset
= 8;
639 var
->green
.length
= 8;
640 var
->blue
.offset
= 16;
641 var
->blue
.length
= 8;
642 var
->transp
.offset
= 0;
643 var
->transp
.length
= 0;
647 * ffb_setcolreg - Optional function. Sets a color register.
648 * @regno: boolean, 0 copy local, 1 get_user() function
649 * @red: frame buffer colormap structure
650 * @green: The green value which can be up to 16 bits wide
651 * @blue: The blue value which can be up to 16 bits wide.
652 * @transp: If supported the alpha value which can be up to 16 bits wide.
653 * @info: frame buffer info structure
655 static int ffb_setcolreg(unsigned regno
,
656 unsigned red
, unsigned green
, unsigned blue
,
657 unsigned transp
, struct fb_info
*info
)
668 value
= (blue
<< 16) | (green
<< 8) | red
;
669 ((u32
*)info
->pseudo_palette
)[regno
] = value
;
675 * ffb_blank - Optional function. Blanks the display.
676 * @blank_mode: the blank mode we want.
677 * @info: frame buffer structure that represents a single frame buffer
680 ffb_blank(int blank
, struct fb_info
*info
)
682 struct ffb_par
*par
= (struct ffb_par
*) info
->par
;
683 struct ffb_dac __iomem
*dac
= par
->dac
;
688 spin_lock_irqsave(&par
->lock
, flags
);
692 upa_writel(FFB_DAC_TGEN
, &dac
->type
);
693 val
= upa_readl(&dac
->value
);
695 case FB_BLANK_UNBLANK
: /* Unblanking */
696 val
|= FFB_DAC_TGEN_VIDE
;
697 par
->flags
&= ~FFB_FLAG_BLANKED
;
700 case FB_BLANK_NORMAL
: /* Normal blanking */
701 case FB_BLANK_VSYNC_SUSPEND
: /* VESA blank (vsync off) */
702 case FB_BLANK_HSYNC_SUSPEND
: /* VESA blank (hsync off) */
703 case FB_BLANK_POWERDOWN
: /* Poweroff */
704 val
&= ~FFB_DAC_TGEN_VIDE
;
705 par
->flags
|= FFB_FLAG_BLANKED
;
708 upa_writel(FFB_DAC_TGEN
, &dac
->type
);
709 upa_writel(val
, &dac
->value
);
710 for (i
= 0; i
< 10; i
++) {
711 upa_writel(FFB_DAC_TGEN
, &dac
->type
);
712 upa_readl(&dac
->value
);
715 spin_unlock_irqrestore(&par
->lock
, flags
);
720 static struct sbus_mmap_map ffb_mmap_map
[] = {
722 .voff
= FFB_SFB8R_VOFF
,
723 .poff
= FFB_SFB8R_POFF
,
727 .voff
= FFB_SFB8G_VOFF
,
728 .poff
= FFB_SFB8G_POFF
,
732 .voff
= FFB_SFB8B_VOFF
,
733 .poff
= FFB_SFB8B_POFF
,
737 .voff
= FFB_SFB8X_VOFF
,
738 .poff
= FFB_SFB8X_POFF
,
742 .voff
= FFB_SFB32_VOFF
,
743 .poff
= FFB_SFB32_POFF
,
747 .voff
= FFB_SFB64_VOFF
,
748 .poff
= FFB_SFB64_POFF
,
752 .voff
= FFB_FBC_REGS_VOFF
,
753 .poff
= FFB_FBC_REGS_POFF
,
757 .voff
= FFB_BM_FBC_REGS_VOFF
,
758 .poff
= FFB_BM_FBC_REGS_POFF
,
762 .voff
= FFB_DFB8R_VOFF
,
763 .poff
= FFB_DFB8R_POFF
,
767 .voff
= FFB_DFB8G_VOFF
,
768 .poff
= FFB_DFB8G_POFF
,
772 .voff
= FFB_DFB8B_VOFF
,
773 .poff
= FFB_DFB8B_POFF
,
777 .voff
= FFB_DFB8X_VOFF
,
778 .poff
= FFB_DFB8X_POFF
,
782 .voff
= FFB_DFB24_VOFF
,
783 .poff
= FFB_DFB24_POFF
,
787 .voff
= FFB_DFB32_VOFF
,
788 .poff
= FFB_DFB32_POFF
,
792 .voff
= FFB_FBC_KREGS_VOFF
,
793 .poff
= FFB_FBC_KREGS_POFF
,
797 .voff
= FFB_DAC_VOFF
,
798 .poff
= FFB_DAC_POFF
,
802 .voff
= FFB_PROM_VOFF
,
803 .poff
= FFB_PROM_POFF
,
807 .voff
= FFB_EXP_VOFF
,
808 .poff
= FFB_EXP_POFF
,
812 .voff
= FFB_DFB422A_VOFF
,
813 .poff
= FFB_DFB422A_POFF
,
817 .voff
= FFB_DFB422AD_VOFF
,
818 .poff
= FFB_DFB422AD_POFF
,
822 .voff
= FFB_DFB24B_VOFF
,
823 .poff
= FFB_DFB24B_POFF
,
827 .voff
= FFB_DFB422B_VOFF
,
828 .poff
= FFB_DFB422B_POFF
,
832 .voff
= FFB_DFB422BD_VOFF
,
833 .poff
= FFB_DFB422BD_POFF
,
837 .voff
= FFB_SFB16Z_VOFF
,
838 .poff
= FFB_SFB16Z_POFF
,
842 .voff
= FFB_SFB8Z_VOFF
,
843 .poff
= FFB_SFB8Z_POFF
,
847 .voff
= FFB_SFB422_VOFF
,
848 .poff
= FFB_SFB422_POFF
,
852 .voff
= FFB_SFB422D_VOFF
,
853 .poff
= FFB_SFB422D_POFF
,
859 static int ffb_mmap(struct fb_info
*info
, struct vm_area_struct
*vma
)
861 struct ffb_par
*par
= (struct ffb_par
*)info
->par
;
863 return sbusfb_mmap_helper(ffb_mmap_map
,
864 par
->physbase
, par
->fbsize
,
868 static int ffb_ioctl(struct fb_info
*info
, unsigned int cmd
, unsigned long arg
)
870 struct ffb_par
*par
= (struct ffb_par
*) info
->par
;
872 return sbusfb_ioctl_helper(cmd
, arg
, info
,
873 FBTYPE_CREATOR
, 24, par
->fbsize
);
881 ffb_init_fix(struct fb_info
*info
)
883 struct ffb_par
*par
= (struct ffb_par
*)info
->par
;
884 const char *ffb_type_name
;
886 if (!(par
->flags
& FFB_FLAG_AFB
)) {
887 if ((par
->board_type
& 0x7) == 0x3)
888 ffb_type_name
= "Creator 3D";
890 ffb_type_name
= "Creator";
892 ffb_type_name
= "Elite 3D";
894 strlcpy(info
->fix
.id
, ffb_type_name
, sizeof(info
->fix
.id
));
896 info
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
897 info
->fix
.visual
= FB_VISUAL_TRUECOLOR
;
899 /* Framebuffer length is the same regardless of resolution. */
900 info
->fix
.line_length
= 8192;
902 info
->fix
.accel
= FB_ACCEL_SUN_CREATOR
;
905 static int __devinit
ffb_probe(struct of_device
*op
, const struct of_device_id
*match
)
907 struct device_node
*dp
= op
->node
;
908 struct ffb_fbc __iomem
*fbc
;
909 struct ffb_dac __iomem
*dac
;
910 struct fb_info
*info
;
912 u32 dac_pnum
, dac_rev
, dac_mrev
;
915 info
= framebuffer_alloc(sizeof(struct ffb_par
), &op
->dev
);
923 spin_lock_init(&par
->lock
);
924 par
->fbc
= of_ioremap(&op
->resource
[2], 0,
925 sizeof(struct ffb_fbc
), "ffb fbc");
929 par
->dac
= of_ioremap(&op
->resource
[1], 0,
930 sizeof(struct ffb_dac
), "ffb dac");
934 par
->rop_cache
= FFB_ROP_NEW
;
935 par
->physbase
= op
->resource
[0].start
;
937 /* Don't mention copyarea, so SCROLL_REDRAW is always
938 * used. It is the fastest on this chip.
940 info
->flags
= (FBINFO_DEFAULT
|
941 /* FBINFO_HWACCEL_COPYAREA | */
942 FBINFO_HWACCEL_FILLRECT
|
943 FBINFO_HWACCEL_IMAGEBLIT
);
945 info
->fbops
= &ffb_ops
;
947 info
->screen_base
= (char *) par
->physbase
+ FFB_DFB24_POFF
;
948 info
->pseudo_palette
= par
->pseudo_palette
;
950 sbusfb_fill_var(&info
->var
, dp
->node
, 32);
951 par
->fbsize
= PAGE_ALIGN(info
->var
.xres
* info
->var
.yres
* 4);
952 ffb_fixup_var_rgb(&info
->var
);
954 info
->var
.accel_flags
= FB_ACCELF_TEXT
;
956 if (!strcmp(dp
->name
, "SUNW,afb"))
957 par
->flags
|= FFB_FLAG_AFB
;
959 par
->board_type
= of_getintprop_default(dp
, "board_type", 0);
962 if ((upa_readl(&fbc
->ucsr
) & FFB_UCSR_ALL_ERRORS
) != 0)
963 upa_writel(FFB_UCSR_ALL_ERRORS
, &fbc
->ucsr
);
966 upa_writel(FFB_DAC_DID
, &dac
->type
);
967 dac_pnum
= upa_readl(&dac
->value
);
968 dac_rev
= (dac_pnum
& FFB_DAC_DID_REV
) >> FFB_DAC_DID_REV_SHIFT
;
969 dac_pnum
= (dac_pnum
& FFB_DAC_DID_PNUM
) >> FFB_DAC_DID_PNUM_SHIFT
;
971 upa_writel(FFB_DAC_UCTRL
, &dac
->type
);
972 dac_mrev
= upa_readl(&dac
->value
);
973 dac_mrev
= (dac_mrev
& FFB_DAC_UCTRL_MANREV
) >>
974 FFB_DAC_UCTRL_MANREV_SHIFT
;
976 /* Elite3D has different DAC revision numbering, and no DAC revisions
977 * have the reversed meaning of cursor enable. Otherwise, Pacifica 1
978 * ramdacs with manufacturing revision less than 3 have inverted
979 * cursor logic. We identify Pacifica 1 as not Pacifica 2, the
980 * latter having a part number value of 0x236e.
982 if ((par
->flags
& FFB_FLAG_AFB
) || dac_pnum
== 0x236e) {
983 par
->flags
&= ~FFB_FLAG_INVCURSOR
;
986 par
->flags
|= FFB_FLAG_INVCURSOR
;
989 ffb_switch_from_graph(par
);
991 /* Unblank it just to be sure. When there are multiple
992 * FFB/AFB cards in the system, or it is not the OBP
993 * chosen console, it will have video outputs off in
998 if (fb_alloc_cmap(&info
->cmap
, 256, 0))
1003 err
= register_framebuffer(info
);
1005 goto out_dealloc_cmap
;
1007 dev_set_drvdata(&op
->dev
, info
);
1009 printk("%s: %s at %016lx, type %d, "
1010 "DAC pnum[%x] rev[%d] manuf_rev[%d]\n",
1012 ((par
->flags
& FFB_FLAG_AFB
) ? "AFB" : "FFB"),
1013 par
->physbase
, par
->board_type
,
1014 dac_pnum
, dac_rev
, dac_mrev
);
1019 fb_dealloc_cmap(&info
->cmap
);
1022 of_iounmap(&op
->resource
[2], par
->fbc
, sizeof(struct ffb_fbc
));
1025 of_iounmap(&op
->resource
[2], par
->fbc
, sizeof(struct ffb_fbc
));
1028 framebuffer_release(info
);
1034 static int __devexit
ffb_remove(struct of_device
*op
)
1036 struct fb_info
*info
= dev_get_drvdata(&op
->dev
);
1037 struct ffb_par
*par
= info
->par
;
1039 unregister_framebuffer(info
);
1040 fb_dealloc_cmap(&info
->cmap
);
1042 of_iounmap(&op
->resource
[2], par
->fbc
, sizeof(struct ffb_fbc
));
1043 of_iounmap(&op
->resource
[1], par
->dac
, sizeof(struct ffb_dac
));
1045 framebuffer_release(info
);
1047 dev_set_drvdata(&op
->dev
, NULL
);
1052 static struct of_device_id ffb_match
[] = {
1061 MODULE_DEVICE_TABLE(of
, ffb_match
);
1063 static struct of_platform_driver ffb_driver
= {
1065 .match_table
= ffb_match
,
1067 .remove
= __devexit_p(ffb_remove
),
1070 int __init
ffb_init(void)
1072 if (fb_get_options("ffb", NULL
))
1075 return of_register_driver(&ffb_driver
, &of_bus_type
);
1078 void __exit
ffb_exit(void)
1080 of_unregister_driver(&ffb_driver
);
1083 module_init(ffb_init
);
1084 module_exit(ffb_exit
);
1086 MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets");
1087 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
1088 MODULE_VERSION("2.0");
1089 MODULE_LICENSE("GPL");