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[MIPS] Remove stray instruction from __get_user_asm_ll32.
[linux-2.6/mini2440.git] / drivers / ata / sata_sil.c
blobdca3d3749f0626cbc2d79798ecda01502b1452e3
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "2.0"
50
51 enum {
52 SIL_MMIO_BAR = 5,
53
54 /*
55 * host flags
56 */
57 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
58 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
59 SIL_FLAG_MOD15WRITE = (1 << 30),
60
61 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
62 ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME,
63
64 /*
65 * Controller IDs
66 */
67 sil_3112 = 0,
68 sil_3112_no_sata_irq = 1,
69 sil_3512 = 2,
70 sil_3114 = 3,
71
72 /*
73 * Register offsets
74 */
75 SIL_SYSCFG = 0x48,
76
77 /*
78 * Register bits
79 */
80 /* SYSCFG */
81 SIL_MASK_IDE0_INT = (1 << 22),
82 SIL_MASK_IDE1_INT = (1 << 23),
83 SIL_MASK_IDE2_INT = (1 << 24),
84 SIL_MASK_IDE3_INT = (1 << 25),
85 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
86 SIL_MASK_4PORT = SIL_MASK_2PORT |
87 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
88
89 /* BMDMA/BMDMA2 */
90 SIL_INTR_STEERING = (1 << 1),
91
92 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
93 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
94 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
95 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
96 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
97 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
98 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
99 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
100 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
101 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
102
103 /* SIEN */
104 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
105
106 /*
107 * Others
108 */
109 SIL_QUIRK_MOD15WRITE = (1 << 0),
110 SIL_QUIRK_UDMA5MAX = (1 << 1),
111 };
112
113 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
114 #ifdef CONFIG_PM
115 static int sil_pci_device_resume(struct pci_dev *pdev);
116 #endif
117 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
118 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
119 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static void sil_post_set_mode (struct ata_port *ap);
121 static irqreturn_t sil_interrupt(int irq, void *dev_instance);
122 static void sil_freeze(struct ata_port *ap);
123 static void sil_thaw(struct ata_port *ap);
124
125
126 static const struct pci_device_id sil_pci_tbl[] = {
127 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
128 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
129 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
130 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
131 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
132 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
133 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
134
135 { } /* terminate list */
136 };
137
138
139 /* TODO firmware versions should be added - eric */
140 static const struct sil_drivelist {
141 const char * product;
142 unsigned int quirk;
143 } sil_blacklist [] = {
144 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
145 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
146 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
147 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
148 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
149 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
150 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
153 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
154 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
155 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
156 { }
157 };
158
159 static struct pci_driver sil_pci_driver = {
160 .name = DRV_NAME,
161 .id_table = sil_pci_tbl,
162 .probe = sil_init_one,
163 .remove = ata_pci_remove_one,
164 #ifdef CONFIG_PM
165 .suspend = ata_pci_device_suspend,
166 .resume = sil_pci_device_resume,
167 #endif
168 };
169
170 static struct scsi_host_template sil_sht = {
171 .module = THIS_MODULE,
172 .name = DRV_NAME,
173 .ioctl = ata_scsi_ioctl,
174 .queuecommand = ata_scsi_queuecmd,
175 .can_queue = ATA_DEF_QUEUE,
176 .this_id = ATA_SHT_THIS_ID,
177 .sg_tablesize = LIBATA_MAX_PRD,
178 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
179 .emulated = ATA_SHT_EMULATED,
180 .use_clustering = ATA_SHT_USE_CLUSTERING,
181 .proc_name = DRV_NAME,
182 .dma_boundary = ATA_DMA_BOUNDARY,
183 .slave_configure = ata_scsi_slave_config,
184 .slave_destroy = ata_scsi_slave_destroy,
185 .bios_param = ata_std_bios_param,
186 .suspend = ata_scsi_device_suspend,
187 .resume = ata_scsi_device_resume,
188 };
189
190 static const struct ata_port_operations sil_ops = {
191 .port_disable = ata_port_disable,
192 .dev_config = sil_dev_config,
193 .tf_load = ata_tf_load,
194 .tf_read = ata_tf_read,
195 .check_status = ata_check_status,
196 .exec_command = ata_exec_command,
197 .dev_select = ata_std_dev_select,
198 .post_set_mode = sil_post_set_mode,
199 .bmdma_setup = ata_bmdma_setup,
200 .bmdma_start = ata_bmdma_start,
201 .bmdma_stop = ata_bmdma_stop,
202 .bmdma_status = ata_bmdma_status,
203 .qc_prep = ata_qc_prep,
204 .qc_issue = ata_qc_issue_prot,
205 .data_xfer = ata_data_xfer,
206 .freeze = sil_freeze,
207 .thaw = sil_thaw,
208 .error_handler = ata_bmdma_error_handler,
209 .post_internal_cmd = ata_bmdma_post_internal_cmd,
210 .irq_handler = sil_interrupt,
211 .irq_clear = ata_bmdma_irq_clear,
212 .irq_on = ata_irq_on,
213 .irq_ack = ata_irq_ack,
214 .scr_read = sil_scr_read,
215 .scr_write = sil_scr_write,
216 .port_start = ata_port_start,
217 };
218
219 static const struct ata_port_info sil_port_info[] = {
220 /* sil_3112 */
221 {
222 .sht = &sil_sht,
223 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
224 .pio_mask = 0x1f, /* pio0-4 */
225 .mwdma_mask = 0x07, /* mwdma0-2 */
226 .udma_mask = 0x3f, /* udma0-5 */
227 .port_ops = &sil_ops,
228 },
229 /* sil_3112_no_sata_irq */
230 {
231 .sht = &sil_sht,
232 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
233 SIL_FLAG_NO_SATA_IRQ,
234 .pio_mask = 0x1f, /* pio0-4 */
235 .mwdma_mask = 0x07, /* mwdma0-2 */
236 .udma_mask = 0x3f, /* udma0-5 */
237 .port_ops = &sil_ops,
238 },
239 /* sil_3512 */
240 {
241 .sht = &sil_sht,
242 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
243 .pio_mask = 0x1f, /* pio0-4 */
244 .mwdma_mask = 0x07, /* mwdma0-2 */
245 .udma_mask = 0x3f, /* udma0-5 */
246 .port_ops = &sil_ops,
247 },
248 /* sil_3114 */
249 {
250 .sht = &sil_sht,
251 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
252 .pio_mask = 0x1f, /* pio0-4 */
253 .mwdma_mask = 0x07, /* mwdma0-2 */
254 .udma_mask = 0x3f, /* udma0-5 */
255 .port_ops = &sil_ops,
256 },
257 };
258
259 /* per-port register offsets */
260 /* TODO: we can probably calculate rather than use a table */
261 static const struct {
262 unsigned long tf; /* ATA taskfile register block */
263 unsigned long ctl; /* ATA control/altstatus register block */
264 unsigned long bmdma; /* DMA register block */
265 unsigned long bmdma2; /* DMA register block #2 */
266 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
267 unsigned long scr; /* SATA control register block */
268 unsigned long sien; /* SATA Interrupt Enable register */
269 unsigned long xfer_mode;/* data transfer mode register */
270 unsigned long sfis_cfg; /* SATA FIS reception config register */
271 } sil_port[] = {
272 /* port 0 ... */
273 { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
274 { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
275 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
276 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
277 /* ... port 3 */
278 };
279
280 MODULE_AUTHOR("Jeff Garzik");
281 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
282 MODULE_LICENSE("GPL");
283 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
284 MODULE_VERSION(DRV_VERSION);
285
286 static int slow_down = 0;
287 module_param(slow_down, int, 0444);
288 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
289
290
291 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
292 {
293 u8 cache_line = 0;
294 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
295 return cache_line;
296 }
297
298 static void sil_post_set_mode (struct ata_port *ap)
299 {
300 struct ata_host *host = ap->host;
301 struct ata_device *dev;
302 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
303 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
304 u32 tmp, dev_mode[2];
305 unsigned int i;
306
307 for (i = 0; i < 2; i++) {
308 dev = &ap->device[i];
309 if (!ata_dev_enabled(dev))
310 dev_mode[i] = 0; /* PIO0/1/2 */
311 else if (dev->flags & ATA_DFLAG_PIO)
312 dev_mode[i] = 1; /* PIO3/4 */
313 else
314 dev_mode[i] = 3; /* UDMA */
315 /* value 2 indicates MDMA */
316 }
317
318 tmp = readl(addr);
319 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
320 tmp |= dev_mode[0];
321 tmp |= (dev_mode[1] << 4);
322 writel(tmp, addr);
323 readl(addr); /* flush */
324 }
325
326 static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
327 {
328 void __iomem *offset = ap->ioaddr.scr_addr;
329
330 switch (sc_reg) {
331 case SCR_STATUS:
332 return offset + 4;
333 case SCR_ERROR:
334 return offset + 8;
335 case SCR_CONTROL:
336 return offset;
337 default:
338 /* do nothing */
339 break;
340 }
341
342 return 0;
343 }
344
345 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
346 {
347 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
348 if (mmio)
349 return readl(mmio);
350 return 0xffffffffU;
351 }
352
353 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
354 {
355 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
356 if (mmio)
357 writel(val, mmio);
358 }
359
360 static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
361 {
362 struct ata_eh_info *ehi = &ap->eh_info;
363 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
364 u8 status;
365
366 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
367 u32 serror;
368
369 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
370 * controllers continue to assert IRQ as long as
371 * SError bits are pending. Clear SError immediately.
372 */
373 serror = sil_scr_read(ap, SCR_ERROR);
374 sil_scr_write(ap, SCR_ERROR, serror);
375
376 /* Trigger hotplug and accumulate SError only if the
377 * port isn't already frozen. Otherwise, PHY events
378 * during hardreset makes controllers with broken SIEN
379 * repeat probing needlessly.
380 */
381 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
382 ata_ehi_hotplugged(&ap->eh_info);
383 ap->eh_info.serror |= serror;
384 }
385
386 goto freeze;
387 }
388
389 if (unlikely(!qc || qc->tf.ctl & ATA_NIEN))
390 goto freeze;
391
392 /* Check whether we are expecting interrupt in this state */
393 switch (ap->hsm_task_state) {
394 case HSM_ST_FIRST:
395 /* Some pre-ATAPI-4 devices assert INTRQ
396 * at this state when ready to receive CDB.
397 */
398
399 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
400 * The flag was turned on only for atapi devices.
401 * No need to check is_atapi_taskfile(&qc->tf) again.
402 */
403 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
404 goto err_hsm;
405 break;
406 case HSM_ST_LAST:
407 if (qc->tf.protocol == ATA_PROT_DMA ||
408 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
409 /* clear DMA-Start bit */
410 ap->ops->bmdma_stop(qc);
411
412 if (bmdma2 & SIL_DMA_ERROR) {
413 qc->err_mask |= AC_ERR_HOST_BUS;
414 ap->hsm_task_state = HSM_ST_ERR;
415 }
416 }
417 break;
418 case HSM_ST:
419 break;
420 default:
421 goto err_hsm;
422 }
423
424 /* check main status, clearing INTRQ */
425 status = ata_chk_status(ap);
426 if (unlikely(status & ATA_BUSY))
427 goto err_hsm;
428
429 /* ack bmdma irq events */
430 ata_bmdma_irq_clear(ap);
431
432 /* kick HSM in the ass */
433 ata_hsm_move(ap, qc, status, 0);
434
435 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
436 qc->tf.protocol == ATA_PROT_ATAPI_DMA))
437 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
438
439 return;
440
441 err_hsm:
442 qc->err_mask |= AC_ERR_HSM;
443 freeze:
444 ata_port_freeze(ap);
445 }
446
447 static irqreturn_t sil_interrupt(int irq, void *dev_instance)
448 {
449 struct ata_host *host = dev_instance;
450 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
451 int handled = 0;
452 int i;
453
454 spin_lock(&host->lock);
455
456 for (i = 0; i < host->n_ports; i++) {
457 struct ata_port *ap = host->ports[i];
458 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
459
460 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
461 continue;
462
463 /* turn off SATA_IRQ if not supported */
464 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
465 bmdma2 &= ~SIL_DMA_SATA_IRQ;
466
467 if (bmdma2 == 0xffffffff ||
468 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
469 continue;
470
471 sil_host_intr(ap, bmdma2);
472 handled = 1;
473 }
474
475 spin_unlock(&host->lock);
476
477 return IRQ_RETVAL(handled);
478 }
479
480 static void sil_freeze(struct ata_port *ap)
481 {
482 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
483 u32 tmp;
484
485 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
486 writel(0, mmio_base + sil_port[ap->port_no].sien);
487
488 /* plug IRQ */
489 tmp = readl(mmio_base + SIL_SYSCFG);
490 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
491 writel(tmp, mmio_base + SIL_SYSCFG);
492 readl(mmio_base + SIL_SYSCFG); /* flush */
493 }
494
495 static void sil_thaw(struct ata_port *ap)
496 {
497 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
498 u32 tmp;
499
500 /* clear IRQ */
501 ata_chk_status(ap);
502 ata_bmdma_irq_clear(ap);
503
504 /* turn on SATA IRQ if supported */
505 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
506 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
507
508 /* turn on IRQ */
509 tmp = readl(mmio_base + SIL_SYSCFG);
510 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
511 writel(tmp, mmio_base + SIL_SYSCFG);
512 }
513
514 /**
515 * sil_dev_config - Apply device/host-specific errata fixups
516 * @ap: Port containing device to be examined
517 * @dev: Device to be examined
518 *
519 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
520 * device is known to be present, this function is called.
521 * We apply two errata fixups which are specific to Silicon Image,
522 * a Seagate and a Maxtor fixup.
523 *
524 * For certain Seagate devices, we must limit the maximum sectors
525 * to under 8K.
526 *
527 * For certain Maxtor devices, we must not program the drive
528 * beyond udma5.
529 *
530 * Both fixups are unfairly pessimistic. As soon as I get more
531 * information on these errata, I will create a more exhaustive
532 * list, and apply the fixups to only the specific
533 * devices/hosts/firmwares that need it.
534 *
535 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
536 * The Maxtor quirk is in the blacklist, but I'm keeping the original
537 * pessimistic fix for the following reasons...
538 * - There seems to be less info on it, only one device gleaned off the
539 * Windows driver, maybe only one is affected. More info would be greatly
540 * appreciated.
541 * - But then again UDMA5 is hardly anything to complain about
542 */
543 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
544 {
545 int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO;
546 unsigned int n, quirks = 0;
547 unsigned char model_num[ATA_ID_PROD_LEN + 1];
548
549 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
550
551 for (n = 0; sil_blacklist[n].product; n++)
552 if (!strcmp(sil_blacklist[n].product, model_num)) {
553 quirks = sil_blacklist[n].quirk;
554 break;
555 }
556
557 /* limit requests to 15 sectors */
558 if (slow_down ||
559 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
560 (quirks & SIL_QUIRK_MOD15WRITE))) {
561 if (print_info)
562 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
563 "errata fix (mod15write workaround)\n");
564 dev->max_sectors = 15;
565 return;
566 }
567
568 /* limit to udma5 */
569 if (quirks & SIL_QUIRK_UDMA5MAX) {
570 if (print_info)
571 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
572 "errata fix %s\n", model_num);
573 dev->udma_mask &= ATA_UDMA5;
574 return;
575 }
576 }
577
578 static void sil_init_controller(struct pci_dev *pdev,
579 int n_ports, unsigned long port_flags,
580 void __iomem *mmio_base)
581 {
582 u8 cls;
583 u32 tmp;
584 int i;
585
586 /* Initialize FIFO PCI bus arbitration */
587 cls = sil_get_device_cache_line(pdev);
588 if (cls) {
589 cls >>= 3;
590 cls++; /* cls = (line_size/8)+1 */
591 for (i = 0; i < n_ports; i++)
592 writew(cls << 8 | cls,
593 mmio_base + sil_port[i].fifo_cfg);
594 } else
595 dev_printk(KERN_WARNING, &pdev->dev,
596 "cache line size not set. Driver may not function\n");
597
598 /* Apply R_ERR on DMA activate FIS errata workaround */
599 if (port_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
600 int cnt;
601
602 for (i = 0, cnt = 0; i < n_ports; i++) {
603 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
604 if ((tmp & 0x3) != 0x01)
605 continue;
606 if (!cnt)
607 dev_printk(KERN_INFO, &pdev->dev,
608 "Applying R_ERR on DMA activate "
609 "FIS errata fix\n");
610 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
611 cnt++;
612 }
613 }
614
615 if (n_ports == 4) {
616 /* flip the magic "make 4 ports work" bit */
617 tmp = readl(mmio_base + sil_port[2].bmdma);
618 if ((tmp & SIL_INTR_STEERING) == 0)
619 writel(tmp | SIL_INTR_STEERING,
620 mmio_base + sil_port[2].bmdma);
621 }
622 }
623
624 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
625 {
626 static int printed_version;
627 struct device *dev = &pdev->dev;
628 struct ata_probe_ent *probe_ent;
629 void __iomem *mmio_base;
630 int rc;
631 unsigned int i;
632
633 if (!printed_version++)
634 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
635
636 rc = pcim_enable_device(pdev);
637 if (rc)
638 return rc;
639
640 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
641 if (rc == -EBUSY)
642 pcim_pin_device(pdev);
643 if (rc)
644 return rc;
645
646 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
647 if (rc)
648 return rc;
649 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
650 if (rc)
651 return rc;
652
653 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
654 if (probe_ent == NULL)
655 return -ENOMEM;
656
657 INIT_LIST_HEAD(&probe_ent->node);
658 probe_ent->dev = pci_dev_to_dev(pdev);
659 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
660 probe_ent->sht = sil_port_info[ent->driver_data].sht;
661 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
662 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
663 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
664 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
665 probe_ent->irq = pdev->irq;
666 probe_ent->irq_flags = IRQF_SHARED;
667 probe_ent->port_flags = sil_port_info[ent->driver_data].flags;
668
669 probe_ent->iomap = pcim_iomap_table(pdev);
670
671 mmio_base = probe_ent->iomap[SIL_MMIO_BAR];
672
673 for (i = 0; i < probe_ent->n_ports; i++) {
674 probe_ent->port[i].cmd_addr = mmio_base + sil_port[i].tf;
675 probe_ent->port[i].altstatus_addr =
676 probe_ent->port[i].ctl_addr = mmio_base + sil_port[i].ctl;
677 probe_ent->port[i].bmdma_addr = mmio_base + sil_port[i].bmdma;
678 probe_ent->port[i].scr_addr = mmio_base + sil_port[i].scr;
679 ata_std_ports(&probe_ent->port[i]);
680 }
681
682 sil_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags,
683 mmio_base);
684
685 pci_set_master(pdev);
686
687 if (!ata_device_add(probe_ent))
688 return -ENODEV;
689
690 devm_kfree(dev, probe_ent);
691 return 0;
692 }
693
694 #ifdef CONFIG_PM
695 static int sil_pci_device_resume(struct pci_dev *pdev)
696 {
697 struct ata_host *host = dev_get_drvdata(&pdev->dev);
698 int rc;
699
700 rc = ata_pci_device_do_resume(pdev);
701 if (rc)
702 return rc;
703
704 sil_init_controller(pdev, host->n_ports, host->ports[0]->flags,
705 host->iomap[SIL_MMIO_BAR]);
706 ata_host_resume(host);
707
708 return 0;
709 }
710 #endif
711
712 static int __init sil_init(void)
713 {
714 return pci_register_driver(&sil_pci_driver);
715 }
716
717 static void __exit sil_exit(void)
718 {
719 pci_unregister_driver(&sil_pci_driver);
720 }
721
722
723 module_init(sil_init);
724 module_exit(sil_exit);
Support for the Chinese Samsung S3C2440 based development boards