drivers/spi/omap_uwire.c

   1 /*
   2  * omap_uwire.c -- MicroWire interface driver for OMAP
   3  *
   4  * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
   5  *
   6  * Ported to 2.6 OMAP uwire interface.
   7  * Copyright (C) 2004 Texas Instruments.
   8  *
   9  * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
  10  *
  11  * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
  12  * Copyright (C) 2006 Nokia
  13  *
  14  * Many updates by Imre Deak <imre.deak@nokia.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * You should have received a copy of the GNU General Public License along
  33  * with this program; if not, write to the Free Software Foundation, Inc.,
  34  * 675 Mass Ave, Cambridge, MA 02139, USA.
  35  */
  36 #include <linux/kernel.h>
  37 #include <linux/init.h>
  38 #include <linux/delay.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/err.h>
  43 #include <linux/clk.h>
  44
  45 #include <linux/spi/spi.h>
  46 #include <linux/spi/spi_bitbang.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/irq.h>
  50 #include <mach/hardware.h>
  51 #include <asm/io.h>
  52 #include <asm/mach-types.h>
  53
  54 #include <mach/mux.h>
  55 #include <mach/omap730.h>       /* OMAP730_IO_CONF registers */
  56
  57
  58 /* FIXME address is now a platform device resource,
  59  * and irqs should show there too...
  60  */
  61 #define UWIRE_BASE_PHYS         0xFFFB3000
  62
  63 /* uWire Registers: */
  64 #define UWIRE_IO_SIZE 0x20
  65 #define UWIRE_TDR     0x00
  66 #define UWIRE_RDR     0x00
  67 #define UWIRE_CSR     0x01
  68 #define UWIRE_SR1     0x02
  69 #define UWIRE_SR2     0x03
  70 #define UWIRE_SR3     0x04
  71 #define UWIRE_SR4     0x05
  72 #define UWIRE_SR5     0x06
  73
  74 /* CSR bits */
  75 #define RDRB    (1 << 15)
  76 #define CSRB    (1 << 14)
  77 #define START   (1 << 13)
  78 #define CS_CMD  (1 << 12)
  79
  80 /* SR1 or SR2 bits */
  81 #define UWIRE_READ_FALLING_EDGE         0x0001
  82 #define UWIRE_READ_RISING_EDGE          0x0000
  83 #define UWIRE_WRITE_FALLING_EDGE        0x0000
  84 #define UWIRE_WRITE_RISING_EDGE         0x0002
  85 #define UWIRE_CS_ACTIVE_LOW             0x0000
  86 #define UWIRE_CS_ACTIVE_HIGH            0x0004
  87 #define UWIRE_FREQ_DIV_2                0x0000
  88 #define UWIRE_FREQ_DIV_4                0x0008
  89 #define UWIRE_FREQ_DIV_8                0x0010
  90 #define UWIRE_CHK_READY                 0x0020
  91 #define UWIRE_CLK_INVERTED              0x0040
  92
  93
  94 struct uwire_spi {
  95         struct spi_bitbang      bitbang;
  96         struct clk              *ck;
  97 };
  98
  99 struct uwire_state {
 100         unsigned        bits_per_word;
 101         unsigned        div1_idx;
 102 };
 103
 104 /* REVISIT compile time constant for idx_shift? */
 105 /*
 106  * Or, put it in a structure which is used throughout the driver;
 107  * that avoids having to issue two loads for each bit of static data.
 108  */
 109 static unsigned int uwire_idx_shift;
 110 static void __iomem *uwire_base;
 111
 112 static inline void uwire_write_reg(int idx, u16 val)
 113 {
 114         __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
 115 }
 116
 117 static inline u16 uwire_read_reg(int idx)
 118 {
 119         return __raw_readw(uwire_base + (idx << uwire_idx_shift));
 120 }
 121
 122 static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
 123 {
 124         u16     w, val = 0;
 125         int     shift, reg;
 126
 127         if (flags & UWIRE_CLK_INVERTED)
 128                 val ^= 0x03;
 129         val = flags & 0x3f;
 130         if (cs & 1)
 131                 shift = 6;
 132         else
 133                 shift = 0;
 134         if (cs <= 1)
 135                 reg = UWIRE_SR1;
 136         else
 137                 reg = UWIRE_SR2;
 138
 139         w = uwire_read_reg(reg);
 140         w &= ~(0x3f << shift);
 141         w |= val << shift;
 142         uwire_write_reg(reg, w);
 143 }
 144
 145 static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
 146 {
 147         u16 w;
 148         int c = 0;
 149         unsigned long max_jiffies = jiffies + HZ;
 150
 151         for (;;) {
 152                 w = uwire_read_reg(UWIRE_CSR);
 153                 if ((w & mask) == val)
 154                         break;
 155                 if (time_after(jiffies, max_jiffies)) {
 156                         printk(KERN_ERR "%s: timeout. reg=%#06x "
 157                                         "mask=%#06x val=%#06x\n",
 158                                __func__, w, mask, val);
 159                         return -1;
 160                 }
 161                 c++;
 162                 if (might_not_catch && c > 64)
 163                         break;
 164         }
 165         return 0;
 166 }
 167
 168 static void uwire_set_clk1_div(int div1_idx)
 169 {
 170         u16 w;
 171
 172         w = uwire_read_reg(UWIRE_SR3);
 173         w &= ~(0x03 << 1);
 174         w |= div1_idx << 1;
 175         uwire_write_reg(UWIRE_SR3, w);
 176 }
 177
 178 static void uwire_chipselect(struct spi_device *spi, int value)
 179 {
 180         struct  uwire_state *ust = spi->controller_state;
 181         u16     w;
 182         int     old_cs;
 183
 184
 185         BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
 186
 187         w = uwire_read_reg(UWIRE_CSR);
 188         old_cs = (w >> 10) & 0x03;
 189         if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
 190                 /* Deselect this CS, or the previous CS */
 191                 w &= ~CS_CMD;
 192                 uwire_write_reg(UWIRE_CSR, w);
 193         }
 194         /* activate specfied chipselect */
 195         if (value == BITBANG_CS_ACTIVE) {
 196                 uwire_set_clk1_div(ust->div1_idx);
 197                 /* invert clock? */
 198                 if (spi->mode & SPI_CPOL)
 199                         uwire_write_reg(UWIRE_SR4, 1);
 200                 else
 201                         uwire_write_reg(UWIRE_SR4, 0);
 202
 203                 w = spi->chip_select << 10;
 204                 w |= CS_CMD;
 205                 uwire_write_reg(UWIRE_CSR, w);
 206         }
 207 }
 208
 209 static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
 210 {
 211         struct uwire_state *ust = spi->controller_state;
 212         unsigned        len = t->len;
 213         unsigned        bits = ust->bits_per_word;
 214         unsigned        bytes;
 215         u16             val, w;
 216         int             status = 0;;
 217
 218         if (!t->tx_buf && !t->rx_buf)
 219                 return 0;
 220
 221         /* Microwire doesn't read and write concurrently */
 222         if (t->tx_buf && t->rx_buf)
 223                 return -EPERM;
 224
 225         w = spi->chip_select << 10;
 226         w |= CS_CMD;
 227
 228         if (t->tx_buf) {
 229                 const u8        *buf = t->tx_buf;
 230
 231                 /* NOTE:  DMA could be used for TX transfers */
 232
 233                 /* write one or two bytes at a time */
 234                 while (len >= 1) {
 235                         /* tx bit 15 is first sent; we byteswap multibyte words
 236                          * (msb-first) on the way out from memory.
 237                          */
 238                         val = *buf++;
 239                         if (bits > 8) {
 240                                 bytes = 2;
 241                                 val |= *buf++ << 8;
 242                         } else
 243                                 bytes = 1;
 244                         val <<= 16 - bits;
 245
 246 #ifdef  VERBOSE
 247                         pr_debug("%s: write-%d =%04x\n",
 248                                         spi->dev.bus_id, bits, val);
 249 #endif
 250                         if (wait_uwire_csr_flag(CSRB, 0, 0))
 251                                 goto eio;
 252
 253                         uwire_write_reg(UWIRE_TDR, val);
 254
 255                         /* start write */
 256                         val = START | w | (bits << 5);
 257
 258                         uwire_write_reg(UWIRE_CSR, val);
 259                         len -= bytes;
 260
 261                         /* Wait till write actually starts.
 262                          * This is needed with MPU clock 60+ MHz.
 263                          * REVISIT: we may not have time to catch it...
 264                          */
 265                         if (wait_uwire_csr_flag(CSRB, CSRB, 1))
 266                                 goto eio;
 267
 268                         status += bytes;
 269                 }
 270
 271                 /* REVISIT:  save this for later to get more i/o overlap */
 272                 if (wait_uwire_csr_flag(CSRB, 0, 0))
 273                         goto eio;
 274
 275         } else if (t->rx_buf) {
 276                 u8              *buf = t->rx_buf;
 277
 278                 /* read one or two bytes at a time */
 279                 while (len) {
 280                         if (bits > 8) {
 281                                 bytes = 2;
 282                         } else
 283                                 bytes = 1;
 284
 285                         /* start read */
 286                         val = START | w | (bits << 0);
 287                         uwire_write_reg(UWIRE_CSR, val);
 288                         len -= bytes;
 289
 290                         /* Wait till read actually starts */
 291                         (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
 292
 293                         if (wait_uwire_csr_flag(RDRB | CSRB,
 294                                                 RDRB, 0))
 295                                 goto eio;
 296
 297                         /* rx bit 0 is last received; multibyte words will
 298                          * be properly byteswapped on the way to memory.
 299                          */
 300                         val = uwire_read_reg(UWIRE_RDR);
 301                         val &= (1 << bits) - 1;
 302                         *buf++ = (u8) val;
 303                         if (bytes == 2)
 304                                 *buf++ = val >> 8;
 305                         status += bytes;
 306 #ifdef  VERBOSE
 307                         pr_debug("%s: read-%d =%04x\n",
 308                                         spi->dev.bus_id, bits, val);
 309 #endif
 310
 311                 }
 312         }
 313         return status;
 314 eio:
 315         return -EIO;
 316 }
 317
 318 static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 319 {
 320         struct uwire_state      *ust = spi->controller_state;
 321         struct uwire_spi        *uwire;
 322         unsigned                flags = 0;
 323         unsigned                bits;
 324         unsigned                hz;
 325         unsigned long           rate;
 326         int                     div1_idx;
 327         int                     div1;
 328         int                     div2;
 329         int                     status;
 330
 331         uwire = spi_master_get_devdata(spi->master);
 332
 333         if (spi->chip_select > 3) {
 334                 pr_debug("%s: cs%d?\n", spi->dev.bus_id, spi->chip_select);
 335                 status = -ENODEV;
 336                 goto done;
 337         }
 338
 339         bits = spi->bits_per_word;
 340         if (t != NULL && t->bits_per_word)
 341                 bits = t->bits_per_word;
 342         if (!bits)
 343                 bits = 8;
 344
 345         if (bits > 16) {
 346                 pr_debug("%s: wordsize %d?\n", spi->dev.bus_id, bits);
 347                 status = -ENODEV;
 348                 goto done;
 349         }
 350         ust->bits_per_word = bits;
 351
 352         /* mode 0..3, clock inverted separately;
 353          * standard nCS signaling;
 354          * don't treat DI=high as "not ready"
 355          */
 356         if (spi->mode & SPI_CS_HIGH)
 357                 flags |= UWIRE_CS_ACTIVE_HIGH;
 358
 359         if (spi->mode & SPI_CPOL)
 360                 flags |= UWIRE_CLK_INVERTED;
 361
 362         switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
 363         case SPI_MODE_0:
 364         case SPI_MODE_3:
 365                 flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
 366                 break;
 367         case SPI_MODE_1:
 368         case SPI_MODE_2:
 369                 flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
 370                 break;
 371         }
 372
 373         /* assume it's already enabled */
 374         rate = clk_get_rate(uwire->ck);
 375
 376         hz = spi->max_speed_hz;
 377         if (t != NULL && t->speed_hz)
 378                 hz = t->speed_hz;
 379
 380         if (!hz) {
 381                 pr_debug("%s: zero speed?\n", spi->dev.bus_id);
 382                 status = -EINVAL;
 383                 goto done;
 384         }
 385
 386         /* F_INT = mpu_xor_clk / DIV1 */
 387         for (div1_idx = 0; div1_idx < 4; div1_idx++) {
 388                 switch (div1_idx) {
 389                 case 0:
 390                         div1 = 2;
 391                         break;
 392                 case 1:
 393                         div1 = 4;
 394                         break;
 395                 case 2:
 396                         div1 = 7;
 397                         break;
 398                 default:
 399                 case 3:
 400                         div1 = 10;
 401                         break;
 402                 }
 403                 div2 = (rate / div1 + hz - 1) / hz;
 404                 if (div2 <= 8)
 405                         break;
 406         }
 407         if (div1_idx == 4) {
 408                 pr_debug("%s: lowest clock %ld, need %d\n",
 409                         spi->dev.bus_id, rate / 10 / 8, hz);
 410                 status = -EDOM;
 411                 goto done;
 412         }
 413
 414         /* we have to cache this and reset in uwire_chipselect as this is a
 415          * global parameter and another uwire device can change it under
 416          * us */
 417         ust->div1_idx = div1_idx;
 418         uwire_set_clk1_div(div1_idx);
 419
 420         rate /= div1;
 421
 422         switch (div2) {
 423         case 0:
 424         case 1:
 425         case 2:
 426                 flags |= UWIRE_FREQ_DIV_2;
 427                 rate /= 2;
 428                 break;
 429         case 3:
 430         case 4:
 431                 flags |= UWIRE_FREQ_DIV_4;
 432                 rate /= 4;
 433                 break;
 434         case 5:
 435         case 6:
 436         case 7:
 437         case 8:
 438                 flags |= UWIRE_FREQ_DIV_8;
 439                 rate /= 8;
 440                 break;
 441         }
 442         omap_uwire_configure_mode(spi->chip_select, flags);
 443         pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
 444                         __func__, flags,
 445                         clk_get_rate(uwire->ck) / 1000,
 446                         rate / 1000);
 447         status = 0;
 448 done:
 449         return status;
 450 }
 451
 452 /* the spi->mode bits understood by this driver: */
 453 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 454
 455 static int uwire_setup(struct spi_device *spi)
 456 {
 457         struct uwire_state *ust = spi->controller_state;
 458
 459         if (spi->mode & ~MODEBITS) {
 460                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 461                         spi->mode & ~MODEBITS);
 462                 return -EINVAL;
 463         }
 464
 465         if (ust == NULL) {
 466                 ust = kzalloc(sizeof(*ust), GFP_KERNEL);
 467                 if (ust == NULL)
 468                         return -ENOMEM;
 469                 spi->controller_state = ust;
 470         }
 471
 472         return uwire_setup_transfer(spi, NULL);
 473 }
 474
 475 static void uwire_cleanup(struct spi_device *spi)
 476 {
 477         kfree(spi->controller_state);
 478 }
 479
 480 static void uwire_off(struct uwire_spi *uwire)
 481 {
 482         uwire_write_reg(UWIRE_SR3, 0);
 483         clk_disable(uwire->ck);
 484         clk_put(uwire->ck);
 485         spi_master_put(uwire->bitbang.master);
 486 }
 487
 488 static int __init uwire_probe(struct platform_device *pdev)
 489 {
 490         struct spi_master       *master;
 491         struct uwire_spi        *uwire;
 492         int                     status;
 493
 494         master = spi_alloc_master(&pdev->dev, sizeof *uwire);
 495         if (!master)
 496                 return -ENODEV;
 497
 498         uwire = spi_master_get_devdata(master);
 499
 500         uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
 501         if (!uwire_base) {
 502                 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
 503                 spi_master_put(master);
 504                 return -ENOMEM;
 505         }
 506
 507         dev_set_drvdata(&pdev->dev, uwire);
 508
 509         uwire->ck = clk_get(&pdev->dev, "armxor_ck");
 510         if (!uwire->ck || IS_ERR(uwire->ck)) {
 511                 dev_dbg(&pdev->dev, "no mpu_xor_clk ?\n");
 512                 spi_master_put(master);
 513                 return -ENODEV;
 514         }
 515         clk_enable(uwire->ck);
 516
 517         if (cpu_is_omap730())
 518                 uwire_idx_shift = 1;
 519         else
 520                 uwire_idx_shift = 2;
 521
 522         uwire_write_reg(UWIRE_SR3, 1);
 523
 524         master->bus_num = 2;    /* "official" */
 525         master->num_chipselect = 4;
 526         master->setup = uwire_setup;
 527         master->cleanup = uwire_cleanup;
 528
 529         uwire->bitbang.master = master;
 530         uwire->bitbang.chipselect = uwire_chipselect;
 531         uwire->bitbang.setup_transfer = uwire_setup_transfer;
 532         uwire->bitbang.txrx_bufs = uwire_txrx;
 533
 534         status = spi_bitbang_start(&uwire->bitbang);
 535         if (status < 0) {
 536                 uwire_off(uwire);
 537                 iounmap(uwire_base);
 538         }
 539         return status;
 540 }
 541
 542 static int __exit uwire_remove(struct platform_device *pdev)
 543 {
 544         struct uwire_spi        *uwire = dev_get_drvdata(&pdev->dev);
 545         int                     status;
 546
 547         // FIXME remove all child devices, somewhere ...
 548
 549         status = spi_bitbang_stop(&uwire->bitbang);
 550         uwire_off(uwire);
 551         iounmap(uwire_base);
 552         return status;
 553 }
 554
 555 /* work with hotplug and coldplug */
 556 MODULE_ALIAS("platform:omap_uwire");
 557
 558 static struct platform_driver uwire_driver = {
 559         .driver = {
 560                 .name           = "omap_uwire",
 561                 .owner          = THIS_MODULE,
 562         },
 563         .remove         = __exit_p(uwire_remove),
 564         // suspend ... unuse ck
 565         // resume ... use ck
 566 };
 567
 568 static int __init omap_uwire_init(void)
 569 {
 570         /* FIXME move these into the relevant board init code. also, include
 571          * H3 support; it uses tsc2101 like H2 (on a different chipselect).
 572          */
 573
 574         if (machine_is_omap_h2()) {
 575                 /* defaults: W21 SDO, U18 SDI, V19 SCL */
 576                 omap_cfg_reg(N14_1610_UWIRE_CS0);
 577                 omap_cfg_reg(N15_1610_UWIRE_CS1);
 578         }
 579         if (machine_is_omap_perseus2()) {
 580                 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
 581                 int val = omap_readl(OMAP730_IO_CONF_9) & ~0x00EEE000;
 582                 omap_writel(val | 0x00AAA000, OMAP730_IO_CONF_9);
 583         }
 584
 585         return platform_driver_probe(&uwire_driver, uwire_probe);
 586 }
 587
 588 static void __exit omap_uwire_exit(void)
 589 {
 590         platform_driver_unregister(&uwire_driver);
 591 }
 592
 593 subsys_initcall(omap_uwire_init);
 594 module_exit(omap_uwire_exit);
 595
 596 MODULE_LICENSE("GPL");
 597