include/asm-ppc/system.h

   1 /*
   2  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   3  */
   4 #ifndef __PPC_SYSTEM_H
   5 #define __PPC_SYSTEM_H
   6
   7 #include <linux/kernel.h>
   8
   9 #include <asm/atomic.h>
  10 #include <asm/hw_irq.h>
  11
  12 /*
  13  * Memory barrier.
  14  * The sync instruction guarantees that all memory accesses initiated
  15  * by this processor have been performed (with respect to all other
  16  * mechanisms that access memory).  The eieio instruction is a barrier
  17  * providing an ordering (separately) for (a) cacheable stores and (b)
  18  * loads and stores to non-cacheable memory (e.g. I/O devices).
  19  *
  20  * mb() prevents loads and stores being reordered across this point.
  21  * rmb() prevents loads being reordered across this point.
  22  * wmb() prevents stores being reordered across this point.
  23  * read_barrier_depends() prevents data-dependent loads being reordered
  24  *      across this point (nop on PPC).
  25  *
  26  * We can use the eieio instruction for wmb, but since it doesn't
  27  * give any ordering guarantees about loads, we have to use the
  28  * stronger but slower sync instruction for mb and rmb.
  29  */
  30 #define mb()  __asm__ __volatile__ ("sync" : : : "memory")
  31 #define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
  32 #define wmb()  __asm__ __volatile__ ("eieio" : : : "memory")
  33 #define read_barrier_depends()  do { } while(0)
  34
  35 #define set_mb(var, value)      do { var = value; mb(); } while (0)
  36 #define set_wmb(var, value)     do { var = value; wmb(); } while (0)
  37
  38 #ifdef CONFIG_SMP
  39 #define smp_mb()        mb()
  40 #define smp_rmb()       rmb()
  41 #define smp_wmb()       __asm__ __volatile__ ("eieio" : : : "memory")
  42 #define smp_read_barrier_depends()      read_barrier_depends()
  43 #else
  44 #define smp_mb()        barrier()
  45 #define smp_rmb()       barrier()
  46 #define smp_wmb()       barrier()
  47 #define smp_read_barrier_depends()      do { } while(0)
  48 #endif /* CONFIG_SMP */
  49
  50 #ifdef __KERNEL__
  51 struct task_struct;
  52 struct pt_regs;
  53
  54 extern void print_backtrace(unsigned long *);
  55 extern void show_regs(struct pt_regs * regs);
  56 extern void flush_instruction_cache(void);
  57 extern void hard_reset_now(void);
  58 extern void poweroff_now(void);
  59 #ifdef CONFIG_6xx
  60 extern long _get_L2CR(void);
  61 extern long _get_L3CR(void);
  62 extern void _set_L2CR(unsigned long);
  63 extern void _set_L3CR(unsigned long);
  64 #else
  65 #define _get_L2CR()     0L
  66 #define _get_L3CR()     0L
  67 #define _set_L2CR(val)  do { } while(0)
  68 #define _set_L3CR(val)  do { } while(0)
  69 #endif
  70 extern void via_cuda_init(void);
  71 extern void pmac_nvram_init(void);
  72 extern void chrp_nvram_init(void);
  73 extern void read_rtc_time(void);
  74 extern void pmac_find_display(void);
  75 extern void giveup_fpu(struct task_struct *);
  76 extern void disable_kernel_fp(void);
  77 extern void enable_kernel_fp(void);
  78 extern void flush_fp_to_thread(struct task_struct *);
  79 extern void enable_kernel_altivec(void);
  80 extern void giveup_altivec(struct task_struct *);
  81 extern void load_up_altivec(struct task_struct *);
  82 extern int emulate_altivec(struct pt_regs *);
  83 extern void giveup_spe(struct task_struct *);
  84 extern void load_up_spe(struct task_struct *);
  85 extern int fix_alignment(struct pt_regs *);
  86 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
  87 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
  88
  89 #ifndef CONFIG_SMP
  90 extern void discard_lazy_cpu_state(void);
  91 #else
  92 static inline void discard_lazy_cpu_state(void)
  93 {
  94 }
  95 #endif
  96
  97 #ifdef CONFIG_ALTIVEC
  98 extern void flush_altivec_to_thread(struct task_struct *);
  99 #else
 100 static inline void flush_altivec_to_thread(struct task_struct *t)
 101 {
 102 }
 103 #endif
 104
 105 #ifdef CONFIG_SPE
 106 extern void flush_spe_to_thread(struct task_struct *);
 107 #else
 108 static inline void flush_spe_to_thread(struct task_struct *t)
 109 {
 110 }
 111 #endif
 112
 113 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 114 extern void cacheable_memzero(void *p, unsigned int nb);
 115 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 116 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 117 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
 118 extern int die(const char *, struct pt_regs *, long);
 119 extern void _exception(int, struct pt_regs *, int, unsigned long);
 120 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 121
 122 #ifdef CONFIG_BOOKE_WDT
 123 extern u32 booke_wdt_enabled;
 124 extern u32 booke_wdt_period;
 125 #endif /* CONFIG_BOOKE_WDT */
 126
 127 struct device_node;
 128 extern void note_scsi_host(struct device_node *, void *);
 129
 130 extern struct task_struct *__switch_to(struct task_struct *,
 131         struct task_struct *);
 132 #define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 133
 134 /*
 135  * On SMP systems, when the scheduler does migration-cost autodetection,
 136  * it needs a way to flush as much of the CPU's caches as possible.
 137  *
 138  * TODO: fill this in!
 139  */
 140 static inline void sched_cacheflush(void)
 141 {
 142 }
 143
 144 struct thread_struct;
 145 extern struct task_struct *_switch(struct thread_struct *prev,
 146                                    struct thread_struct *next);
 147
 148 extern unsigned int rtas_data;
 149
 150 static __inline__ unsigned long
 151 xchg_u32(volatile void *p, unsigned long val)
 152 {
 153         unsigned long prev;
 154
 155         __asm__ __volatile__ ("\n\
 156 1:      lwarx   %0,0,%2 \n"
 157         PPC405_ERR77(0,%2)
 158 "       stwcx.  %3,0,%2 \n\
 159         bne-    1b"
 160         : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
 161         : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
 162         : "cc", "memory");
 163
 164         return prev;
 165 }
 166
 167 /*
 168  * This function doesn't exist, so you'll get a linker error
 169  * if something tries to do an invalid xchg().
 170  */
 171 extern void __xchg_called_with_bad_pointer(void);
 172
 173 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 174 #define tas(ptr) (xchg((ptr),1))
 175
 176 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 177 {
 178         switch (size) {
 179         case 4:
 180                 return (unsigned long) xchg_u32(ptr, x);
 181 #if 0   /* xchg_u64 doesn't exist on 32-bit PPC */
 182         case 8:
 183                 return (unsigned long) xchg_u64(ptr, x);
 184 #endif /* 0 */
 185         }
 186         __xchg_called_with_bad_pointer();
 187         return x;
 188
 189
 190 }
 191
 192 extern inline void * xchg_ptr(void * m, void * val)
 193 {
 194         return (void *) xchg_u32(m, (unsigned long) val);
 195 }
 196
 197
 198 #define __HAVE_ARCH_CMPXCHG     1
 199
 200 static __inline__ unsigned long
 201 __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
 202 {
 203         unsigned int prev;
 204
 205         __asm__ __volatile__ ("\n\
 206 1:      lwarx   %0,0,%2 \n\
 207         cmpw    0,%0,%3 \n\
 208         bne     2f \n"
 209         PPC405_ERR77(0,%2)
 210 "       stwcx.  %4,0,%2 \n\
 211         bne-    1b\n"
 212 #ifdef CONFIG_SMP
 213 "       sync\n"
 214 #endif /* CONFIG_SMP */
 215 "2:"
 216         : "=&r" (prev), "=m" (*p)
 217         : "r" (p), "r" (old), "r" (new), "m" (*p)
 218         : "cc", "memory");
 219
 220         return prev;
 221 }
 222
 223 /* This function doesn't exist, so you'll get a linker error
 224    if something tries to do an invalid cmpxchg().  */
 225 extern void __cmpxchg_called_with_bad_pointer(void);
 226
 227 static __inline__ unsigned long
 228 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 229 {
 230         switch (size) {
 231         case 4:
 232                 return __cmpxchg_u32(ptr, old, new);
 233 #if 0   /* we don't have __cmpxchg_u64 on 32-bit PPC */
 234         case 8:
 235                 return __cmpxchg_u64(ptr, old, new);
 236 #endif /* 0 */
 237         }
 238         __cmpxchg_called_with_bad_pointer();
 239         return old;
 240 }
 241
 242 #define cmpxchg(ptr,o,n)                                                 \
 243   ({                                                                     \
 244      __typeof__(*(ptr)) _o_ = (o);                                       \
 245      __typeof__(*(ptr)) _n_ = (n);                                       \
 246      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 247                                     (unsigned long)_n_, sizeof(*(ptr))); \
 248   })
 249
 250 #define arch_align_stack(x) (x)
 251
 252 #endif /* __KERNEL__ */
 253 #endif /* __PPC_SYSTEM_H */