[CPUFREQ] Fix the p4-clockmod N60 errata workaround.
[linux-2.6/mini2440.git] / include / asm-m32r / assembler.h
blobb7f4d8aaeb469b0409103dd8057e3b6f80c2cc8f
1 #ifndef _ASM_M32R_ASSEMBLER_H
2 #define _ASM_M32R_ASSEMBLER_H
4 /*
5 * linux/asm-m32r/assembler.h
7 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
9 * This file contains M32R architecture specific macro definitions.
12 #include <linux/config.h>
14 #ifndef __STR
15 #ifdef __ASSEMBLY__
16 #define __STR(x) x
17 #else
18 #define __STR(x) #x
19 #endif
20 #endif /* __STR */
22 #ifdef CONFIG_SMP
23 #define M32R_LOCK __STR(lock)
24 #define M32R_UNLOCK __STR(unlock)
25 #else
26 #define M32R_LOCK __STR(ld)
27 #define M32R_UNLOCK __STR(st)
28 #endif
30 #ifdef __ASSEMBLY__
31 #undef ENTRY
32 #define ENTRY(name) ENTRY_M name
33 .macro ENTRY_M name
34 .global \name
35 ALIGN
36 \name:
37 .endm
38 #endif
41 /**
42 * LDIMM - load immediate value
43 * STI - enable interruption
44 * CLI - disable interruption
47 #ifdef __ASSEMBLY__
49 #define LDIMM(reg,x) LDIMM reg x
50 .macro LDIMM reg x
51 seth \reg, #high(\x)
52 or3 \reg, \reg, #low(\x)
53 .endm
55 #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
56 #define STI(reg) STI_M reg
57 .macro STI_M reg
58 setpsw #0x40 -> nop
59 ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
60 .endm
62 #define CLI(reg) CLI_M reg
63 .macro CLI_M reg
64 clrpsw #0x40 -> nop
65 ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
66 .endm
67 #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
68 #define STI(reg) STI_M reg
69 .macro STI_M reg
70 mvfc \reg, psw
71 or3 \reg, \reg, #0x0040
72 mvtc \reg, psw
73 .endm
75 #define CLI(reg) CLI_M reg
76 .macro CLI_M reg
77 mvfc \reg, psw
78 and3 \reg, \reg, #0xffbf
79 mvtc \reg, psw
80 .endm
81 #endif /* CONFIG_CHIP_M32102 */
83 .macro SAVE_ALL
84 push r0 ; orig_r0
85 push sp ; spi (r15)
86 push lr ; r14
87 push r13
88 mvfc r13, cr3 ; spu
89 push r13
90 mvfc r13, bbpc
91 push r13
92 mvfc r13, bbpsw
93 push r13
94 mvfc r13, bpc
95 push r13
96 mvfc r13, psw
97 push r13
98 #if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
99 mvfaclo r13, a1
100 push r13
101 mvfachi r13, a1
102 push r13
103 mvfaclo r13, a0
104 push r13
105 mvfachi r13, a0
106 push r13
107 #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
108 mvfaclo r13
109 push r13
110 mvfachi r13
111 push r13
112 #else
113 #error unknown isa configuration
114 #endif
115 ldi r13, #-1
116 push r13 ; syscall_nr (default: -1)
117 push r12
118 push r11
119 push r10
120 push r9
121 push r8
122 push r7
123 push r3
124 push r2
125 push r1
126 push r0
127 addi sp, #-4 ; room for implicit pt_regs parameter
128 push r6
129 push r5
130 push r4
131 .endm
133 .macro RESTORE_ALL
134 pop r4
135 pop r5
136 pop r6
137 addi sp, #4
138 pop r0
139 pop r1
140 pop r2
141 pop r3
142 pop r7
143 pop r8
144 pop r9
145 pop r10
146 pop r11
147 pop r12
148 addi r15, #4 ; Skip syscall number
149 #if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
150 pop r13
151 mvtachi r13, a0
152 pop r13
153 mvtaclo r13, a0
154 pop r13
155 mvtachi r13, a1
156 pop r13
157 mvtaclo r13, a1
158 #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
159 pop r13
160 mvtachi r13
161 pop r13
162 mvtaclo r13
163 #else
164 #error unknown isa configuration
165 #endif
166 pop r14
167 mvtc r14, psw
168 pop r14
169 mvtc r14, bpc
170 addi sp, #8 ; Skip bbpsw, bbpc
171 pop r14
172 mvtc r14, cr3 ; spu
173 pop r13
174 pop lr ; r14
175 pop sp ; spi (r15)
176 addi sp, #4 ; Skip orig_r0
177 .fillinsn
178 1: rte
179 .section .fixup,"ax"
180 2: bl do_exit
181 .previous
182 .section __ex_table,"a"
183 ALIGN
184 .long 1b, 2b
185 .previous
186 .endm
188 #define GET_CURRENT(reg) get_current reg
189 .macro get_current reg
190 ldi \reg, #-8192
191 and \reg, sp
192 .endm
194 #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
195 .macro SWITCH_TO_KERNEL_STACK
196 ; switch to kernel stack (spi)
197 clrpsw #0x80 -> nop
198 .endm
199 #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
200 .macro SWITCH_TO_KERNEL_STACK
201 push r0 ; save r0 for working
202 mvfc r0, psw
203 and3 r0, r0, #0x00ff7f
204 mvtc r0, psw
205 slli r0, #16
206 bltz r0, 1f ; check BSM-bit
208 ;; called from kernel context: previous stack = spi
209 pop r0 ; retrieve r0
210 bra 2f
211 .fillinsn
213 ;; called from user context: previous stack = spu
214 mvfc r0, cr3 ; spu
215 addi r0, #4
216 mvtc r0, cr3 ; spu
217 ld r0, @(-4,r0) ; retrieve r0
218 .fillinsn
220 .endm
221 #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
223 #endif /* __ASSEMBLY__ */
225 #endif /* _ASM_M32R_ASSEMBLER_H */