include/asm-ia64/pgtable.h

   1 #ifndef _ASM_IA64_PGTABLE_H
   2 #define _ASM_IA64_PGTABLE_H
   3
   4 /*
   5  * This file contains the functions and defines necessary to modify and use
   6  * the IA-64 page table tree.
   7  *
   8  * This hopefully works with any (fixed) IA-64 page-size, as defined
   9  * in <asm/page.h>.
  10  *
  11  * Copyright (C) 1998-2005 Hewlett-Packard Co
  12  *      David Mosberger-Tang <davidm@hpl.hp.com>
  13  */
  14
  15 #include <linux/config.h>
  16
  17 #include <asm/mman.h>
  18 #include <asm/page.h>
  19 #include <asm/processor.h>
  20 #include <asm/system.h>
  21 #include <asm/types.h>
  22
  23 #define IA64_MAX_PHYS_BITS      50      /* max. number of physical address bits (architected) */
  24
  25 /*
  26  * First, define the various bits in a PTE.  Note that the PTE format
  27  * matches the VHPT short format, the firt doubleword of the VHPD long
  28  * format, and the first doubleword of the TLB insertion format.
  29  */
  30 #define _PAGE_P_BIT             0
  31 #define _PAGE_A_BIT             5
  32 #define _PAGE_D_BIT             6
  33
  34 #define _PAGE_P                 (1 << _PAGE_P_BIT)      /* page present bit */
  35 #define _PAGE_MA_WB             (0x0 <<  2)     /* write back memory attribute */
  36 #define _PAGE_MA_UC             (0x4 <<  2)     /* uncacheable memory attribute */
  37 #define _PAGE_MA_UCE            (0x5 <<  2)     /* UC exported attribute */
  38 #define _PAGE_MA_WC             (0x6 <<  2)     /* write coalescing memory attribute */
  39 #define _PAGE_MA_NAT            (0x7 <<  2)     /* not-a-thing attribute */
  40 #define _PAGE_MA_MASK           (0x7 <<  2)
  41 #define _PAGE_PL_0              (0 <<  7)       /* privilege level 0 (kernel) */
  42 #define _PAGE_PL_1              (1 <<  7)       /* privilege level 1 (unused) */
  43 #define _PAGE_PL_2              (2 <<  7)       /* privilege level 2 (unused) */
  44 #define _PAGE_PL_3              (3 <<  7)       /* privilege level 3 (user) */
  45 #define _PAGE_PL_MASK           (3 <<  7)
  46 #define _PAGE_AR_R              (0 <<  9)       /* read only */
  47 #define _PAGE_AR_RX             (1 <<  9)       /* read & execute */
  48 #define _PAGE_AR_RW             (2 <<  9)       /* read & write */
  49 #define _PAGE_AR_RWX            (3 <<  9)       /* read, write & execute */
  50 #define _PAGE_AR_R_RW           (4 <<  9)       /* read / read & write */
  51 #define _PAGE_AR_RX_RWX         (5 <<  9)       /* read & exec / read, write & exec */
  52 #define _PAGE_AR_RWX_RW         (6 <<  9)       /* read, write & exec / read & write */
  53 #define _PAGE_AR_X_RX           (7 <<  9)       /* exec & promote / read & exec */
  54 #define _PAGE_AR_MASK           (7 <<  9)
  55 #define _PAGE_AR_SHIFT          9
  56 #define _PAGE_A                 (1 << _PAGE_A_BIT)      /* page accessed bit */
  57 #define _PAGE_D                 (1 << _PAGE_D_BIT)      /* page dirty bit */
  58 #define _PAGE_PPN_MASK          (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
  59 #define _PAGE_ED                (__IA64_UL(1) << 52)    /* exception deferral */
  60 #define _PAGE_PROTNONE          (__IA64_UL(1) << 63)
  61
  62 /* Valid only for a PTE with the present bit cleared: */
  63 #define _PAGE_FILE              (1 << 1)                /* see swap & file pte remarks below */
  64
  65 #define _PFN_MASK               _PAGE_PPN_MASK
  66 /* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
  67 #define _PAGE_CHG_MASK  (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
  68
  69 #define _PAGE_SIZE_4K   12
  70 #define _PAGE_SIZE_8K   13
  71 #define _PAGE_SIZE_16K  14
  72 #define _PAGE_SIZE_64K  16
  73 #define _PAGE_SIZE_256K 18
  74 #define _PAGE_SIZE_1M   20
  75 #define _PAGE_SIZE_4M   22
  76 #define _PAGE_SIZE_16M  24
  77 #define _PAGE_SIZE_64M  26
  78 #define _PAGE_SIZE_256M 28
  79 #define _PAGE_SIZE_1G   30
  80 #define _PAGE_SIZE_4G   32
  81
  82 #define __ACCESS_BITS           _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
  83 #define __DIRTY_BITS_NO_ED      _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
  84 #define __DIRTY_BITS            _PAGE_ED | __DIRTY_BITS_NO_ED
  85
  86 /*
  87  * How many pointers will a page table level hold expressed in shift
  88  */
  89 #define PTRS_PER_PTD_SHIFT      (PAGE_SHIFT-3)
  90
  91 /*
  92  * Definitions for fourth level:
  93  */
  94 #define PTRS_PER_PTE    (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))
  95
  96 /*
  97  * Definitions for third level:
  98  *
  99  * PMD_SHIFT determines the size of the area a third-level page table
 100  * can map.
 101  */
 102 #define PMD_SHIFT       (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT))
 103 #define PMD_SIZE        (1UL << PMD_SHIFT)
 104 #define PMD_MASK        (~(PMD_SIZE-1))
 105 #define PTRS_PER_PMD    (1UL << (PTRS_PER_PTD_SHIFT))
 106
 107 #ifdef CONFIG_PGTABLE_4
 108 /*
 109  * Definitions for second level:
 110  *
 111  * PUD_SHIFT determines the size of the area a second-level page table
 112  * can map.
 113  */
 114 #define PUD_SHIFT       (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
 115 #define PUD_SIZE        (1UL << PUD_SHIFT)
 116 #define PUD_MASK        (~(PUD_SIZE-1))
 117 #define PTRS_PER_PUD    (1UL << (PTRS_PER_PTD_SHIFT))
 118 #endif
 119
 120 /*
 121  * Definitions for first level:
 122  *
 123  * PGDIR_SHIFT determines what a first-level page table entry can map.
 124  */
 125 #ifdef CONFIG_PGTABLE_4
 126 #define PGDIR_SHIFT             (PUD_SHIFT + (PTRS_PER_PTD_SHIFT))
 127 #else
 128 #define PGDIR_SHIFT             (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
 129 #endif
 130 #define PGDIR_SIZE              (__IA64_UL(1) << PGDIR_SHIFT)
 131 #define PGDIR_MASK              (~(PGDIR_SIZE-1))
 132 #define PTRS_PER_PGD_SHIFT      PTRS_PER_PTD_SHIFT
 133 #define PTRS_PER_PGD            (1UL << PTRS_PER_PGD_SHIFT)
 134 #define USER_PTRS_PER_PGD       (5*PTRS_PER_PGD/8)      /* regions 0-4 are user regions */
 135 #define FIRST_USER_ADDRESS      0
 136
 137 /*
 138  * All the normal masks have the "page accessed" bits on, as any time
 139  * they are used, the page is accessed. They are cleared only by the
 140  * page-out routines.
 141  */
 142 #define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_A)
 143 #define PAGE_SHARED     __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
 144 #define PAGE_READONLY   __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
 145 #define PAGE_COPY       __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
 146 #define PAGE_COPY_EXEC  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
 147 #define PAGE_GATE       __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
 148 #define PAGE_KERNEL     __pgprot(__DIRTY_BITS  | _PAGE_PL_0 | _PAGE_AR_RWX)
 149 #define PAGE_KERNELRX   __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
 150
 151 # ifndef __ASSEMBLY__
 152
 153 #include <linux/sched.h>        /* for mm_struct */
 154 #include <asm/bitops.h>
 155 #include <asm/cacheflush.h>
 156 #include <asm/mmu_context.h>
 157 #include <asm/processor.h>
 158
 159 /*
 160  * Next come the mappings that determine how mmap() protection bits
 161  * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented.  The
 162  * _P version gets used for a private shared memory segment, the _S
 163  * version gets used for a shared memory segment with MAP_SHARED on.
 164  * In a private shared memory segment, we do a copy-on-write if a task
 165  * attempts to write to the page.
 166  */
 167         /* xwr */
 168 #define __P000  PAGE_NONE
 169 #define __P001  PAGE_READONLY
 170 #define __P010  PAGE_READONLY   /* write to priv pg -> copy & make writable */
 171 #define __P011  PAGE_READONLY   /* ditto */
 172 #define __P100  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
 173 #define __P101  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
 174 #define __P110  PAGE_COPY_EXEC
 175 #define __P111  PAGE_COPY_EXEC
 176
 177 #define __S000  PAGE_NONE
 178 #define __S001  PAGE_READONLY
 179 #define __S010  PAGE_SHARED     /* we don't have (and don't need) write-only */
 180 #define __S011  PAGE_SHARED
 181 #define __S100  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
 182 #define __S101  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
 183 #define __S110  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
 184 #define __S111  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
 185
 186 #define pgd_ERROR(e)    printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
 187 #ifdef CONFIG_PGTABLE_4
 188 #define pud_ERROR(e)    printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
 189 #endif
 190 #define pmd_ERROR(e)    printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
 191 #define pte_ERROR(e)    printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
 192
 193
 194 /*
 195  * Some definitions to translate between mem_map, PTEs, and page addresses:
 196  */
 197
 198
 199 /* Quick test to see if ADDR is a (potentially) valid physical address. */
 200 static inline long
 201 ia64_phys_addr_valid (unsigned long addr)
 202 {
 203         return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
 204 }
 205
 206 /*
 207  * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
 208  * memory.  For the return value to be meaningful, ADDR must be >=
 209  * PAGE_OFFSET.  This operation can be relatively expensive (e.g.,
 210  * require a hash-, or multi-level tree-lookup or something of that
 211  * sort) but it guarantees to return TRUE only if accessing the page
 212  * at that address does not cause an error.  Note that there may be
 213  * addresses for which kern_addr_valid() returns FALSE even though an
 214  * access would not cause an error (e.g., this is typically true for
 215  * memory mapped I/O regions.
 216  *
 217  * XXX Need to implement this for IA-64.
 218  */
 219 #define kern_addr_valid(addr)   (1)
 220
 221
 222 /*
 223  * Now come the defines and routines to manage and access the three-level
 224  * page table.
 225  */
 226
 227 /*
 228  * On some architectures, special things need to be done when setting
 229  * the PTE in a page table.  Nothing special needs to be on IA-64.
 230  */
 231 #define set_pte(ptep, pteval)   (*(ptep) = (pteval))
 232 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
 233
 234 #define VMALLOC_START           (RGN_BASE(RGN_GATE) + 0x200000000UL)
 235 #ifdef CONFIG_VIRTUAL_MEM_MAP
 236 # define VMALLOC_END_INIT       (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
 237 # define VMALLOC_END            vmalloc_end
 238   extern unsigned long vmalloc_end;
 239 #else
 240 # define VMALLOC_END            (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
 241 #endif
 242
 243 /* fs/proc/kcore.c */
 244 #define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
 245 #define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
 246
 247 #define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3)
 248 #define RGN_MAP_LIMIT   ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE)    /* per region addr limit */
 249
 250 /*
 251  * Conversion functions: convert page frame number (pfn) and a protection value to a page
 252  * table entry (pte).
 253  */
 254 #define pfn_pte(pfn, pgprot) \
 255 ({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
 256
 257 /* Extract pfn from pte.  */
 258 #define pte_pfn(_pte)           ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
 259
 260 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 261
 262 /* This takes a physical page address that is used by the remapping functions */
 263 #define mk_pte_phys(physpage, pgprot) \
 264 ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
 265
 266 #define pte_modify(_pte, newprot) \
 267         (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
 268
 269 #define pte_none(pte)                   (!pte_val(pte))
 270 #define pte_present(pte)                (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
 271 #define pte_clear(mm,addr,pte)          (pte_val(*(pte)) = 0UL)
 272 /* pte_page() returns the "struct page *" corresponding to the PTE: */
 273 #define pte_page(pte)                   virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
 274
 275 #define pmd_none(pmd)                   (!pmd_val(pmd))
 276 #define pmd_bad(pmd)                    (!ia64_phys_addr_valid(pmd_val(pmd)))
 277 #define pmd_present(pmd)                (pmd_val(pmd) != 0UL)
 278 #define pmd_clear(pmdp)                 (pmd_val(*(pmdp)) = 0UL)
 279 #define pmd_page_kernel(pmd)            ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
 280 #define pmd_page(pmd)                   virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
 281
 282 #define pud_none(pud)                   (!pud_val(pud))
 283 #define pud_bad(pud)                    (!ia64_phys_addr_valid(pud_val(pud)))
 284 #define pud_present(pud)                (pud_val(pud) != 0UL)
 285 #define pud_clear(pudp)                 (pud_val(*(pudp)) = 0UL)
 286 #define pud_page(pud)                   ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
 287
 288 #ifdef CONFIG_PGTABLE_4
 289 #define pgd_none(pgd)                   (!pgd_val(pgd))
 290 #define pgd_bad(pgd)                    (!ia64_phys_addr_valid(pgd_val(pgd)))
 291 #define pgd_present(pgd)                (pgd_val(pgd) != 0UL)
 292 #define pgd_clear(pgdp)                 (pgd_val(*(pgdp)) = 0UL)
 293 #define pgd_page(pgd)                   ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
 294 #endif
 295
 296 /*
 297  * The following have defined behavior only work if pte_present() is true.
 298  */
 299 #define pte_user(pte)           ((pte_val(pte) & _PAGE_PL_MASK) == _PAGE_PL_3)
 300 #define pte_read(pte)           (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6)
 301 #define pte_write(pte)  ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
 302 #define pte_exec(pte)           ((pte_val(pte) & _PAGE_AR_RX) != 0)
 303 #define pte_dirty(pte)          ((pte_val(pte) & _PAGE_D) != 0)
 304 #define pte_young(pte)          ((pte_val(pte) & _PAGE_A) != 0)
 305 #define pte_file(pte)           ((pte_val(pte) & _PAGE_FILE) != 0)
 306 /*
 307  * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
 308  * access rights:
 309  */
 310 #define pte_wrprotect(pte)      (__pte(pte_val(pte) & ~_PAGE_AR_RW))
 311 #define pte_mkwrite(pte)        (__pte(pte_val(pte) | _PAGE_AR_RW))
 312 #define pte_mkexec(pte)         (__pte(pte_val(pte) | _PAGE_AR_RX))
 313 #define pte_mkold(pte)          (__pte(pte_val(pte) & ~_PAGE_A))
 314 #define pte_mkyoung(pte)        (__pte(pte_val(pte) | _PAGE_A))
 315 #define pte_mkclean(pte)        (__pte(pte_val(pte) & ~_PAGE_D))
 316 #define pte_mkdirty(pte)        (__pte(pte_val(pte) | _PAGE_D))
 317 #define pte_mkhuge(pte)         (__pte(pte_val(pte) | _PAGE_P))
 318
 319 /*
 320  * Macro to a page protection value as "uncacheable".  Note that "protection" is really a
 321  * misnomer here as the protection value contains the memory attribute bits, dirty bits,
 322  * and various other bits as well.
 323  */
 324 #define pgprot_noncached(prot)          __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
 325
 326 /*
 327  * Macro to make mark a page protection value as "write-combining".
 328  * Note that "protection" is really a misnomer here as the protection
 329  * value contains the memory attribute bits, dirty bits, and various
 330  * other bits as well.  Accesses through a write-combining translation
 331  * works bypasses the caches, but does allow for consecutive writes to
 332  * be combined into single (but larger) write transactions.
 333  */
 334 #define pgprot_writecombine(prot)       __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
 335
 336 static inline unsigned long
 337 pgd_index (unsigned long address)
 338 {
 339         unsigned long region = address >> 61;
 340         unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
 341
 342         return (region << (PAGE_SHIFT - 6)) | l1index;
 343 }
 344
 345 /* The offset in the 1-level directory is given by the 3 region bits
 346    (61..63) and the level-1 bits.  */
 347 static inline pgd_t*
 348 pgd_offset (struct mm_struct *mm, unsigned long address)
 349 {
 350         return mm->pgd + pgd_index(address);
 351 }
 352
 353 /* In the kernel's mapped region we completely ignore the region number
 354    (since we know it's in region number 5). */
 355 #define pgd_offset_k(addr) \
 356         (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
 357
 358 /* Look up a pgd entry in the gate area.  On IA-64, the gate-area
 359    resides in the kernel-mapped segment, hence we use pgd_offset_k()
 360    here.  */
 361 #define pgd_offset_gate(mm, addr)       pgd_offset_k(addr)
 362
 363 #ifdef CONFIG_PGTABLE_4
 364 /* Find an entry in the second-level page table.. */
 365 #define pud_offset(dir,addr) \
 366         ((pud_t *) pgd_page(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
 367 #endif
 368
 369 /* Find an entry in the third-level page table.. */
 370 #define pmd_offset(dir,addr) \
 371         ((pmd_t *) pud_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
 372
 373 /*
 374  * Find an entry in the third-level page table.  This looks more complicated than it
 375  * should be because some platforms place page tables in high memory.
 376  */
 377 #define pte_index(addr)         (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 378 #define pte_offset_kernel(dir,addr)     ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr))
 379 #define pte_offset_map(dir,addr)        pte_offset_kernel(dir, addr)
 380 #define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
 381 #define pte_unmap(pte)                  do { } while (0)
 382 #define pte_unmap_nested(pte)           do { } while (0)
 383
 384 /* atomic versions of the some PTE manipulations: */
 385
 386 static inline int
 387 ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
 388 {
 389 #ifdef CONFIG_SMP
 390         if (!pte_young(*ptep))
 391                 return 0;
 392         return test_and_clear_bit(_PAGE_A_BIT, ptep);
 393 #else
 394         pte_t pte = *ptep;
 395         if (!pte_young(pte))
 396                 return 0;
 397         set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
 398         return 1;
 399 #endif
 400 }
 401
 402 static inline int
 403 ptep_test_and_clear_dirty (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
 404 {
 405 #ifdef CONFIG_SMP
 406         if (!pte_dirty(*ptep))
 407                 return 0;
 408         return test_and_clear_bit(_PAGE_D_BIT, ptep);
 409 #else
 410         pte_t pte = *ptep;
 411         if (!pte_dirty(pte))
 412                 return 0;
 413         set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte));
 414         return 1;
 415 #endif
 416 }
 417
 418 static inline pte_t
 419 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 420 {
 421 #ifdef CONFIG_SMP
 422         return __pte(xchg((long *) ptep, 0));
 423 #else
 424         pte_t pte = *ptep;
 425         pte_clear(mm, addr, ptep);
 426         return pte;
 427 #endif
 428 }
 429
 430 static inline void
 431 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 432 {
 433 #ifdef CONFIG_SMP
 434         unsigned long new, old;
 435
 436         do {
 437                 old = pte_val(*ptep);
 438                 new = pte_val(pte_wrprotect(__pte (old)));
 439         } while (cmpxchg((unsigned long *) ptep, old, new) != old);
 440 #else
 441         pte_t old_pte = *ptep;
 442         set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
 443 #endif
 444 }
 445
 446 static inline int
 447 pte_same (pte_t a, pte_t b)
 448 {
 449         return pte_val(a) == pte_val(b);
 450 }
 451
 452 #define update_mmu_cache(vma, address, pte) do { } while (0)
 453
 454 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 455 extern void paging_init (void);
 456
 457 /*
 458  * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
 459  *       bits in the swap-type field of the swap pte.  It would be nice to
 460  *       enforce that, but we can't easily include <linux/swap.h> here.
 461  *       (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
 462  *
 463  * Format of swap pte:
 464  *      bit   0   : present bit (must be zero)
 465  *      bit   1   : _PAGE_FILE (must be zero)
 466  *      bits  2- 8: swap-type
 467  *      bits  9-62: swap offset
 468  *      bit  63   : _PAGE_PROTNONE bit
 469  *
 470  * Format of file pte:
 471  *      bit   0   : present bit (must be zero)
 472  *      bit   1   : _PAGE_FILE (must be one)
 473  *      bits  2-62: file_offset/PAGE_SIZE
 474  *      bit  63   : _PAGE_PROTNONE bit
 475  */
 476 #define __swp_type(entry)               (((entry).val >> 2) & 0x7f)
 477 #define __swp_offset(entry)             (((entry).val << 1) >> 10)
 478 #define __swp_entry(type,offset)        ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) })
 479 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 480 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 481
 482 #define PTE_FILE_MAX_BITS               61
 483 #define pte_to_pgoff(pte)               ((pte_val(pte) << 1) >> 3)
 484 #define pgoff_to_pte(off)               ((pte_t) { ((off) << 2) | _PAGE_FILE })
 485
 486 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 487                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 488
 489 #define MK_IOSPACE_PFN(space, pfn)      (pfn)
 490 #define GET_IOSPACE(pfn)                0
 491 #define GET_PFN(pfn)                    (pfn)
 492
 493 /*
 494  * ZERO_PAGE is a global shared page that is always zero: used
 495  * for zero-mapped memory areas etc..
 496  */
 497 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
 498 extern struct page *zero_page_memmap_ptr;
 499 #define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
 500
 501 /* We provide our own get_unmapped_area to cope with VA holes for userland */
 502 #define HAVE_ARCH_UNMAPPED_AREA
 503
 504 #ifdef CONFIG_HUGETLB_PAGE
 505 #define HUGETLB_PGDIR_SHIFT     (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
 506 #define HUGETLB_PGDIR_SIZE      (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
 507 #define HUGETLB_PGDIR_MASK      (~(HUGETLB_PGDIR_SIZE-1))
 508 struct mmu_gather;
 509 void hugetlb_free_pgd_range(struct mmu_gather **tlb, unsigned long addr,
 510                 unsigned long end, unsigned long floor, unsigned long ceiling);
 511 #endif
 512
 513 /*
 514  * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
 515  * information.  However, we use this routine to take care of any (delayed) i-cache
 516  * flushing that may be necessary.
 517  */
 518 extern void lazy_mmu_prot_update (pte_t pte);
 519
 520 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 521 /*
 522  * Update PTEP with ENTRY, which is guaranteed to be a less
 523  * restrictive PTE.  That is, ENTRY may have the ACCESSED, DIRTY, and
 524  * WRITABLE bits turned on, when the value at PTEP did not.  The
 525  * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
 526  *
 527  * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
 528  * having to worry about races.  On SMP machines, there are only two
 529  * cases where this is true:
 530  *
 531  *      (1) *PTEP has the PRESENT bit turned OFF
 532  *      (2) ENTRY has the DIRTY bit turned ON
 533  *
 534  * On ia64, we could implement this routine with a cmpxchg()-loop
 535  * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
 536  * However, like on x86, we can get a more streamlined version by
 537  * observing that it is OK to drop ACCESSED bit updates when
 538  * SAFELY_WRITABLE is FALSE.  Besides being rare, all that would do is
 539  * result in an extra Access-bit fault, which would then turn on the
 540  * ACCESSED bit in the low-level fault handler (iaccess_bit or
 541  * daccess_bit in ivt.S).
 542  */
 543 #ifdef CONFIG_SMP
 544 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable)       \
 545 do {                                                                                    \
 546         if (__safely_writable) {                                                        \
 547                 set_pte(__ptep, __entry);                                               \
 548                 flush_tlb_page(__vma, __addr);                                          \
 549         }                                                                               \
 550 } while (0)
 551 #else
 552 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable)       \
 553         ptep_establish(__vma, __addr, __ptep, __entry)
 554 #endif
 555
 556 #  ifdef CONFIG_VIRTUAL_MEM_MAP
 557   /* arch mem_map init routine is needed due to holes in a virtual mem_map */
 558 #   define __HAVE_ARCH_MEMMAP_INIT
 559     extern void memmap_init (unsigned long size, int nid, unsigned long zone,
 560                              unsigned long start_pfn);
 561 #  endif /* CONFIG_VIRTUAL_MEM_MAP */
 562 # endif /* !__ASSEMBLY__ */
 563
 564 /*
 565  * Identity-mapped regions use a large page size.  We'll call such large pages
 566  * "granules".  If you can think of a better name that's unambiguous, let me
 567  * know...
 568  */
 569 #if defined(CONFIG_IA64_GRANULE_64MB)
 570 # define IA64_GRANULE_SHIFT     _PAGE_SIZE_64M
 571 #elif defined(CONFIG_IA64_GRANULE_16MB)
 572 # define IA64_GRANULE_SHIFT     _PAGE_SIZE_16M
 573 #endif
 574 #define IA64_GRANULE_SIZE       (1 << IA64_GRANULE_SHIFT)
 575 /*
 576  * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
 577  */
 578 #define KERNEL_TR_PAGE_SHIFT    _PAGE_SIZE_64M
 579 #define KERNEL_TR_PAGE_SIZE     (1 << KERNEL_TR_PAGE_SHIFT)
 580
 581 /*
 582  * No page table caches to initialise
 583  */
 584 #define pgtable_cache_init()    do { } while (0)
 585
 586 /* These tell get_user_pages() that the first gate page is accessible from user-level.  */
 587 #define FIXADDR_USER_START      GATE_ADDR
 588 #ifdef HAVE_BUGGY_SEGREL
 589 # define FIXADDR_USER_END       (GATE_ADDR + 2*PAGE_SIZE)
 590 #else
 591 # define FIXADDR_USER_END       (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
 592 #endif
 593
 594 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 595 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 596 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 597 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 598 #define __HAVE_ARCH_PTE_SAME
 599 #define __HAVE_ARCH_PGD_OFFSET_GATE
 600 #define __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
 601
 602 #ifndef CONFIG_PGTABLE_4
 603 #include <asm-generic/pgtable-nopud.h>
 604 #endif
 605 #include <asm-generic/pgtable.h>
 606
 607 #endif /* _ASM_IA64_PGTABLE_H */