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[CPUFREQ] Fix the p4-clockmod N60 errata workaround.
[linux-2.6/mini2440.git] / drivers / serial / pmac_zilog.c
blob9b7ed58cb53b53a6800851d40d22ba41743668bb
1 /*
2 * linux/drivers/serial/pmac_zilog.c
3 *
4 * Driver for PowerMac Z85c30 based ESCC cell found in the
5 * "macio" ASICs of various PowerMac models
6 *
7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
10 * and drivers/serial/sunzilog.c by David S. Miller
11 *
12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
13 * adapted special tweaks needed for us. I don't think it's worth
14 * merging back those though. The DMA code still has to get in
15 * and once done, I expect that driver to remain fairly stable in
16 * the long term, unless we change the driver model again...
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
33 * - Enable BREAK interrupt
34 * - Add support for sysreq
35 *
36 * TODO: - Add DMA support
37 * - Defer port shutdown to a few seconds after close
38 * - maybe put something right into uap->clk_divisor
39 */
40
41 #undef DEBUG
42 #undef DEBUG_HARD
43 #undef USE_CTRL_O_SYSRQ
44
45 #include <linux/config.h>
46 #include <linux/module.h>
47 #include <linux/tty.h>
48
49 #include <linux/tty_flip.h>
50 #include <linux/major.h>
51 #include <linux/string.h>
52 #include <linux/fcntl.h>
53 #include <linux/mm.h>
54 #include <linux/kernel.h>
55 #include <linux/delay.h>
56 #include <linux/init.h>
57 #include <linux/console.h>
58 #include <linux/slab.h>
59 #include <linux/adb.h>
60 #include <linux/pmu.h>
61 #include <linux/bitops.h>
62 #include <linux/sysrq.h>
63 #include <linux/mutex.h>
64 #include <asm/sections.h>
65 #include <asm/io.h>
66 #include <asm/irq.h>
67 #include <asm/prom.h>
68 #include <asm/machdep.h>
69 #include <asm/pmac_feature.h>
70 #include <asm/dbdma.h>
71 #include <asm/macio.h>
72
73 #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
74 #define SUPPORT_SYSRQ
75 #endif
76
77 #include <linux/serial.h>
78 #include <linux/serial_core.h>
79
80 #include "pmac_zilog.h"
81
82 /* Not yet implemented */
83 #undef HAS_DBDMA
84
85 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
86 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
87 MODULE_DESCRIPTION("Driver for the PowerMac serial ports.");
88 MODULE_LICENSE("GPL");
89
90 #define PWRDBG(fmt, arg...) printk(KERN_DEBUG fmt , ## arg)
91
92
93 /*
94 * For the sake of early serial console, we can do a pre-probe
95 * (optional) of the ports at rather early boot time.
96 */
97 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
98 static int pmz_ports_count;
99 static DEFINE_MUTEX(pmz_irq_mutex);
100
101 static struct uart_driver pmz_uart_reg = {
102 .owner = THIS_MODULE,
103 .driver_name = "ttyS",
104 .devfs_name = "tts/",
105 .dev_name = "ttyS",
106 .major = TTY_MAJOR,
107 };
108
109
110 /*
111 * Load all registers to reprogram the port
112 * This function must only be called when the TX is not busy. The UART
113 * port lock must be held and local interrupts disabled.
114 */
115 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
116 {
117 int i;
118
119 if (ZS_IS_ASLEEP(uap))
120 return;
121
122 /* Let pending transmits finish. */
123 for (i = 0; i < 1000; i++) {
124 unsigned char stat = read_zsreg(uap, R1);
125 if (stat & ALL_SNT)
126 break;
127 udelay(100);
128 }
129
130 ZS_CLEARERR(uap);
131 zssync(uap);
132 ZS_CLEARFIFO(uap);
133 zssync(uap);
134 ZS_CLEARERR(uap);
135
136 /* Disable all interrupts. */
137 write_zsreg(uap, R1,
138 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
139
140 /* Set parity, sync config, stop bits, and clock divisor. */
141 write_zsreg(uap, R4, regs[R4]);
142
143 /* Set misc. TX/RX control bits. */
144 write_zsreg(uap, R10, regs[R10]);
145
146 /* Set TX/RX controls sans the enable bits. */
147 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
148 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
149
150 /* now set R7 "prime" on ESCC */
151 write_zsreg(uap, R15, regs[R15] | EN85C30);
152 write_zsreg(uap, R7, regs[R7P]);
153
154 /* make sure we use R7 "non-prime" on ESCC */
155 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
156
157 /* Synchronous mode config. */
158 write_zsreg(uap, R6, regs[R6]);
159 write_zsreg(uap, R7, regs[R7]);
160
161 /* Disable baud generator. */
162 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
163
164 /* Clock mode control. */
165 write_zsreg(uap, R11, regs[R11]);
166
167 /* Lower and upper byte of baud rate generator divisor. */
168 write_zsreg(uap, R12, regs[R12]);
169 write_zsreg(uap, R13, regs[R13]);
170
171 /* Now rewrite R14, with BRENAB (if set). */
172 write_zsreg(uap, R14, regs[R14]);
173
174 /* Reset external status interrupts. */
175 write_zsreg(uap, R0, RES_EXT_INT);
176 write_zsreg(uap, R0, RES_EXT_INT);
177
178 /* Rewrite R3/R5, this time without enables masked. */
179 write_zsreg(uap, R3, regs[R3]);
180 write_zsreg(uap, R5, regs[R5]);
181
182 /* Rewrite R1, this time without IRQ enabled masked. */
183 write_zsreg(uap, R1, regs[R1]);
184
185 /* Enable interrupts */
186 write_zsreg(uap, R9, regs[R9]);
187 }
188
189 /*
190 * We do like sunzilog to avoid disrupting pending Tx
191 * Reprogram the Zilog channel HW registers with the copies found in the
192 * software state struct. If the transmitter is busy, we defer this update
193 * until the next TX complete interrupt. Else, we do it right now.
194 *
195 * The UART port lock must be held and local interrupts disabled.
196 */
197 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
198 {
199 if (!ZS_REGS_HELD(uap)) {
200 if (ZS_TX_ACTIVE(uap)) {
201 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
202 } else {
203 pmz_debug("pmz: maybe_update_regs: updating\n");
204 pmz_load_zsregs(uap, uap->curregs);
205 }
206 }
207 }
208
209 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap,
210 struct pt_regs *regs)
211 {
212 struct tty_struct *tty = NULL;
213 unsigned char ch, r1, drop, error, flag;
214 int loops = 0;
215
216 /* The interrupt can be enabled when the port isn't open, typically
217 * that happens when using one port is open and the other closed (stale
218 * interrupt) or when one port is used as a console.
219 */
220 if (!ZS_IS_OPEN(uap)) {
221 pmz_debug("pmz: draining input\n");
222 /* Port is closed, drain input data */
223 for (;;) {
224 if ((++loops) > 1000)
225 goto flood;
226 (void)read_zsreg(uap, R1);
227 write_zsreg(uap, R0, ERR_RES);
228 (void)read_zsdata(uap);
229 ch = read_zsreg(uap, R0);
230 if (!(ch & Rx_CH_AV))
231 break;
232 }
233 return NULL;
234 }
235
236 /* Sanity check, make sure the old bug is no longer happening */
237 if (uap->port.info == NULL || uap->port.info->tty == NULL) {
238 WARN_ON(1);
239 (void)read_zsdata(uap);
240 return NULL;
241 }
242 tty = uap->port.info->tty;
243
244 while (1) {
245 error = 0;
246 drop = 0;
247
248 r1 = read_zsreg(uap, R1);
249 ch = read_zsdata(uap);
250
251 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
252 write_zsreg(uap, R0, ERR_RES);
253 zssync(uap);
254 }
255
256 ch &= uap->parity_mask;
257 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
258 uap->flags &= ~PMACZILOG_FLAG_BREAK;
259 }
260
261 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
262 #ifdef USE_CTRL_O_SYSRQ
263 /* Handle the SysRq ^O Hack */
264 if (ch == '\x0f') {
265 uap->port.sysrq = jiffies + HZ*5;
266 goto next_char;
267 }
268 #endif /* USE_CTRL_O_SYSRQ */
269 if (uap->port.sysrq) {
270 int swallow;
271 spin_unlock(&uap->port.lock);
272 swallow = uart_handle_sysrq_char(&uap->port, ch, regs);
273 spin_lock(&uap->port.lock);
274 if (swallow)
275 goto next_char;
276 }
277 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
278
279 /* A real serial line, record the character and status. */
280 if (drop)
281 goto next_char;
282
283 flag = TTY_NORMAL;
284 uap->port.icount.rx++;
285
286 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
287 error = 1;
288 if (r1 & BRK_ABRT) {
289 pmz_debug("pmz: got break !\n");
290 r1 &= ~(PAR_ERR | CRC_ERR);
291 uap->port.icount.brk++;
292 if (uart_handle_break(&uap->port))
293 goto next_char;
294 }
295 else if (r1 & PAR_ERR)
296 uap->port.icount.parity++;
297 else if (r1 & CRC_ERR)
298 uap->port.icount.frame++;
299 if (r1 & Rx_OVR)
300 uap->port.icount.overrun++;
301 r1 &= uap->port.read_status_mask;
302 if (r1 & BRK_ABRT)
303 flag = TTY_BREAK;
304 else if (r1 & PAR_ERR)
305 flag = TTY_PARITY;
306 else if (r1 & CRC_ERR)
307 flag = TTY_FRAME;
308 }
309
310 if (uap->port.ignore_status_mask == 0xff ||
311 (r1 & uap->port.ignore_status_mask) == 0) {
312 tty_insert_flip_char(tty, ch, flag);
313 }
314 if (r1 & Rx_OVR)
315 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
316 next_char:
317 /* We can get stuck in an infinite loop getting char 0 when the
318 * line is in a wrong HW state, we break that here.
319 * When that happens, I disable the receive side of the driver.
320 * Note that what I've been experiencing is a real irq loop where
321 * I'm getting flooded regardless of the actual port speed.
322 * Something stange is going on with the HW
323 */
324 if ((++loops) > 1000)
325 goto flood;
326 ch = read_zsreg(uap, R0);
327 if (!(ch & Rx_CH_AV))
328 break;
329 }
330
331 return tty;
332 flood:
333 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
334 write_zsreg(uap, R1, uap->curregs[R1]);
335 zssync(uap);
336 dev_err(&uap->dev->ofdev.dev, "pmz: rx irq flood !\n");
337 return tty;
338 }
339
340 static void pmz_status_handle(struct uart_pmac_port *uap, struct pt_regs *regs)
341 {
342 unsigned char status;
343
344 status = read_zsreg(uap, R0);
345 write_zsreg(uap, R0, RES_EXT_INT);
346 zssync(uap);
347
348 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
349 if (status & SYNC_HUNT)
350 uap->port.icount.dsr++;
351
352 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
353 * But it does not tell us which bit has changed, we have to keep
354 * track of this ourselves.
355 * The CTS input is inverted for some reason. -- paulus
356 */
357 if ((status ^ uap->prev_status) & DCD)
358 uart_handle_dcd_change(&uap->port,
359 (status & DCD));
360 if ((status ^ uap->prev_status) & CTS)
361 uart_handle_cts_change(&uap->port,
362 !(status & CTS));
363
364 wake_up_interruptible(&uap->port.info->delta_msr_wait);
365 }
366
367 if (status & BRK_ABRT)
368 uap->flags |= PMACZILOG_FLAG_BREAK;
369
370 uap->prev_status = status;
371 }
372
373 static void pmz_transmit_chars(struct uart_pmac_port *uap)
374 {
375 struct circ_buf *xmit;
376
377 if (ZS_IS_ASLEEP(uap))
378 return;
379 if (ZS_IS_CONS(uap)) {
380 unsigned char status = read_zsreg(uap, R0);
381
382 /* TX still busy? Just wait for the next TX done interrupt.
383 *
384 * It can occur because of how we do serial console writes. It would
385 * be nice to transmit console writes just like we normally would for
386 * a TTY line. (ie. buffered and TX interrupt driven). That is not
387 * easy because console writes cannot sleep. One solution might be
388 * to poll on enough port->xmit space becomming free. -DaveM
389 */
390 if (!(status & Tx_BUF_EMP))
391 return;
392 }
393
394 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
395
396 if (ZS_REGS_HELD(uap)) {
397 pmz_load_zsregs(uap, uap->curregs);
398 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
399 }
400
401 if (ZS_TX_STOPPED(uap)) {
402 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
403 goto ack_tx_int;
404 }
405
406 if (uap->port.x_char) {
407 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
408 write_zsdata(uap, uap->port.x_char);
409 zssync(uap);
410 uap->port.icount.tx++;
411 uap->port.x_char = 0;
412 return;
413 }
414
415 if (uap->port.info == NULL)
416 goto ack_tx_int;
417 xmit = &uap->port.info->xmit;
418 if (uart_circ_empty(xmit)) {
419 uart_write_wakeup(&uap->port);
420 goto ack_tx_int;
421 }
422 if (uart_tx_stopped(&uap->port))
423 goto ack_tx_int;
424
425 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
426 write_zsdata(uap, xmit->buf[xmit->tail]);
427 zssync(uap);
428
429 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
430 uap->port.icount.tx++;
431
432 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
433 uart_write_wakeup(&uap->port);
434
435 return;
436
437 ack_tx_int:
438 write_zsreg(uap, R0, RES_Tx_P);
439 zssync(uap);
440 }
441
442 /* Hrm... we register that twice, fixme later.... */
443 static irqreturn_t pmz_interrupt(int irq, void *dev_id, struct pt_regs *regs)
444 {
445 struct uart_pmac_port *uap = dev_id;
446 struct uart_pmac_port *uap_a;
447 struct uart_pmac_port *uap_b;
448 int rc = IRQ_NONE;
449 struct tty_struct *tty;
450 u8 r3;
451
452 uap_a = pmz_get_port_A(uap);
453 uap_b = uap_a->mate;
454
455 spin_lock(&uap_a->port.lock);
456 r3 = read_zsreg(uap_a, R3);
457
458 #ifdef DEBUG_HARD
459 pmz_debug("irq, r3: %x\n", r3);
460 #endif
461 /* Channel A */
462 tty = NULL;
463 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
464 write_zsreg(uap_a, R0, RES_H_IUS);
465 zssync(uap_a);
466 if (r3 & CHAEXT)
467 pmz_status_handle(uap_a, regs);
468 if (r3 & CHARxIP)
469 tty = pmz_receive_chars(uap_a, regs);
470 if (r3 & CHATxIP)
471 pmz_transmit_chars(uap_a);
472 rc = IRQ_HANDLED;
473 }
474 spin_unlock(&uap_a->port.lock);
475 if (tty != NULL)
476 tty_flip_buffer_push(tty);
477
478 if (uap_b->node == NULL)
479 goto out;
480
481 spin_lock(&uap_b->port.lock);
482 tty = NULL;
483 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
484 write_zsreg(uap_b, R0, RES_H_IUS);
485 zssync(uap_b);
486 if (r3 & CHBEXT)
487 pmz_status_handle(uap_b, regs);
488 if (r3 & CHBRxIP)
489 tty = pmz_receive_chars(uap_b, regs);
490 if (r3 & CHBTxIP)
491 pmz_transmit_chars(uap_b);
492 rc = IRQ_HANDLED;
493 }
494 spin_unlock(&uap_b->port.lock);
495 if (tty != NULL)
496 tty_flip_buffer_push(tty);
497
498 out:
499 #ifdef DEBUG_HARD
500 pmz_debug("irq done.\n");
501 #endif
502 return rc;
503 }
504
505 /*
506 * Peek the status register, lock not held by caller
507 */
508 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
509 {
510 unsigned long flags;
511 u8 status;
512
513 spin_lock_irqsave(&uap->port.lock, flags);
514 status = read_zsreg(uap, R0);
515 spin_unlock_irqrestore(&uap->port.lock, flags);
516
517 return status;
518 }
519
520 /*
521 * Check if transmitter is empty
522 * The port lock is not held.
523 */
524 static unsigned int pmz_tx_empty(struct uart_port *port)
525 {
526 struct uart_pmac_port *uap = to_pmz(port);
527 unsigned char status;
528
529 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
530 return TIOCSER_TEMT;
531
532 status = pmz_peek_status(to_pmz(port));
533 if (status & Tx_BUF_EMP)
534 return TIOCSER_TEMT;
535 return 0;
536 }
537
538 /*
539 * Set Modem Control (RTS & DTR) bits
540 * The port lock is held and interrupts are disabled.
541 * Note: Shall we really filter out RTS on external ports or
542 * should that be dealt at higher level only ?
543 */
544 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
545 {
546 struct uart_pmac_port *uap = to_pmz(port);
547 unsigned char set_bits, clear_bits;
548
549 /* Do nothing for irda for now... */
550 if (ZS_IS_IRDA(uap))
551 return;
552 /* We get called during boot with a port not up yet */
553 if (ZS_IS_ASLEEP(uap) ||
554 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
555 return;
556
557 set_bits = clear_bits = 0;
558
559 if (ZS_IS_INTMODEM(uap)) {
560 if (mctrl & TIOCM_RTS)
561 set_bits |= RTS;
562 else
563 clear_bits |= RTS;
564 }
565 if (mctrl & TIOCM_DTR)
566 set_bits |= DTR;
567 else
568 clear_bits |= DTR;
569
570 /* NOTE: Not subject to 'transmitter active' rule. */
571 uap->curregs[R5] |= set_bits;
572 uap->curregs[R5] &= ~clear_bits;
573 if (ZS_IS_ASLEEP(uap))
574 return;
575 write_zsreg(uap, R5, uap->curregs[R5]);
576 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
577 set_bits, clear_bits, uap->curregs[R5]);
578 zssync(uap);
579 }
580
581 /*
582 * Get Modem Control bits (only the input ones, the core will
583 * or that with a cached value of the control ones)
584 * The port lock is held and interrupts are disabled.
585 */
586 static unsigned int pmz_get_mctrl(struct uart_port *port)
587 {
588 struct uart_pmac_port *uap = to_pmz(port);
589 unsigned char status;
590 unsigned int ret;
591
592 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
593 return 0;
594
595 status = read_zsreg(uap, R0);
596
597 ret = 0;
598 if (status & DCD)
599 ret |= TIOCM_CAR;
600 if (status & SYNC_HUNT)
601 ret |= TIOCM_DSR;
602 if (!(status & CTS))
603 ret |= TIOCM_CTS;
604
605 return ret;
606 }
607
608 /*
609 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
610 * though for DMA, we will have to do a bit more.
611 * The port lock is held and interrupts are disabled.
612 */
613 static void pmz_stop_tx(struct uart_port *port)
614 {
615 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
616 }
617
618 /*
619 * Kick the Tx side.
620 * The port lock is held and interrupts are disabled.
621 */
622 static void pmz_start_tx(struct uart_port *port)
623 {
624 struct uart_pmac_port *uap = to_pmz(port);
625 unsigned char status;
626
627 pmz_debug("pmz: start_tx()\n");
628
629 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
630 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
631
632 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
633 return;
634
635 status = read_zsreg(uap, R0);
636
637 /* TX busy? Just wait for the TX done interrupt. */
638 if (!(status & Tx_BUF_EMP))
639 return;
640
641 /* Send the first character to jump-start the TX done
642 * IRQ sending engine.
643 */
644 if (port->x_char) {
645 write_zsdata(uap, port->x_char);
646 zssync(uap);
647 port->icount.tx++;
648 port->x_char = 0;
649 } else {
650 struct circ_buf *xmit = &port->info->xmit;
651
652 write_zsdata(uap, xmit->buf[xmit->tail]);
653 zssync(uap);
654 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
655 port->icount.tx++;
656
657 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
658 uart_write_wakeup(&uap->port);
659 }
660 pmz_debug("pmz: start_tx() done.\n");
661 }
662
663 /*
664 * Stop Rx side, basically disable emitting of
665 * Rx interrupts on the port. We don't disable the rx
666 * side of the chip proper though
667 * The port lock is held.
668 */
669 static void pmz_stop_rx(struct uart_port *port)
670 {
671 struct uart_pmac_port *uap = to_pmz(port);
672
673 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
674 return;
675
676 pmz_debug("pmz: stop_rx()()\n");
677
678 /* Disable all RX interrupts. */
679 uap->curregs[R1] &= ~RxINT_MASK;
680 pmz_maybe_update_regs(uap);
681
682 pmz_debug("pmz: stop_rx() done.\n");
683 }
684
685 /*
686 * Enable modem status change interrupts
687 * The port lock is held.
688 */
689 static void pmz_enable_ms(struct uart_port *port)
690 {
691 struct uart_pmac_port *uap = to_pmz(port);
692 unsigned char new_reg;
693
694 if (ZS_IS_IRDA(uap) || uap->node == NULL)
695 return;
696 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
697 if (new_reg != uap->curregs[R15]) {
698 uap->curregs[R15] = new_reg;
699
700 if (ZS_IS_ASLEEP(uap))
701 return;
702 /* NOTE: Not subject to 'transmitter active' rule. */
703 write_zsreg(uap, R15, uap->curregs[R15]);
704 }
705 }
706
707 /*
708 * Control break state emission
709 * The port lock is not held.
710 */
711 static void pmz_break_ctl(struct uart_port *port, int break_state)
712 {
713 struct uart_pmac_port *uap = to_pmz(port);
714 unsigned char set_bits, clear_bits, new_reg;
715 unsigned long flags;
716
717 if (uap->node == NULL)
718 return;
719 set_bits = clear_bits = 0;
720
721 if (break_state)
722 set_bits |= SND_BRK;
723 else
724 clear_bits |= SND_BRK;
725
726 spin_lock_irqsave(&port->lock, flags);
727
728 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
729 if (new_reg != uap->curregs[R5]) {
730 uap->curregs[R5] = new_reg;
731
732 /* NOTE: Not subject to 'transmitter active' rule. */
733 if (ZS_IS_ASLEEP(uap))
734 return;
735 write_zsreg(uap, R5, uap->curregs[R5]);
736 }
737
738 spin_unlock_irqrestore(&port->lock, flags);
739 }
740
741 /*
742 * Turn power on or off to the SCC and associated stuff
743 * (port drivers, modem, IR port, etc.)
744 * Returns the number of milliseconds we should wait before
745 * trying to use the port.
746 */
747 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
748 {
749 int delay = 0;
750 int rc;
751
752 if (state) {
753 rc = pmac_call_feature(
754 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
755 pmz_debug("port power on result: %d\n", rc);
756 if (ZS_IS_INTMODEM(uap)) {
757 rc = pmac_call_feature(
758 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
759 delay = 2500; /* wait for 2.5s before using */
760 pmz_debug("modem power result: %d\n", rc);
761 }
762 } else {
763 /* TODO: Make that depend on a timer, don't power down
764 * immediately
765 */
766 if (ZS_IS_INTMODEM(uap)) {
767 rc = pmac_call_feature(
768 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
769 pmz_debug("port power off result: %d\n", rc);
770 }
771 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
772 }
773 return delay;
774 }
775
776 /*
777 * FixZeroBug....Works around a bug in the SCC receving channel.
778 * Inspired from Darwin code, 15 Sept. 2000 -DanM
779 *
780 * The following sequence prevents a problem that is seen with O'Hare ASICs
781 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
782 * at the input to the receiver becomes 'stuck' and locks up the receiver.
783 * This problem can occur as a result of a zero bit at the receiver input
784 * coincident with any of the following events:
785 *
786 * The SCC is initialized (hardware or software).
787 * A framing error is detected.
788 * The clocking option changes from synchronous or X1 asynchronous
789 * clocking to X16, X32, or X64 asynchronous clocking.
790 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
791 *
792 * This workaround attempts to recover from the lockup condition by placing
793 * the SCC in synchronous loopback mode with a fast clock before programming
794 * any of the asynchronous modes.
795 */
796 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
797 {
798 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
799 zssync(uap);
800 udelay(10);
801 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
802 zssync(uap);
803
804 write_zsreg(uap, 4, X1CLK | MONSYNC);
805 write_zsreg(uap, 3, Rx8);
806 write_zsreg(uap, 5, Tx8 | RTS);
807 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
808 write_zsreg(uap, 11, RCBR | TCBR);
809 write_zsreg(uap, 12, 0);
810 write_zsreg(uap, 13, 0);
811 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
812 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
813 write_zsreg(uap, 3, Rx8 | RxENABLE);
814 write_zsreg(uap, 0, RES_EXT_INT);
815 write_zsreg(uap, 0, RES_EXT_INT);
816 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
817
818 /* The channel should be OK now, but it is probably receiving
819 * loopback garbage.
820 * Switch to asynchronous mode, disable the receiver,
821 * and discard everything in the receive buffer.
822 */
823 write_zsreg(uap, 9, NV);
824 write_zsreg(uap, 4, X16CLK | SB_MASK);
825 write_zsreg(uap, 3, Rx8);
826
827 while (read_zsreg(uap, 0) & Rx_CH_AV) {
828 (void)read_zsreg(uap, 8);
829 write_zsreg(uap, 0, RES_EXT_INT);
830 write_zsreg(uap, 0, ERR_RES);
831 }
832 }
833
834 /*
835 * Real startup routine, powers up the hardware and sets up
836 * the SCC. Returns a delay in ms where you need to wait before
837 * actually using the port, this is typically the internal modem
838 * powerup delay. This routine expect the lock to be taken.
839 */
840 static int __pmz_startup(struct uart_pmac_port *uap)
841 {
842 int pwr_delay = 0;
843
844 memset(&uap->curregs, 0, sizeof(uap->curregs));
845
846 /* Power up the SCC & underlying hardware (modem/irda) */
847 pwr_delay = pmz_set_scc_power(uap, 1);
848
849 /* Nice buggy HW ... */
850 pmz_fix_zero_bug_scc(uap);
851
852 /* Reset the channel */
853 uap->curregs[R9] = 0;
854 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
855 zssync(uap);
856 udelay(10);
857 write_zsreg(uap, 9, 0);
858 zssync(uap);
859
860 /* Clear the interrupt registers */
861 write_zsreg(uap, R1, 0);
862 write_zsreg(uap, R0, ERR_RES);
863 write_zsreg(uap, R0, ERR_RES);
864 write_zsreg(uap, R0, RES_H_IUS);
865 write_zsreg(uap, R0, RES_H_IUS);
866
867 /* Setup some valid baud rate */
868 uap->curregs[R4] = X16CLK | SB1;
869 uap->curregs[R3] = Rx8;
870 uap->curregs[R5] = Tx8 | RTS;
871 if (!ZS_IS_IRDA(uap))
872 uap->curregs[R5] |= DTR;
873 uap->curregs[R12] = 0;
874 uap->curregs[R13] = 0;
875 uap->curregs[R14] = BRENAB;
876
877 /* Clear handshaking, enable BREAK interrupts */
878 uap->curregs[R15] = BRKIE;
879
880 /* Master interrupt enable */
881 uap->curregs[R9] |= NV | MIE;
882
883 pmz_load_zsregs(uap, uap->curregs);
884
885 /* Enable receiver and transmitter. */
886 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
887 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
888
889 /* Remember status for DCD/CTS changes */
890 uap->prev_status = read_zsreg(uap, R0);
891
892
893 return pwr_delay;
894 }
895
896 static void pmz_irda_reset(struct uart_pmac_port *uap)
897 {
898 uap->curregs[R5] |= DTR;
899 write_zsreg(uap, R5, uap->curregs[R5]);
900 zssync(uap);
901 mdelay(110);
902 uap->curregs[R5] &= ~DTR;
903 write_zsreg(uap, R5, uap->curregs[R5]);
904 zssync(uap);
905 mdelay(10);
906 }
907
908 /*
909 * This is the "normal" startup routine, using the above one
910 * wrapped with the lock and doing a schedule delay
911 */
912 static int pmz_startup(struct uart_port *port)
913 {
914 struct uart_pmac_port *uap = to_pmz(port);
915 unsigned long flags;
916 int pwr_delay = 0;
917
918 pmz_debug("pmz: startup()\n");
919
920 if (ZS_IS_ASLEEP(uap))
921 return -EAGAIN;
922 if (uap->node == NULL)
923 return -ENODEV;
924
925 mutex_lock(&pmz_irq_mutex);
926
927 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
928
929 /* A console is never powered down. Else, power up and
930 * initialize the chip
931 */
932 if (!ZS_IS_CONS(uap)) {
933 spin_lock_irqsave(&port->lock, flags);
934 pwr_delay = __pmz_startup(uap);
935 spin_unlock_irqrestore(&port->lock, flags);
936 }
937
938 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
939 if (request_irq(uap->port.irq, pmz_interrupt, SA_SHIRQ, "PowerMac Zilog", uap)) {
940 dev_err(&uap->dev->ofdev.dev,
941 "Unable to register zs interrupt handler.\n");
942 pmz_set_scc_power(uap, 0);
943 mutex_unlock(&pmz_irq_mutex);
944 return -ENXIO;
945 }
946
947 mutex_unlock(&pmz_irq_mutex);
948
949 /* Right now, we deal with delay by blocking here, I'll be
950 * smarter later on
951 */
952 if (pwr_delay != 0) {
953 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
954 msleep(pwr_delay);
955 }
956
957 /* IrDA reset is done now */
958 if (ZS_IS_IRDA(uap))
959 pmz_irda_reset(uap);
960
961 /* Enable interrupts emission from the chip */
962 spin_lock_irqsave(&port->lock, flags);
963 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
964 if (!ZS_IS_EXTCLK(uap))
965 uap->curregs[R1] |= EXT_INT_ENAB;
966 write_zsreg(uap, R1, uap->curregs[R1]);
967 spin_unlock_irqrestore(&port->lock, flags);
968
969 pmz_debug("pmz: startup() done.\n");
970
971 return 0;
972 }
973
974 static void pmz_shutdown(struct uart_port *port)
975 {
976 struct uart_pmac_port *uap = to_pmz(port);
977 unsigned long flags;
978
979 pmz_debug("pmz: shutdown()\n");
980
981 if (uap->node == NULL)
982 return;
983
984 mutex_lock(&pmz_irq_mutex);
985
986 /* Release interrupt handler */
987 free_irq(uap->port.irq, uap);
988
989 spin_lock_irqsave(&port->lock, flags);
990
991 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
992
993 if (!ZS_IS_OPEN(uap->mate))
994 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
995
996 /* Disable interrupts */
997 if (!ZS_IS_ASLEEP(uap)) {
998 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
999 write_zsreg(uap, R1, uap->curregs[R1]);
1000 zssync(uap);
1001 }
1002
1003 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1004 spin_unlock_irqrestore(&port->lock, flags);
1005 mutex_unlock(&pmz_irq_mutex);
1006 return;
1007 }
1008
1009 /* Disable receiver and transmitter. */
1010 uap->curregs[R3] &= ~RxENABLE;
1011 uap->curregs[R5] &= ~TxENABLE;
1012
1013 /* Disable all interrupts and BRK assertion. */
1014 uap->curregs[R5] &= ~SND_BRK;
1015 pmz_maybe_update_regs(uap);
1016
1017 /* Shut the chip down */
1018 pmz_set_scc_power(uap, 0);
1019
1020 spin_unlock_irqrestore(&port->lock, flags);
1021
1022 mutex_unlock(&pmz_irq_mutex);
1023
1024 pmz_debug("pmz: shutdown() done.\n");
1025 }
1026
1027 /* Shared by TTY driver and serial console setup. The port lock is held
1028 * and local interrupts are disabled.
1029 */
1030 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1031 unsigned int iflag, unsigned long baud)
1032 {
1033 int brg;
1034
1035
1036 /* Switch to external clocking for IrDA high clock rates. That
1037 * code could be re-used for Midi interfaces with different
1038 * multipliers
1039 */
1040 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1041 uap->curregs[R4] = X1CLK;
1042 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1043 uap->curregs[R14] = 0; /* BRG off */
1044 uap->curregs[R12] = 0;
1045 uap->curregs[R13] = 0;
1046 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1047 } else {
1048 switch (baud) {
1049 case ZS_CLOCK/16: /* 230400 */
1050 uap->curregs[R4] = X16CLK;
1051 uap->curregs[R11] = 0;
1052 uap->curregs[R14] = 0;
1053 break;
1054 case ZS_CLOCK/32: /* 115200 */
1055 uap->curregs[R4] = X32CLK;
1056 uap->curregs[R11] = 0;
1057 uap->curregs[R14] = 0;
1058 break;
1059 default:
1060 uap->curregs[R4] = X16CLK;
1061 uap->curregs[R11] = TCBR | RCBR;
1062 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1063 uap->curregs[R12] = (brg & 255);
1064 uap->curregs[R13] = ((brg >> 8) & 255);
1065 uap->curregs[R14] = BRENAB;
1066 }
1067 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1068 }
1069
1070 /* Character size, stop bits, and parity. */
1071 uap->curregs[3] &= ~RxN_MASK;
1072 uap->curregs[5] &= ~TxN_MASK;
1073
1074 switch (cflag & CSIZE) {
1075 case CS5:
1076 uap->curregs[3] |= Rx5;
1077 uap->curregs[5] |= Tx5;
1078 uap->parity_mask = 0x1f;
1079 break;
1080 case CS6:
1081 uap->curregs[3] |= Rx6;
1082 uap->curregs[5] |= Tx6;
1083 uap->parity_mask = 0x3f;
1084 break;
1085 case CS7:
1086 uap->curregs[3] |= Rx7;
1087 uap->curregs[5] |= Tx7;
1088 uap->parity_mask = 0x7f;
1089 break;
1090 case CS8:
1091 default:
1092 uap->curregs[3] |= Rx8;
1093 uap->curregs[5] |= Tx8;
1094 uap->parity_mask = 0xff;
1095 break;
1096 };
1097 uap->curregs[4] &= ~(SB_MASK);
1098 if (cflag & CSTOPB)
1099 uap->curregs[4] |= SB2;
1100 else
1101 uap->curregs[4] |= SB1;
1102 if (cflag & PARENB)
1103 uap->curregs[4] |= PAR_ENAB;
1104 else
1105 uap->curregs[4] &= ~PAR_ENAB;
1106 if (!(cflag & PARODD))
1107 uap->curregs[4] |= PAR_EVEN;
1108 else
1109 uap->curregs[4] &= ~PAR_EVEN;
1110
1111 uap->port.read_status_mask = Rx_OVR;
1112 if (iflag & INPCK)
1113 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1114 if (iflag & (BRKINT | PARMRK))
1115 uap->port.read_status_mask |= BRK_ABRT;
1116
1117 uap->port.ignore_status_mask = 0;
1118 if (iflag & IGNPAR)
1119 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1120 if (iflag & IGNBRK) {
1121 uap->port.ignore_status_mask |= BRK_ABRT;
1122 if (iflag & IGNPAR)
1123 uap->port.ignore_status_mask |= Rx_OVR;
1124 }
1125
1126 if ((cflag & CREAD) == 0)
1127 uap->port.ignore_status_mask = 0xff;
1128 }
1129
1130
1131 /*
1132 * Set the irda codec on the imac to the specified baud rate.
1133 */
1134 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1135 {
1136 u8 cmdbyte;
1137 int t, version;
1138
1139 switch (*baud) {
1140 /* SIR modes */
1141 case 2400:
1142 cmdbyte = 0x53;
1143 break;
1144 case 4800:
1145 cmdbyte = 0x52;
1146 break;
1147 case 9600:
1148 cmdbyte = 0x51;
1149 break;
1150 case 19200:
1151 cmdbyte = 0x50;
1152 break;
1153 case 38400:
1154 cmdbyte = 0x4f;
1155 break;
1156 case 57600:
1157 cmdbyte = 0x4e;
1158 break;
1159 case 115200:
1160 cmdbyte = 0x4d;
1161 break;
1162 /* The FIR modes aren't really supported at this point, how
1163 * do we select the speed ? via the FCR on KeyLargo ?
1164 */
1165 case 1152000:
1166 cmdbyte = 0;
1167 break;
1168 case 4000000:
1169 cmdbyte = 0;
1170 break;
1171 default: /* 9600 */
1172 cmdbyte = 0x51;
1173 *baud = 9600;
1174 break;
1175 }
1176
1177 /* Wait for transmitter to drain */
1178 t = 10000;
1179 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1180 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1181 if (--t <= 0) {
1182 dev_err(&uap->dev->ofdev.dev, "transmitter didn't drain\n");
1183 return;
1184 }
1185 udelay(10);
1186 }
1187
1188 /* Drain the receiver too */
1189 t = 100;
1190 (void)read_zsdata(uap);
1191 (void)read_zsdata(uap);
1192 (void)read_zsdata(uap);
1193 mdelay(10);
1194 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1195 read_zsdata(uap);
1196 mdelay(10);
1197 if (--t <= 0) {
1198 dev_err(&uap->dev->ofdev.dev, "receiver didn't drain\n");
1199 return;
1200 }
1201 }
1202
1203 /* Switch to command mode */
1204 uap->curregs[R5] |= DTR;
1205 write_zsreg(uap, R5, uap->curregs[R5]);
1206 zssync(uap);
1207 mdelay(1);
1208
1209 /* Switch SCC to 19200 */
1210 pmz_convert_to_zs(uap, CS8, 0, 19200);
1211 pmz_load_zsregs(uap, uap->curregs);
1212 mdelay(1);
1213
1214 /* Write get_version command byte */
1215 write_zsdata(uap, 1);
1216 t = 5000;
1217 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1218 if (--t <= 0) {
1219 dev_err(&uap->dev->ofdev.dev,
1220 "irda_setup timed out on get_version byte\n");
1221 goto out;
1222 }
1223 udelay(10);
1224 }
1225 version = read_zsdata(uap);
1226
1227 if (version < 4) {
1228 dev_info(&uap->dev->ofdev.dev, "IrDA: dongle version %d not supported\n",
1229 version);
1230 goto out;
1231 }
1232
1233 /* Send speed mode */
1234 write_zsdata(uap, cmdbyte);
1235 t = 5000;
1236 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1237 if (--t <= 0) {
1238 dev_err(&uap->dev->ofdev.dev,
1239 "irda_setup timed out on speed mode byte\n");
1240 goto out;
1241 }
1242 udelay(10);
1243 }
1244 t = read_zsdata(uap);
1245 if (t != cmdbyte)
1246 dev_err(&uap->dev->ofdev.dev,
1247 "irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1248
1249 dev_info(&uap->dev->ofdev.dev, "IrDA setup for %ld bps, dongle version: %d\n",
1250 *baud, version);
1251
1252 (void)read_zsdata(uap);
1253 (void)read_zsdata(uap);
1254 (void)read_zsdata(uap);
1255
1256 out:
1257 /* Switch back to data mode */
1258 uap->curregs[R5] &= ~DTR;
1259 write_zsreg(uap, R5, uap->curregs[R5]);
1260 zssync(uap);
1261
1262 (void)read_zsdata(uap);
1263 (void)read_zsdata(uap);
1264 (void)read_zsdata(uap);
1265 }
1266
1267
1268 static void __pmz_set_termios(struct uart_port *port, struct termios *termios,
1269 struct termios *old)
1270 {
1271 struct uart_pmac_port *uap = to_pmz(port);
1272 unsigned long baud;
1273
1274 pmz_debug("pmz: set_termios()\n");
1275
1276 if (ZS_IS_ASLEEP(uap))
1277 return;
1278
1279 memcpy(&uap->termios_cache, termios, sizeof(struct termios));
1280
1281 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1282 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1283 * about the FIR mode and high speed modes. So these are unused. For
1284 * implementing proper support for these, we should probably add some
1285 * DMA as well, at least on the Rx side, which isn't a simple thing
1286 * at this point.
1287 */
1288 if (ZS_IS_IRDA(uap)) {
1289 /* Calc baud rate */
1290 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1291 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1292 /* Cet the irda codec to the right rate */
1293 pmz_irda_setup(uap, &baud);
1294 /* Set final baud rate */
1295 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1296 pmz_load_zsregs(uap, uap->curregs);
1297 zssync(uap);
1298 } else {
1299 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1300 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1301 /* Make sure modem status interrupts are correctly configured */
1302 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1303 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1304 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1305 } else {
1306 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1307 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1308 }
1309
1310 /* Load registers to the chip */
1311 pmz_maybe_update_regs(uap);
1312 }
1313 uart_update_timeout(port, termios->c_cflag, baud);
1314
1315 pmz_debug("pmz: set_termios() done.\n");
1316 }
1317
1318 /* The port lock is not held. */
1319 static void pmz_set_termios(struct uart_port *port, struct termios *termios,
1320 struct termios *old)
1321 {
1322 struct uart_pmac_port *uap = to_pmz(port);
1323 unsigned long flags;
1324
1325 spin_lock_irqsave(&port->lock, flags);
1326
1327 /* Disable IRQs on the port */
1328 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1329 write_zsreg(uap, R1, uap->curregs[R1]);
1330
1331 /* Setup new port configuration */
1332 __pmz_set_termios(port, termios, old);
1333
1334 /* Re-enable IRQs on the port */
1335 if (ZS_IS_OPEN(uap)) {
1336 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1337 if (!ZS_IS_EXTCLK(uap))
1338 uap->curregs[R1] |= EXT_INT_ENAB;
1339 write_zsreg(uap, R1, uap->curregs[R1]);
1340 }
1341 spin_unlock_irqrestore(&port->lock, flags);
1342 }
1343
1344 static const char *pmz_type(struct uart_port *port)
1345 {
1346 struct uart_pmac_port *uap = to_pmz(port);
1347
1348 if (ZS_IS_IRDA(uap))
1349 return "Z85c30 ESCC - Infrared port";
1350 else if (ZS_IS_INTMODEM(uap))
1351 return "Z85c30 ESCC - Internal modem";
1352 return "Z85c30 ESCC - Serial port";
1353 }
1354
1355 /* We do not request/release mappings of the registers here, this
1356 * happens at early serial probe time.
1357 */
1358 static void pmz_release_port(struct uart_port *port)
1359 {
1360 }
1361
1362 static int pmz_request_port(struct uart_port *port)
1363 {
1364 return 0;
1365 }
1366
1367 /* These do not need to do anything interesting either. */
1368 static void pmz_config_port(struct uart_port *port, int flags)
1369 {
1370 }
1371
1372 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1373 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1374 {
1375 return -EINVAL;
1376 }
1377
1378 static struct uart_ops pmz_pops = {
1379 .tx_empty = pmz_tx_empty,
1380 .set_mctrl = pmz_set_mctrl,
1381 .get_mctrl = pmz_get_mctrl,
1382 .stop_tx = pmz_stop_tx,
1383 .start_tx = pmz_start_tx,
1384 .stop_rx = pmz_stop_rx,
1385 .enable_ms = pmz_enable_ms,
1386 .break_ctl = pmz_break_ctl,
1387 .startup = pmz_startup,
1388 .shutdown = pmz_shutdown,
1389 .set_termios = pmz_set_termios,
1390 .type = pmz_type,
1391 .release_port = pmz_release_port,
1392 .request_port = pmz_request_port,
1393 .config_port = pmz_config_port,
1394 .verify_port = pmz_verify_port,
1395 };
1396
1397 /*
1398 * Setup one port structure after probing, HW is down at this point,
1399 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1400 * register our console before uart_add_one_port() is called
1401 */
1402 static int __init pmz_init_port(struct uart_pmac_port *uap)
1403 {
1404 struct device_node *np = uap->node;
1405 char *conn;
1406 struct slot_names_prop {
1407 int count;
1408 char name[1];
1409 } *slots;
1410 int len;
1411 struct resource r_ports, r_rxdma, r_txdma;
1412
1413 /*
1414 * Request & map chip registers
1415 */
1416 if (of_address_to_resource(np, 0, &r_ports))
1417 return -ENODEV;
1418 uap->port.mapbase = r_ports.start;
1419 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1420
1421 uap->control_reg = uap->port.membase;
1422 uap->data_reg = uap->control_reg + 0x10;
1423
1424 /*
1425 * Request & map DBDMA registers
1426 */
1427 #ifdef HAS_DBDMA
1428 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1429 of_address_to_resource(np, 2, &r_rxdma) == 0)
1430 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1431 #else
1432 memset(&r_txdma, 0, sizeof(struct resource));
1433 memset(&r_rxdma, 0, sizeof(struct resource));
1434 #endif
1435 if (ZS_HAS_DMA(uap)) {
1436 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1437 if (uap->tx_dma_regs == NULL) {
1438 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1439 goto no_dma;
1440 }
1441 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1442 if (uap->rx_dma_regs == NULL) {
1443 iounmap(uap->tx_dma_regs);
1444 uap->tx_dma_regs = NULL;
1445 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1446 goto no_dma;
1447 }
1448 uap->tx_dma_irq = np->intrs[1].line;
1449 uap->rx_dma_irq = np->intrs[2].line;
1450 }
1451 no_dma:
1452
1453 /*
1454 * Detect port type
1455 */
1456 if (device_is_compatible(np, "cobalt"))
1457 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1458 conn = get_property(np, "AAPL,connector", &len);
1459 if (conn && (strcmp(conn, "infrared") == 0))
1460 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1461 uap->port_type = PMAC_SCC_ASYNC;
1462 /* 1999 Powerbook G3 has slot-names property instead */
1463 slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
1464 if (slots && slots->count > 0) {
1465 if (strcmp(slots->name, "IrDA") == 0)
1466 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1467 else if (strcmp(slots->name, "Modem") == 0)
1468 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1469 }
1470 if (ZS_IS_IRDA(uap))
1471 uap->port_type = PMAC_SCC_IRDA;
1472 if (ZS_IS_INTMODEM(uap)) {
1473 struct device_node* i2c_modem = find_devices("i2c-modem");
1474 if (i2c_modem) {
1475 char* mid = get_property(i2c_modem, "modem-id", NULL);
1476 if (mid) switch(*mid) {
1477 case 0x04 :
1478 case 0x05 :
1479 case 0x07 :
1480 case 0x08 :
1481 case 0x0b :
1482 case 0x0c :
1483 uap->port_type = PMAC_SCC_I2S1;
1484 }
1485 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1486 mid ? (*mid) : 0);
1487 } else {
1488 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1489 }
1490 }
1491
1492 /*
1493 * Init remaining bits of "port" structure
1494 */
1495 uap->port.iotype = UPIO_MEM;
1496 uap->port.irq = np->intrs[0].line;
1497 uap->port.uartclk = ZS_CLOCK;
1498 uap->port.fifosize = 1;
1499 uap->port.ops = &pmz_pops;
1500 uap->port.type = PORT_PMAC_ZILOG;
1501 uap->port.flags = 0;
1502
1503 /* Setup some valid baud rate information in the register
1504 * shadows so we don't write crap there before baud rate is
1505 * first initialized.
1506 */
1507 pmz_convert_to_zs(uap, CS8, 0, 9600);
1508
1509 return 0;
1510 }
1511
1512 /*
1513 * Get rid of a port on module removal
1514 */
1515 static void pmz_dispose_port(struct uart_pmac_port *uap)
1516 {
1517 struct device_node *np;
1518
1519 np = uap->node;
1520 iounmap(uap->rx_dma_regs);
1521 iounmap(uap->tx_dma_regs);
1522 iounmap(uap->control_reg);
1523 uap->node = NULL;
1524 of_node_put(np);
1525 memset(uap, 0, sizeof(struct uart_pmac_port));
1526 }
1527
1528 /*
1529 * Called upon match with an escc node in the devive-tree.
1530 */
1531 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1532 {
1533 int i;
1534
1535 /* Iterate the pmz_ports array to find a matching entry
1536 */
1537 for (i = 0; i < MAX_ZS_PORTS; i++)
1538 if (pmz_ports[i].node == mdev->ofdev.node) {
1539 struct uart_pmac_port *uap = &pmz_ports[i];
1540
1541 uap->dev = mdev;
1542 dev_set_drvdata(&mdev->ofdev.dev, uap);
1543 if (macio_request_resources(uap->dev, "pmac_zilog"))
1544 printk(KERN_WARNING "%s: Failed to request resource"
1545 ", port still active\n",
1546 uap->node->name);
1547 else
1548 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1549 return 0;
1550 }
1551 return -ENODEV;
1552 }
1553
1554 /*
1555 * That one should not be called, macio isn't really a hotswap device,
1556 * we don't expect one of those serial ports to go away...
1557 */
1558 static int pmz_detach(struct macio_dev *mdev)
1559 {
1560 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1561
1562 if (!uap)
1563 return -ENODEV;
1564
1565 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1566 macio_release_resources(uap->dev);
1567 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1568 }
1569 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1570 uap->dev = NULL;
1571
1572 return 0;
1573 }
1574
1575
1576 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1577 {
1578 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1579 struct uart_state *state;
1580 unsigned long flags;
1581
1582 if (uap == NULL) {
1583 printk("HRM... pmz_suspend with NULL uap\n");
1584 return 0;
1585 }
1586
1587 if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
1588 return 0;
1589
1590 pmz_debug("suspend, switching to state %d\n", pm_state);
1591
1592 state = pmz_uart_reg.state + uap->port.line;
1593
1594 mutex_lock(&pmz_irq_mutex);
1595 mutex_lock(&state->mutex);
1596
1597 spin_lock_irqsave(&uap->port.lock, flags);
1598
1599 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1600 /* Disable receiver and transmitter. */
1601 uap->curregs[R3] &= ~RxENABLE;
1602 uap->curregs[R5] &= ~TxENABLE;
1603
1604 /* Disable all interrupts and BRK assertion. */
1605 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1606 uap->curregs[R5] &= ~SND_BRK;
1607 pmz_load_zsregs(uap, uap->curregs);
1608 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1609 mb();
1610 }
1611
1612 spin_unlock_irqrestore(&uap->port.lock, flags);
1613
1614 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1615 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1616 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1617 disable_irq(uap->port.irq);
1618 }
1619
1620 if (ZS_IS_CONS(uap))
1621 uap->port.cons->flags &= ~CON_ENABLED;
1622
1623 /* Shut the chip down */
1624 pmz_set_scc_power(uap, 0);
1625
1626 mutex_unlock(&state->mutex);
1627 mutex_unlock(&pmz_irq_mutex);
1628
1629 pmz_debug("suspend, switching complete\n");
1630
1631 mdev->ofdev.dev.power.power_state = pm_state;
1632
1633 return 0;
1634 }
1635
1636
1637 static int pmz_resume(struct macio_dev *mdev)
1638 {
1639 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1640 struct uart_state *state;
1641 unsigned long flags;
1642 int pwr_delay = 0;
1643
1644 if (uap == NULL)
1645 return 0;
1646
1647 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
1648 return 0;
1649
1650 pmz_debug("resume, switching to state 0\n");
1651
1652 state = pmz_uart_reg.state + uap->port.line;
1653
1654 mutex_lock(&pmz_irq_mutex);
1655 mutex_lock(&state->mutex);
1656
1657 spin_lock_irqsave(&uap->port.lock, flags);
1658 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1659 spin_unlock_irqrestore(&uap->port.lock, flags);
1660 goto bail;
1661 }
1662 pwr_delay = __pmz_startup(uap);
1663
1664 /* Take care of config that may have changed while asleep */
1665 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1666
1667 if (ZS_IS_OPEN(uap)) {
1668 /* Enable interrupts */
1669 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1670 if (!ZS_IS_EXTCLK(uap))
1671 uap->curregs[R1] |= EXT_INT_ENAB;
1672 write_zsreg(uap, R1, uap->curregs[R1]);
1673 }
1674
1675 spin_unlock_irqrestore(&uap->port.lock, flags);
1676
1677 if (ZS_IS_CONS(uap))
1678 uap->port.cons->flags |= CON_ENABLED;
1679
1680 /* Re-enable IRQ on the controller */
1681 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1682 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1683 enable_irq(uap->port.irq);
1684 }
1685
1686 bail:
1687 mutex_unlock(&state->mutex);
1688 mutex_unlock(&pmz_irq_mutex);
1689
1690 /* Right now, we deal with delay by blocking here, I'll be
1691 * smarter later on
1692 */
1693 if (pwr_delay != 0) {
1694 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1695 msleep(pwr_delay);
1696 }
1697
1698 pmz_debug("resume, switching complete\n");
1699
1700 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1701
1702 return 0;
1703 }
1704
1705 /*
1706 * Probe all ports in the system and build the ports array, we register
1707 * with the serial layer at this point, the macio-type probing is only
1708 * used later to "attach" to the sysfs tree so we get power management
1709 * events
1710 */
1711 static int __init pmz_probe(void)
1712 {
1713 struct device_node *node_p, *node_a, *node_b, *np;
1714 int count = 0;
1715 int rc;
1716
1717 /*
1718 * Find all escc chips in the system
1719 */
1720 node_p = of_find_node_by_name(NULL, "escc");
1721 while (node_p) {
1722 /*
1723 * First get channel A/B node pointers
1724 *
1725 * TODO: Add routines with proper locking to do that...
1726 */
1727 node_a = node_b = NULL;
1728 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1729 if (strncmp(np->name, "ch-a", 4) == 0)
1730 node_a = of_node_get(np);
1731 else if (strncmp(np->name, "ch-b", 4) == 0)
1732 node_b = of_node_get(np);
1733 }
1734 if (!node_a && !node_b) {
1735 of_node_put(node_a);
1736 of_node_put(node_b);
1737 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1738 (!node_a) ? 'a' : 'b', node_p->full_name);
1739 goto next;
1740 }
1741
1742 /*
1743 * Fill basic fields in the port structures
1744 */
1745 pmz_ports[count].mate = &pmz_ports[count+1];
1746 pmz_ports[count+1].mate = &pmz_ports[count];
1747 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1748 pmz_ports[count].node = node_a;
1749 pmz_ports[count+1].node = node_b;
1750 pmz_ports[count].port.line = count;
1751 pmz_ports[count+1].port.line = count+1;
1752
1753 /*
1754 * Setup the ports for real
1755 */
1756 rc = pmz_init_port(&pmz_ports[count]);
1757 if (rc == 0 && node_b != NULL)
1758 rc = pmz_init_port(&pmz_ports[count+1]);
1759 if (rc != 0) {
1760 of_node_put(node_a);
1761 of_node_put(node_b);
1762 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1763 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1764 goto next;
1765 }
1766 count += 2;
1767 next:
1768 node_p = of_find_node_by_name(node_p, "escc");
1769 }
1770 pmz_ports_count = count;
1771
1772 return 0;
1773 }
1774
1775 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1776
1777 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1778 static int __init pmz_console_setup(struct console *co, char *options);
1779
1780 static struct console pmz_console = {
1781 .name = "ttyS",
1782 .write = pmz_console_write,
1783 .device = uart_console_device,
1784 .setup = pmz_console_setup,
1785 .flags = CON_PRINTBUFFER,
1786 .index = -1,
1787 .data = &pmz_uart_reg,
1788 };
1789
1790 #define PMACZILOG_CONSOLE &pmz_console
1791 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1792 #define PMACZILOG_CONSOLE (NULL)
1793 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1794
1795 /*
1796 * Register the driver, console driver and ports with the serial
1797 * core
1798 */
1799 static int __init pmz_register(void)
1800 {
1801 int i, rc;
1802
1803 pmz_uart_reg.nr = pmz_ports_count;
1804 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1805 pmz_uart_reg.minor = 64;
1806
1807 /*
1808 * Register this driver with the serial core
1809 */
1810 rc = uart_register_driver(&pmz_uart_reg);
1811 if (rc)
1812 return rc;
1813
1814 /*
1815 * Register each port with the serial core
1816 */
1817 for (i = 0; i < pmz_ports_count; i++) {
1818 struct uart_pmac_port *uport = &pmz_ports[i];
1819 /* NULL node may happen on wallstreet */
1820 if (uport->node != NULL)
1821 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1822 if (rc)
1823 goto err_out;
1824 }
1825
1826 return 0;
1827 err_out:
1828 while (i-- > 0) {
1829 struct uart_pmac_port *uport = &pmz_ports[i];
1830 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1831 }
1832 uart_unregister_driver(&pmz_uart_reg);
1833 return rc;
1834 }
1835
1836 static struct of_device_id pmz_match[] =
1837 {
1838 {
1839 .name = "ch-a",
1840 },
1841 {
1842 .name = "ch-b",
1843 },
1844 {},
1845 };
1846 MODULE_DEVICE_TABLE (of, pmz_match);
1847
1848 static struct macio_driver pmz_driver =
1849 {
1850 .name = "pmac_zilog",
1851 .match_table = pmz_match,
1852 .probe = pmz_attach,
1853 .remove = pmz_detach,
1854 .suspend = pmz_suspend,
1855 .resume = pmz_resume,
1856 };
1857
1858 static int __init init_pmz(void)
1859 {
1860 int rc, i;
1861 printk(KERN_INFO "%s\n", version);
1862
1863 /*
1864 * First, we need to do a direct OF-based probe pass. We
1865 * do that because we want serial console up before the
1866 * macio stuffs calls us back, and since that makes it
1867 * easier to pass the proper number of channels to
1868 * uart_register_driver()
1869 */
1870 if (pmz_ports_count == 0)
1871 pmz_probe();
1872
1873 /*
1874 * Bail early if no port found
1875 */
1876 if (pmz_ports_count == 0)
1877 return -ENODEV;
1878
1879 /*
1880 * Now we register with the serial layer
1881 */
1882 rc = pmz_register();
1883 if (rc) {
1884 printk(KERN_ERR
1885 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1886 "pmac_zilog: Did another serial driver already claim the minors?\n");
1887 /* effectively "pmz_unprobe()" */
1888 for (i=0; i < pmz_ports_count; i++)
1889 pmz_dispose_port(&pmz_ports[i]);
1890 return rc;
1891 }
1892
1893 /*
1894 * Then we register the macio driver itself
1895 */
1896 return macio_register_driver(&pmz_driver);
1897 }
1898
1899 static void __exit exit_pmz(void)
1900 {
1901 int i;
1902
1903 /* Get rid of macio-driver (detach from macio) */
1904 macio_unregister_driver(&pmz_driver);
1905
1906 for (i = 0; i < pmz_ports_count; i++) {
1907 struct uart_pmac_port *uport = &pmz_ports[i];
1908 if (uport->node != NULL) {
1909 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1910 pmz_dispose_port(uport);
1911 }
1912 }
1913 /* Unregister UART driver */
1914 uart_unregister_driver(&pmz_uart_reg);
1915 }
1916
1917 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1918
1919 /*
1920 * Print a string to the serial port trying not to disturb
1921 * any possible real use of the port...
1922 */
1923 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1924 {
1925 struct uart_pmac_port *uap = &pmz_ports[con->index];
1926 unsigned long flags;
1927 int i;
1928
1929 if (ZS_IS_ASLEEP(uap))
1930 return;
1931 spin_lock_irqsave(&uap->port.lock, flags);
1932
1933 /* Turn of interrupts and enable the transmitter. */
1934 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1935 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1936
1937 for (i = 0; i < count; i++) {
1938 /* Wait for the transmit buffer to empty. */
1939 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1940 udelay(5);
1941 write_zsdata(uap, s[i]);
1942 if (s[i] == 10) {
1943 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1944 udelay(5);
1945 write_zsdata(uap, R13);
1946 }
1947 }
1948
1949 /* Restore the values in the registers. */
1950 write_zsreg(uap, R1, uap->curregs[1]);
1951 /* Don't disable the transmitter. */
1952
1953 spin_unlock_irqrestore(&uap->port.lock, flags);
1954 }
1955
1956 /*
1957 * Setup the serial console
1958 */
1959 static int __init pmz_console_setup(struct console *co, char *options)
1960 {
1961 struct uart_pmac_port *uap;
1962 struct uart_port *port;
1963 int baud = 38400;
1964 int bits = 8;
1965 int parity = 'n';
1966 int flow = 'n';
1967 unsigned long pwr_delay;
1968
1969 /*
1970 * XServe's default to 57600 bps
1971 */
1972 if (machine_is_compatible("RackMac1,1")
1973 || machine_is_compatible("RackMac1,2")
1974 || machine_is_compatible("MacRISC4"))
1975 baud = 57600;
1976
1977 /*
1978 * Check whether an invalid uart number has been specified, and
1979 * if so, search for the first available port that does have
1980 * console support.
1981 */
1982 if (co->index >= pmz_ports_count)
1983 co->index = 0;
1984 uap = &pmz_ports[co->index];
1985 if (uap->node == NULL)
1986 return -ENODEV;
1987 port = &uap->port;
1988
1989 /*
1990 * Mark port as beeing a console
1991 */
1992 uap->flags |= PMACZILOG_FLAG_IS_CONS;
1993
1994 /*
1995 * Temporary fix for uart layer who didn't setup the spinlock yet
1996 */
1997 spin_lock_init(&port->lock);
1998
1999 /*
2000 * Enable the hardware
2001 */
2002 pwr_delay = __pmz_startup(uap);
2003 if (pwr_delay)
2004 mdelay(pwr_delay);
2005
2006 if (options)
2007 uart_parse_options(options, &baud, &parity, &bits, &flow);
2008
2009 return uart_set_options(port, co, baud, parity, bits, flow);
2010 }
2011
2012 static int __init pmz_console_init(void)
2013 {
2014 /* Probe ports */
2015 pmz_probe();
2016
2017 /* TODO: Autoprobe console based on OF */
2018 /* pmz_console.index = i; */
2019 register_console(&pmz_console);
2020
2021 return 0;
2022
2023 }
2024 console_initcall(pmz_console_init);
2025 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2026
2027 module_init(init_pmz);
2028 module_exit(exit_pmz);
Support for the Chinese Samsung S3C2440 based development boards