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[CPUFREQ] Fix the p4-clockmod N60 errata workaround.
[linux-2.6/mini2440.git] / drivers / serial / mpsc.c
blob0ca83ac31d07a379eb95727ff8718392dd073c37
1 /*
2 * drivers/serial/mpsc.c
3 *
4 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
5 * GT64260, MV64340, MV64360, GT96100, ... ).
6 *
7 * Author: Mark A. Greer <mgreer@mvista.com>
8 *
9 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
10 * have been created by Chris Zankel (formerly of MontaVista) but there
11 * is no proper Copyright so I'm not sure. Apparently, parts were also
12 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
13 * by Russell King.
14 *
15 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
16 * the terms of the GNU General Public License version 2. This program
17 * is licensed "as is" without any warranty of any kind, whether express
18 * or implied.
19 */
20 /*
21 * The MPSC interface is much like a typical network controller's interface.
22 * That is, you set up separate rings of descriptors for transmitting and
23 * receiving data. There is also a pool of buffers with (one buffer per
24 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
25 * out of.
26 *
27 * The MPSC requires two other controllers to be able to work. The Baud Rate
28 * Generator (BRG) provides a clock at programmable frequencies which determines
29 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
30 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
31 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
32 * transmit and receive "engines" going (i.e., indicate data has been
33 * transmitted or received).
34 *
35 * NOTES:
36 *
37 * 1) Some chips have an erratum where several regs cannot be
38 * read. To work around that, we keep a local copy of those regs in
39 * 'mpsc_port_info'.
40 *
41 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
42 * accesses system mem with coherency enabled. For that reason, the driver
43 * assumes that coherency for that ctlr has been disabled. This means
44 * that when in a cache coherent system, the driver has to manually manage
45 * the data cache on the areas that it touches because the dma_* macro are
46 * basically no-ops.
47 *
48 * 3) There is an erratum (on PPC) where you can't use the instruction to do
49 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
50 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
51 *
52 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
53 */
54
55 #include <linux/platform_device.h>
56
57 #include "mpsc.h"
58
59 /*
60 * Define how this driver is known to the outside (we've been assigned a
61 * range on the "Low-density serial ports" major).
62 */
63 #define MPSC_MAJOR 204
64 #define MPSC_MINOR_START 44
65 #define MPSC_DRIVER_NAME "MPSC"
66 #define MPSC_DEVFS_NAME "ttymm/"
67 #define MPSC_DEV_NAME "ttyMM"
68 #define MPSC_VERSION "1.00"
69
70 static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
71 static struct mpsc_shared_regs mpsc_shared_regs;
72 static struct uart_driver mpsc_reg;
73
74 static void mpsc_start_rx(struct mpsc_port_info *pi);
75 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
76 static void mpsc_release_port(struct uart_port *port);
77 /*
78 ******************************************************************************
79 *
80 * Baud Rate Generator Routines (BRG)
81 *
82 ******************************************************************************
83 */
84 static void
85 mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
86 {
87 u32 v;
88
89 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
90 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
91
92 if (pi->brg_can_tune)
93 v &= ~(1 << 25);
94
95 if (pi->mirror_regs)
96 pi->BRG_BCR_m = v;
97 writel(v, pi->brg_base + BRG_BCR);
98
99 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
100 pi->brg_base + BRG_BTR);
101 return;
102 }
103
104 static void
105 mpsc_brg_enable(struct mpsc_port_info *pi)
106 {
107 u32 v;
108
109 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
110 v |= (1 << 16);
111
112 if (pi->mirror_regs)
113 pi->BRG_BCR_m = v;
114 writel(v, pi->brg_base + BRG_BCR);
115 return;
116 }
117
118 static void
119 mpsc_brg_disable(struct mpsc_port_info *pi)
120 {
121 u32 v;
122
123 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
124 v &= ~(1 << 16);
125
126 if (pi->mirror_regs)
127 pi->BRG_BCR_m = v;
128 writel(v, pi->brg_base + BRG_BCR);
129 return;
130 }
131
132 static inline void
133 mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
134 {
135 /*
136 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
137 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
138 * However, the input clock is divided by 16 in the MPSC b/c of how
139 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
140 * calculation by 16 to account for that. So the real calculation
141 * that accounts for the way the mpsc is set up is:
142 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
143 */
144 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
145 u32 v;
146
147 mpsc_brg_disable(pi);
148 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
149 v = (v & 0xffff0000) | (cdv & 0xffff);
150
151 if (pi->mirror_regs)
152 pi->BRG_BCR_m = v;
153 writel(v, pi->brg_base + BRG_BCR);
154 mpsc_brg_enable(pi);
155
156 return;
157 }
158
159 /*
160 ******************************************************************************
161 *
162 * Serial DMA Routines (SDMA)
163 *
164 ******************************************************************************
165 */
166
167 static void
168 mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
169 {
170 u32 v;
171
172 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
173 pi->port.line, burst_size);
174
175 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
176
177 if (burst_size < 2)
178 v = 0x0; /* 1 64-bit word */
179 else if (burst_size < 4)
180 v = 0x1; /* 2 64-bit words */
181 else if (burst_size < 8)
182 v = 0x2; /* 4 64-bit words */
183 else
184 v = 0x3; /* 8 64-bit words */
185
186 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
187 pi->sdma_base + SDMA_SDC);
188 return;
189 }
190
191 static void
192 mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
193 {
194 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
195 burst_size);
196
197 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
198 pi->sdma_base + SDMA_SDC);
199 mpsc_sdma_burstsize(pi, burst_size);
200 return;
201 }
202
203 static inline u32
204 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
205 {
206 u32 old, v;
207
208 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
209
210 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
211 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
212
213 mask &= 0xf;
214 if (pi->port.line)
215 mask <<= 8;
216 v &= ~mask;
217
218 if (pi->mirror_regs)
219 pi->shared_regs->SDMA_INTR_MASK_m = v;
220 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
221
222 if (pi->port.line)
223 old >>= 8;
224 return old & 0xf;
225 }
226
227 static inline void
228 mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
229 {
230 u32 v;
231
232 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
233
234 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
235 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
236
237 mask &= 0xf;
238 if (pi->port.line)
239 mask <<= 8;
240 v |= mask;
241
242 if (pi->mirror_regs)
243 pi->shared_regs->SDMA_INTR_MASK_m = v;
244 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
245 return;
246 }
247
248 static inline void
249 mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
250 {
251 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
252
253 if (pi->mirror_regs)
254 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
255 writel(0, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE);
256 return;
257 }
258
259 static inline void
260 mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p)
261 {
262 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
263 pi->port.line, (u32) rxre_p);
264
265 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
266 return;
267 }
268
269 static inline void
270 mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p)
271 {
272 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
273 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
274 return;
275 }
276
277 static inline void
278 mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
279 {
280 u32 v;
281
282 v = readl(pi->sdma_base + SDMA_SDCM);
283 if (val)
284 v |= val;
285 else
286 v = 0;
287 wmb();
288 writel(v, pi->sdma_base + SDMA_SDCM);
289 wmb();
290 return;
291 }
292
293 static inline uint
294 mpsc_sdma_tx_active(struct mpsc_port_info *pi)
295 {
296 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
297 }
298
299 static inline void
300 mpsc_sdma_start_tx(struct mpsc_port_info *pi)
301 {
302 struct mpsc_tx_desc *txre, *txre_p;
303
304 /* If tx isn't running & there's a desc ready to go, start it */
305 if (!mpsc_sdma_tx_active(pi)) {
306 txre = (struct mpsc_tx_desc *)(pi->txr +
307 (pi->txr_tail * MPSC_TXRE_SIZE));
308 dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
309 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
310 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
311 invalidate_dcache_range((ulong)txre,
312 (ulong)txre + MPSC_TXRE_SIZE);
313 #endif
314
315 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
316 txre_p = (struct mpsc_tx_desc *)(pi->txr_p +
317 (pi->txr_tail *
318 MPSC_TXRE_SIZE));
319
320 mpsc_sdma_set_tx_ring(pi, txre_p);
321 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
322 }
323 }
324
325 return;
326 }
327
328 static inline void
329 mpsc_sdma_stop(struct mpsc_port_info *pi)
330 {
331 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
332
333 /* Abort any SDMA transfers */
334 mpsc_sdma_cmd(pi, 0);
335 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
336
337 /* Clear the SDMA current and first TX and RX pointers */
338 mpsc_sdma_set_tx_ring(pi, NULL);
339 mpsc_sdma_set_rx_ring(pi, NULL);
340
341 /* Disable interrupts */
342 mpsc_sdma_intr_mask(pi, 0xf);
343 mpsc_sdma_intr_ack(pi);
344
345 return;
346 }
347
348 /*
349 ******************************************************************************
350 *
351 * Multi-Protocol Serial Controller Routines (MPSC)
352 *
353 ******************************************************************************
354 */
355
356 static void
357 mpsc_hw_init(struct mpsc_port_info *pi)
358 {
359 u32 v;
360
361 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
362
363 /* Set up clock routing */
364 if (pi->mirror_regs) {
365 v = pi->shared_regs->MPSC_MRR_m;
366 v &= ~0x1c7;
367 pi->shared_regs->MPSC_MRR_m = v;
368 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
369
370 v = pi->shared_regs->MPSC_RCRR_m;
371 v = (v & ~0xf0f) | 0x100;
372 pi->shared_regs->MPSC_RCRR_m = v;
373 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
374
375 v = pi->shared_regs->MPSC_TCRR_m;
376 v = (v & ~0xf0f) | 0x100;
377 pi->shared_regs->MPSC_TCRR_m = v;
378 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
379 }
380 else {
381 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
382 v &= ~0x1c7;
383 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
384
385 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
386 v = (v & ~0xf0f) | 0x100;
387 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
388
389 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
390 v = (v & ~0xf0f) | 0x100;
391 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
392 }
393
394 /* Put MPSC in UART mode & enabel Tx/Rx egines */
395 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
396
397 /* No preamble, 16x divider, low-latency, */
398 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
399
400 if (pi->mirror_regs) {
401 pi->MPSC_CHR_1_m = 0;
402 pi->MPSC_CHR_2_m = 0;
403 }
404 writel(0, pi->mpsc_base + MPSC_CHR_1);
405 writel(0, pi->mpsc_base + MPSC_CHR_2);
406 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
407 writel(0, pi->mpsc_base + MPSC_CHR_4);
408 writel(0, pi->mpsc_base + MPSC_CHR_5);
409 writel(0, pi->mpsc_base + MPSC_CHR_6);
410 writel(0, pi->mpsc_base + MPSC_CHR_7);
411 writel(0, pi->mpsc_base + MPSC_CHR_8);
412 writel(0, pi->mpsc_base + MPSC_CHR_9);
413 writel(0, pi->mpsc_base + MPSC_CHR_10);
414
415 return;
416 }
417
418 static inline void
419 mpsc_enter_hunt(struct mpsc_port_info *pi)
420 {
421 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
422
423 if (pi->mirror_regs) {
424 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
425 pi->mpsc_base + MPSC_CHR_2);
426 /* Erratum prevents reading CHR_2 so just delay for a while */
427 udelay(100);
428 }
429 else {
430 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
431 pi->mpsc_base + MPSC_CHR_2);
432
433 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
434 udelay(10);
435 }
436
437 return;
438 }
439
440 static inline void
441 mpsc_freeze(struct mpsc_port_info *pi)
442 {
443 u32 v;
444
445 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
446
447 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
448 readl(pi->mpsc_base + MPSC_MPCR);
449 v |= MPSC_MPCR_FRZ;
450
451 if (pi->mirror_regs)
452 pi->MPSC_MPCR_m = v;
453 writel(v, pi->mpsc_base + MPSC_MPCR);
454 return;
455 }
456
457 static inline void
458 mpsc_unfreeze(struct mpsc_port_info *pi)
459 {
460 u32 v;
461
462 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
463 readl(pi->mpsc_base + MPSC_MPCR);
464 v &= ~MPSC_MPCR_FRZ;
465
466 if (pi->mirror_regs)
467 pi->MPSC_MPCR_m = v;
468 writel(v, pi->mpsc_base + MPSC_MPCR);
469
470 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
471 return;
472 }
473
474 static inline void
475 mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
476 {
477 u32 v;
478
479 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
480
481 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
482 readl(pi->mpsc_base + MPSC_MPCR);
483 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
484
485 if (pi->mirror_regs)
486 pi->MPSC_MPCR_m = v;
487 writel(v, pi->mpsc_base + MPSC_MPCR);
488 return;
489 }
490
491 static inline void
492 mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
493 {
494 u32 v;
495
496 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
497 pi->port.line, len);
498
499 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
500 readl(pi->mpsc_base + MPSC_MPCR);
501
502 v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
503
504 if (pi->mirror_regs)
505 pi->MPSC_MPCR_m = v;
506 writel(v, pi->mpsc_base + MPSC_MPCR);
507 return;
508 }
509
510 static inline void
511 mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
512 {
513 u32 v;
514
515 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
516
517 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
518 readl(pi->mpsc_base + MPSC_CHR_2);
519
520 p &= 0x3;
521 v = (v & ~0xc000c) | (p << 18) | (p << 2);
522
523 if (pi->mirror_regs)
524 pi->MPSC_CHR_2_m = v;
525 writel(v, pi->mpsc_base + MPSC_CHR_2);
526 return;
527 }
528
529 /*
530 ******************************************************************************
531 *
532 * Driver Init Routines
533 *
534 ******************************************************************************
535 */
536
537 static void
538 mpsc_init_hw(struct mpsc_port_info *pi)
539 {
540 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
541
542 mpsc_brg_init(pi, pi->brg_clk_src);
543 mpsc_brg_enable(pi);
544 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
545 mpsc_sdma_stop(pi);
546 mpsc_hw_init(pi);
547
548 return;
549 }
550
551 static int
552 mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
553 {
554 int rc = 0;
555
556 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
557 pi->port.line);
558
559 if (!pi->dma_region) {
560 if (!dma_supported(pi->port.dev, 0xffffffff)) {
561 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
562 rc = -ENXIO;
563 }
564 else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
565 MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL))
566 == NULL) {
567
568 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
569 rc = -ENOMEM;
570 }
571 }
572
573 return rc;
574 }
575
576 static void
577 mpsc_free_ring_mem(struct mpsc_port_info *pi)
578 {
579 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
580
581 if (pi->dma_region) {
582 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
583 pi->dma_region, pi->dma_region_p);
584 pi->dma_region = NULL;
585 pi->dma_region_p = (dma_addr_t) NULL;
586 }
587
588 return;
589 }
590
591 static void
592 mpsc_init_rings(struct mpsc_port_info *pi)
593 {
594 struct mpsc_rx_desc *rxre;
595 struct mpsc_tx_desc *txre;
596 dma_addr_t dp, dp_p;
597 u8 *bp, *bp_p;
598 int i;
599
600 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
601
602 BUG_ON(pi->dma_region == NULL);
603
604 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
605
606 /*
607 * Descriptors & buffers are multiples of cacheline size and must be
608 * cacheline aligned.
609 */
610 dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment());
611 dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment());
612
613 /*
614 * Partition dma region into rx ring descriptor, rx buffers,
615 * tx ring descriptors, and tx buffers.
616 */
617 pi->rxr = dp;
618 pi->rxr_p = dp_p;
619 dp += MPSC_RXR_SIZE;
620 dp_p += MPSC_RXR_SIZE;
621
622 pi->rxb = (u8 *) dp;
623 pi->rxb_p = (u8 *) dp_p;
624 dp += MPSC_RXB_SIZE;
625 dp_p += MPSC_RXB_SIZE;
626
627 pi->rxr_posn = 0;
628
629 pi->txr = dp;
630 pi->txr_p = dp_p;
631 dp += MPSC_TXR_SIZE;
632 dp_p += MPSC_TXR_SIZE;
633
634 pi->txb = (u8 *) dp;
635 pi->txb_p = (u8 *) dp_p;
636
637 pi->txr_head = 0;
638 pi->txr_tail = 0;
639
640 /* Init rx ring descriptors */
641 dp = pi->rxr;
642 dp_p = pi->rxr_p;
643 bp = pi->rxb;
644 bp_p = pi->rxb_p;
645
646 for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
647 rxre = (struct mpsc_rx_desc *)dp;
648
649 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
650 rxre->bytecnt = cpu_to_be16(0);
651 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
652 SDMA_DESC_CMDSTAT_EI |
653 SDMA_DESC_CMDSTAT_F |
654 SDMA_DESC_CMDSTAT_L);
655 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
656 rxre->buf_ptr = cpu_to_be32(bp_p);
657
658 dp += MPSC_RXRE_SIZE;
659 dp_p += MPSC_RXRE_SIZE;
660 bp += MPSC_RXBE_SIZE;
661 bp_p += MPSC_RXBE_SIZE;
662 }
663 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
664
665 /* Init tx ring descriptors */
666 dp = pi->txr;
667 dp_p = pi->txr_p;
668 bp = pi->txb;
669 bp_p = pi->txb_p;
670
671 for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
672 txre = (struct mpsc_tx_desc *)dp;
673
674 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
675 txre->buf_ptr = cpu_to_be32(bp_p);
676
677 dp += MPSC_TXRE_SIZE;
678 dp_p += MPSC_TXRE_SIZE;
679 bp += MPSC_TXBE_SIZE;
680 bp_p += MPSC_TXBE_SIZE;
681 }
682 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
683
684 dma_cache_sync((void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE,
685 DMA_BIDIRECTIONAL);
686 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
687 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
688 flush_dcache_range((ulong)pi->dma_region,
689 (ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE);
690 #endif
691
692 return;
693 }
694
695 static void
696 mpsc_uninit_rings(struct mpsc_port_info *pi)
697 {
698 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
699
700 BUG_ON(pi->dma_region == NULL);
701
702 pi->rxr = 0;
703 pi->rxr_p = 0;
704 pi->rxb = NULL;
705 pi->rxb_p = NULL;
706 pi->rxr_posn = 0;
707
708 pi->txr = 0;
709 pi->txr_p = 0;
710 pi->txb = NULL;
711 pi->txb_p = NULL;
712 pi->txr_head = 0;
713 pi->txr_tail = 0;
714
715 return;
716 }
717
718 static int
719 mpsc_make_ready(struct mpsc_port_info *pi)
720 {
721 int rc;
722
723 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
724
725 if (!pi->ready) {
726 mpsc_init_hw(pi);
727 if ((rc = mpsc_alloc_ring_mem(pi)))
728 return rc;
729 mpsc_init_rings(pi);
730 pi->ready = 1;
731 }
732
733 return 0;
734 }
735
736 /*
737 ******************************************************************************
738 *
739 * Interrupt Handling Routines
740 *
741 ******************************************************************************
742 */
743
744 static inline int
745 mpsc_rx_intr(struct mpsc_port_info *pi, struct pt_regs *regs)
746 {
747 struct mpsc_rx_desc *rxre;
748 struct tty_struct *tty = pi->port.info->tty;
749 u32 cmdstat, bytes_in, i;
750 int rc = 0;
751 u8 *bp;
752 char flag = TTY_NORMAL;
753
754 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
755
756 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
757
758 dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
759 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
760 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
761 invalidate_dcache_range((ulong)rxre,
762 (ulong)rxre + MPSC_RXRE_SIZE);
763 #endif
764
765 /*
766 * Loop through Rx descriptors handling ones that have been completed.
767 */
768 while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){
769 bytes_in = be16_to_cpu(rxre->bytecnt);
770
771 /* Following use of tty struct directly is deprecated */
772 if (unlikely(tty_buffer_request_room(tty, bytes_in) < bytes_in)) {
773 if (tty->low_latency)
774 tty_flip_buffer_push(tty);
775 /*
776 * If this failed then we will throw away the bytes
777 * but must do so to clear interrupts.
778 */
779 }
780
781 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
782 dma_cache_sync((void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
783 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
784 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
785 invalidate_dcache_range((ulong)bp,
786 (ulong)bp + MPSC_RXBE_SIZE);
787 #endif
788
789 /*
790 * Other than for parity error, the manual provides little
791 * info on what data will be in a frame flagged by any of
792 * these errors. For parity error, it is the last byte in
793 * the buffer that had the error. As for the rest, I guess
794 * we'll assume there is no data in the buffer.
795 * If there is...it gets lost.
796 */
797 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
798 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) {
799
800 pi->port.icount.rx++;
801
802 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
803 pi->port.icount.brk++;
804
805 if (uart_handle_break(&pi->port))
806 goto next_frame;
807 }
808 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)/* Framing */
809 pi->port.icount.frame++;
810 else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */
811 pi->port.icount.overrun++;
812
813 cmdstat &= pi->port.read_status_mask;
814
815 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
816 flag = TTY_BREAK;
817 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
818 flag = TTY_FRAME;
819 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
820 flag = TTY_OVERRUN;
821 else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
822 flag = TTY_PARITY;
823 }
824
825 if (uart_handle_sysrq_char(&pi->port, *bp, regs)) {
826 bp++;
827 bytes_in--;
828 goto next_frame;
829 }
830
831 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
832 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
833 !(cmdstat & pi->port.ignore_status_mask))
834
835 tty_insert_flip_char(tty, *bp, flag);
836 else {
837 for (i=0; i<bytes_in; i++)
838 tty_insert_flip_char(tty, *bp++, TTY_NORMAL);
839
840 pi->port.icount.rx += bytes_in;
841 }
842
843 next_frame:
844 rxre->bytecnt = cpu_to_be16(0);
845 wmb();
846 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
847 SDMA_DESC_CMDSTAT_EI |
848 SDMA_DESC_CMDSTAT_F |
849 SDMA_DESC_CMDSTAT_L);
850 wmb();
851 dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
852 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
853 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
854 flush_dcache_range((ulong)rxre,
855 (ulong)rxre + MPSC_RXRE_SIZE);
856 #endif
857
858 /* Advance to next descriptor */
859 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
860 rxre = (struct mpsc_rx_desc *)(pi->rxr +
861 (pi->rxr_posn * MPSC_RXRE_SIZE));
862 dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
863 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
864 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
865 invalidate_dcache_range((ulong)rxre,
866 (ulong)rxre + MPSC_RXRE_SIZE);
867 #endif
868
869 rc = 1;
870 }
871
872 /* Restart rx engine, if its stopped */
873 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
874 mpsc_start_rx(pi);
875
876 tty_flip_buffer_push(tty);
877 return rc;
878 }
879
880 static inline void
881 mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
882 {
883 struct mpsc_tx_desc *txre;
884
885 txre = (struct mpsc_tx_desc *)(pi->txr +
886 (pi->txr_head * MPSC_TXRE_SIZE));
887
888 txre->bytecnt = cpu_to_be16(count);
889 txre->shadow = txre->bytecnt;
890 wmb(); /* ensure cmdstat is last field updated */
891 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F |
892 SDMA_DESC_CMDSTAT_L | ((intr) ?
893 SDMA_DESC_CMDSTAT_EI
894 : 0));
895 wmb();
896 dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL);
897 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
898 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
899 flush_dcache_range((ulong)txre,
900 (ulong)txre + MPSC_TXRE_SIZE);
901 #endif
902
903 return;
904 }
905
906 static inline void
907 mpsc_copy_tx_data(struct mpsc_port_info *pi)
908 {
909 struct circ_buf *xmit = &pi->port.info->xmit;
910 u8 *bp;
911 u32 i;
912
913 /* Make sure the desc ring isn't full */
914 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) <
915 (MPSC_TXR_ENTRIES - 1)) {
916 if (pi->port.x_char) {
917 /*
918 * Ideally, we should use the TCS field in
919 * CHR_1 to put the x_char out immediately but
920 * errata prevents us from being able to read
921 * CHR_2 to know that its safe to write to
922 * CHR_1. Instead, just put it in-band with
923 * all the other Tx data.
924 */
925 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
926 *bp = pi->port.x_char;
927 pi->port.x_char = 0;
928 i = 1;
929 }
930 else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){
931 i = min((u32) MPSC_TXBE_SIZE,
932 (u32) uart_circ_chars_pending(xmit));
933 i = min(i, (u32) CIRC_CNT_TO_END(xmit->head, xmit->tail,
934 UART_XMIT_SIZE));
935 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
936 memcpy(bp, &xmit->buf[xmit->tail], i);
937 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
938
939 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
940 uart_write_wakeup(&pi->port);
941 }
942 else /* All tx data copied into ring bufs */
943 return;
944
945 dma_cache_sync((void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
946 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
947 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
948 flush_dcache_range((ulong)bp,
949 (ulong)bp + MPSC_TXBE_SIZE);
950 #endif
951 mpsc_setup_tx_desc(pi, i, 1);
952
953 /* Advance to next descriptor */
954 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
955 }
956
957 return;
958 }
959
960 static inline int
961 mpsc_tx_intr(struct mpsc_port_info *pi)
962 {
963 struct mpsc_tx_desc *txre;
964 int rc = 0;
965
966 if (!mpsc_sdma_tx_active(pi)) {
967 txre = (struct mpsc_tx_desc *)(pi->txr +
968 (pi->txr_tail * MPSC_TXRE_SIZE));
969
970 dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
971 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
972 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
973 invalidate_dcache_range((ulong)txre,
974 (ulong)txre + MPSC_TXRE_SIZE);
975 #endif
976
977 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
978 rc = 1;
979 pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
980 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
981
982 /* If no more data to tx, fall out of loop */
983 if (pi->txr_head == pi->txr_tail)
984 break;
985
986 txre = (struct mpsc_tx_desc *)(pi->txr +
987 (pi->txr_tail * MPSC_TXRE_SIZE));
988 dma_cache_sync((void *) txre, MPSC_TXRE_SIZE,
989 DMA_FROM_DEVICE);
990 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
991 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
992 invalidate_dcache_range((ulong)txre,
993 (ulong)txre + MPSC_TXRE_SIZE);
994 #endif
995 }
996
997 mpsc_copy_tx_data(pi);
998 mpsc_sdma_start_tx(pi); /* start next desc if ready */
999 }
1000
1001 return rc;
1002 }
1003
1004 /*
1005 * This is the driver's interrupt handler. To avoid a race, we first clear
1006 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1007 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1008 */
1009 static irqreturn_t
1010 mpsc_sdma_intr(int irq, void *dev_id, struct pt_regs *regs)
1011 {
1012 struct mpsc_port_info *pi = dev_id;
1013 ulong iflags;
1014 int rc = IRQ_NONE;
1015
1016 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1017
1018 spin_lock_irqsave(&pi->port.lock, iflags);
1019 mpsc_sdma_intr_ack(pi);
1020 if (mpsc_rx_intr(pi, regs))
1021 rc = IRQ_HANDLED;
1022 if (mpsc_tx_intr(pi))
1023 rc = IRQ_HANDLED;
1024 spin_unlock_irqrestore(&pi->port.lock, iflags);
1025
1026 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1027 return rc;
1028 }
1029
1030 /*
1031 ******************************************************************************
1032 *
1033 * serial_core.c Interface routines
1034 *
1035 ******************************************************************************
1036 */
1037 static uint
1038 mpsc_tx_empty(struct uart_port *port)
1039 {
1040 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1041 ulong iflags;
1042 uint rc;
1043
1044 spin_lock_irqsave(&pi->port.lock, iflags);
1045 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1046 spin_unlock_irqrestore(&pi->port.lock, iflags);
1047
1048 return rc;
1049 }
1050
1051 static void
1052 mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1053 {
1054 /* Have no way to set modem control lines AFAICT */
1055 return;
1056 }
1057
1058 static uint
1059 mpsc_get_mctrl(struct uart_port *port)
1060 {
1061 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1062 u32 mflags, status;
1063
1064 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m :
1065 readl(pi->mpsc_base + MPSC_CHR_10);
1066
1067 mflags = 0;
1068 if (status & 0x1)
1069 mflags |= TIOCM_CTS;
1070 if (status & 0x2)
1071 mflags |= TIOCM_CAR;
1072
1073 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1074 }
1075
1076 static void
1077 mpsc_stop_tx(struct uart_port *port)
1078 {
1079 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1080
1081 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1082
1083 mpsc_freeze(pi);
1084 return;
1085 }
1086
1087 static void
1088 mpsc_start_tx(struct uart_port *port)
1089 {
1090 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1091
1092 mpsc_unfreeze(pi);
1093 mpsc_copy_tx_data(pi);
1094 mpsc_sdma_start_tx(pi);
1095
1096 pr_debug("mpsc_start_tx[%d]\n", port->line);
1097 return;
1098 }
1099
1100 static void
1101 mpsc_start_rx(struct mpsc_port_info *pi)
1102 {
1103 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1104
1105 /* Issue a Receive Abort to clear any receive errors */
1106 writel(MPSC_CHR_2_RA, pi->mpsc_base + MPSC_CHR_2);
1107 if (pi->rcv_data) {
1108 mpsc_enter_hunt(pi);
1109 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1110 }
1111 return;
1112 }
1113
1114 static void
1115 mpsc_stop_rx(struct uart_port *port)
1116 {
1117 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1118
1119 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1120
1121 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1122 return;
1123 }
1124
1125 static void
1126 mpsc_enable_ms(struct uart_port *port)
1127 {
1128 return; /* Not supported */
1129 }
1130
1131 static void
1132 mpsc_break_ctl(struct uart_port *port, int ctl)
1133 {
1134 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1135 ulong flags;
1136 u32 v;
1137
1138 v = ctl ? 0x00ff0000 : 0;
1139
1140 spin_lock_irqsave(&pi->port.lock, flags);
1141 if (pi->mirror_regs)
1142 pi->MPSC_CHR_1_m = v;
1143 writel(v, pi->mpsc_base + MPSC_CHR_1);
1144 spin_unlock_irqrestore(&pi->port.lock, flags);
1145
1146 return;
1147 }
1148
1149 static int
1150 mpsc_startup(struct uart_port *port)
1151 {
1152 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1153 u32 flag = 0;
1154 int rc;
1155
1156 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1157 port->line, pi->port.irq);
1158
1159 if ((rc = mpsc_make_ready(pi)) == 0) {
1160 /* Setup IRQ handler */
1161 mpsc_sdma_intr_ack(pi);
1162
1163 /* If irq's are shared, need to set flag */
1164 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
1165 flag = SA_SHIRQ;
1166
1167 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1168 "mpsc/sdma", pi))
1169 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1170 pi->port.irq);
1171
1172 mpsc_sdma_intr_unmask(pi, 0xf);
1173 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p +
1174 (pi->rxr_posn * MPSC_RXRE_SIZE)));
1175 }
1176
1177 return rc;
1178 }
1179
1180 static void
1181 mpsc_shutdown(struct uart_port *port)
1182 {
1183 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1184
1185 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1186
1187 mpsc_sdma_stop(pi);
1188 free_irq(pi->port.irq, pi);
1189 return;
1190 }
1191
1192 static void
1193 mpsc_set_termios(struct uart_port *port, struct termios *termios,
1194 struct termios *old)
1195 {
1196 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1197 u32 baud;
1198 ulong flags;
1199 u32 chr_bits, stop_bits, par;
1200
1201 pi->c_iflag = termios->c_iflag;
1202 pi->c_cflag = termios->c_cflag;
1203
1204 switch (termios->c_cflag & CSIZE) {
1205 case CS5:
1206 chr_bits = MPSC_MPCR_CL_5;
1207 break;
1208 case CS6:
1209 chr_bits = MPSC_MPCR_CL_6;
1210 break;
1211 case CS7:
1212 chr_bits = MPSC_MPCR_CL_7;
1213 break;
1214 case CS8:
1215 default:
1216 chr_bits = MPSC_MPCR_CL_8;
1217 break;
1218 }
1219
1220 if (termios->c_cflag & CSTOPB)
1221 stop_bits = MPSC_MPCR_SBL_2;
1222 else
1223 stop_bits = MPSC_MPCR_SBL_1;
1224
1225 par = MPSC_CHR_2_PAR_EVEN;
1226 if (termios->c_cflag & PARENB)
1227 if (termios->c_cflag & PARODD)
1228 par = MPSC_CHR_2_PAR_ODD;
1229 #ifdef CMSPAR
1230 if (termios->c_cflag & CMSPAR) {
1231 if (termios->c_cflag & PARODD)
1232 par = MPSC_CHR_2_PAR_MARK;
1233 else
1234 par = MPSC_CHR_2_PAR_SPACE;
1235 }
1236 #endif
1237
1238 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1239
1240 spin_lock_irqsave(&pi->port.lock, flags);
1241
1242 uart_update_timeout(port, termios->c_cflag, baud);
1243
1244 mpsc_set_char_length(pi, chr_bits);
1245 mpsc_set_stop_bit_length(pi, stop_bits);
1246 mpsc_set_parity(pi, par);
1247 mpsc_set_baudrate(pi, baud);
1248
1249 /* Characters/events to read */
1250 pi->rcv_data = 1;
1251 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1252
1253 if (termios->c_iflag & INPCK)
1254 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE |
1255 SDMA_DESC_CMDSTAT_FR;
1256
1257 if (termios->c_iflag & (BRKINT | PARMRK))
1258 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1259
1260 /* Characters/events to ignore */
1261 pi->port.ignore_status_mask = 0;
1262
1263 if (termios->c_iflag & IGNPAR)
1264 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE |
1265 SDMA_DESC_CMDSTAT_FR;
1266
1267 if (termios->c_iflag & IGNBRK) {
1268 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1269
1270 if (termios->c_iflag & IGNPAR)
1271 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1272 }
1273
1274 /* Ignore all chars if CREAD not set */
1275 if (!(termios->c_cflag & CREAD))
1276 pi->rcv_data = 0;
1277 else
1278 mpsc_start_rx(pi);
1279
1280 spin_unlock_irqrestore(&pi->port.lock, flags);
1281 return;
1282 }
1283
1284 static const char *
1285 mpsc_type(struct uart_port *port)
1286 {
1287 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1288 return MPSC_DRIVER_NAME;
1289 }
1290
1291 static int
1292 mpsc_request_port(struct uart_port *port)
1293 {
1294 /* Should make chip/platform specific call */
1295 return 0;
1296 }
1297
1298 static void
1299 mpsc_release_port(struct uart_port *port)
1300 {
1301 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1302
1303 if (pi->ready) {
1304 mpsc_uninit_rings(pi);
1305 mpsc_free_ring_mem(pi);
1306 pi->ready = 0;
1307 }
1308
1309 return;
1310 }
1311
1312 static void
1313 mpsc_config_port(struct uart_port *port, int flags)
1314 {
1315 return;
1316 }
1317
1318 static int
1319 mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1320 {
1321 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1322 int rc = 0;
1323
1324 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1325
1326 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1327 rc = -EINVAL;
1328 else if (pi->port.irq != ser->irq)
1329 rc = -EINVAL;
1330 else if (ser->io_type != SERIAL_IO_MEM)
1331 rc = -EINVAL;
1332 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1333 rc = -EINVAL;
1334 else if ((void *)pi->port.mapbase != ser->iomem_base)
1335 rc = -EINVAL;
1336 else if (pi->port.iobase != ser->port)
1337 rc = -EINVAL;
1338 else if (ser->hub6 != 0)
1339 rc = -EINVAL;
1340
1341 return rc;
1342 }
1343
1344 static struct uart_ops mpsc_pops = {
1345 .tx_empty = mpsc_tx_empty,
1346 .set_mctrl = mpsc_set_mctrl,
1347 .get_mctrl = mpsc_get_mctrl,
1348 .stop_tx = mpsc_stop_tx,
1349 .start_tx = mpsc_start_tx,
1350 .stop_rx = mpsc_stop_rx,
1351 .enable_ms = mpsc_enable_ms,
1352 .break_ctl = mpsc_break_ctl,
1353 .startup = mpsc_startup,
1354 .shutdown = mpsc_shutdown,
1355 .set_termios = mpsc_set_termios,
1356 .type = mpsc_type,
1357 .release_port = mpsc_release_port,
1358 .request_port = mpsc_request_port,
1359 .config_port = mpsc_config_port,
1360 .verify_port = mpsc_verify_port,
1361 };
1362
1363 /*
1364 ******************************************************************************
1365 *
1366 * Console Interface Routines
1367 *
1368 ******************************************************************************
1369 */
1370
1371 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
1372 static void
1373 mpsc_console_write(struct console *co, const char *s, uint count)
1374 {
1375 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1376 u8 *bp, *dp, add_cr = 0;
1377 int i;
1378
1379 while (mpsc_sdma_tx_active(pi))
1380 udelay(100);
1381
1382 while (count > 0) {
1383 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1384
1385 for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1386 if (count == 0)
1387 break;
1388
1389 if (add_cr) {
1390 *(dp++) = '\r';
1391 add_cr = 0;
1392 }
1393 else {
1394 *(dp++) = *s;
1395
1396 if (*(s++) == '\n') { /* add '\r' after '\n' */
1397 add_cr = 1;
1398 count++;
1399 }
1400 }
1401
1402 count--;
1403 }
1404
1405 dma_cache_sync((void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
1406 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1407 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1408 flush_dcache_range((ulong)bp,
1409 (ulong)bp + MPSC_TXBE_SIZE);
1410 #endif
1411 mpsc_setup_tx_desc(pi, i, 0);
1412 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1413 mpsc_sdma_start_tx(pi);
1414
1415 while (mpsc_sdma_tx_active(pi))
1416 udelay(100);
1417
1418 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1419 }
1420
1421 return;
1422 }
1423
1424 static int __init
1425 mpsc_console_setup(struct console *co, char *options)
1426 {
1427 struct mpsc_port_info *pi;
1428 int baud, bits, parity, flow;
1429
1430 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1431
1432 if (co->index >= MPSC_NUM_CTLRS)
1433 co->index = 0;
1434
1435 pi = &mpsc_ports[co->index];
1436
1437 baud = pi->default_baud;
1438 bits = pi->default_bits;
1439 parity = pi->default_parity;
1440 flow = pi->default_flow;
1441
1442 if (!pi->port.ops)
1443 return -ENODEV;
1444
1445 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1446
1447 if (options)
1448 uart_parse_options(options, &baud, &parity, &bits, &flow);
1449
1450 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1451 }
1452
1453 static struct console mpsc_console = {
1454 .name = MPSC_DEV_NAME,
1455 .write = mpsc_console_write,
1456 .device = uart_console_device,
1457 .setup = mpsc_console_setup,
1458 .flags = CON_PRINTBUFFER,
1459 .index = -1,
1460 .data = &mpsc_reg,
1461 };
1462
1463 static int __init
1464 mpsc_late_console_init(void)
1465 {
1466 pr_debug("mpsc_late_console_init: Enter\n");
1467
1468 if (!(mpsc_console.flags & CON_ENABLED))
1469 register_console(&mpsc_console);
1470 return 0;
1471 }
1472
1473 late_initcall(mpsc_late_console_init);
1474
1475 #define MPSC_CONSOLE &mpsc_console
1476 #else
1477 #define MPSC_CONSOLE NULL
1478 #endif
1479 /*
1480 ******************************************************************************
1481 *
1482 * Dummy Platform Driver to extract & map shared register regions
1483 *
1484 ******************************************************************************
1485 */
1486 static void
1487 mpsc_resource_err(char *s)
1488 {
1489 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1490 return;
1491 }
1492
1493 static int
1494 mpsc_shared_map_regs(struct platform_device *pd)
1495 {
1496 struct resource *r;
1497
1498 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1499 MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start,
1500 MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) {
1501
1502 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
1503 MPSC_ROUTING_REG_BLOCK_SIZE);
1504 mpsc_shared_regs.mpsc_routing_base_p = r->start;
1505 }
1506 else {
1507 mpsc_resource_err("MPSC routing base");
1508 return -ENOMEM;
1509 }
1510
1511 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1512 MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start,
1513 MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) {
1514
1515 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1516 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1517 mpsc_shared_regs.sdma_intr_base_p = r->start;
1518 }
1519 else {
1520 iounmap(mpsc_shared_regs.mpsc_routing_base);
1521 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1522 MPSC_ROUTING_REG_BLOCK_SIZE);
1523 mpsc_resource_err("SDMA intr base");
1524 return -ENOMEM;
1525 }
1526
1527 return 0;
1528 }
1529
1530 static void
1531 mpsc_shared_unmap_regs(void)
1532 {
1533 if (!mpsc_shared_regs.mpsc_routing_base) {
1534 iounmap(mpsc_shared_regs.mpsc_routing_base);
1535 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1536 MPSC_ROUTING_REG_BLOCK_SIZE);
1537 }
1538 if (!mpsc_shared_regs.sdma_intr_base) {
1539 iounmap(mpsc_shared_regs.sdma_intr_base);
1540 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
1541 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1542 }
1543
1544 mpsc_shared_regs.mpsc_routing_base = NULL;
1545 mpsc_shared_regs.sdma_intr_base = NULL;
1546
1547 mpsc_shared_regs.mpsc_routing_base_p = 0;
1548 mpsc_shared_regs.sdma_intr_base_p = 0;
1549
1550 return;
1551 }
1552
1553 static int
1554 mpsc_shared_drv_probe(struct platform_device *dev)
1555 {
1556 struct mpsc_shared_pdata *pdata;
1557 int rc = -ENODEV;
1558
1559 if (dev->id == 0) {
1560 if (!(rc = mpsc_shared_map_regs(dev))) {
1561 pdata = (struct mpsc_shared_pdata *)dev->dev.platform_data;
1562
1563 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1564 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1565 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1566 mpsc_shared_regs.SDMA_INTR_CAUSE_m =
1567 pdata->intr_cause_val;
1568 mpsc_shared_regs.SDMA_INTR_MASK_m =
1569 pdata->intr_mask_val;
1570
1571 rc = 0;
1572 }
1573 }
1574
1575 return rc;
1576 }
1577
1578 static int
1579 mpsc_shared_drv_remove(struct platform_device *dev)
1580 {
1581 int rc = -ENODEV;
1582
1583 if (dev->id == 0) {
1584 mpsc_shared_unmap_regs();
1585 mpsc_shared_regs.MPSC_MRR_m = 0;
1586 mpsc_shared_regs.MPSC_RCRR_m = 0;
1587 mpsc_shared_regs.MPSC_TCRR_m = 0;
1588 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1589 mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1590 rc = 0;
1591 }
1592
1593 return rc;
1594 }
1595
1596 static struct platform_driver mpsc_shared_driver = {
1597 .probe = mpsc_shared_drv_probe,
1598 .remove = mpsc_shared_drv_remove,
1599 .driver = {
1600 .name = MPSC_SHARED_NAME,
1601 },
1602 };
1603
1604 /*
1605 ******************************************************************************
1606 *
1607 * Driver Interface Routines
1608 *
1609 ******************************************************************************
1610 */
1611 static struct uart_driver mpsc_reg = {
1612 .owner = THIS_MODULE,
1613 .driver_name = MPSC_DRIVER_NAME,
1614 .devfs_name = MPSC_DEVFS_NAME,
1615 .dev_name = MPSC_DEV_NAME,
1616 .major = MPSC_MAJOR,
1617 .minor = MPSC_MINOR_START,
1618 .nr = MPSC_NUM_CTLRS,
1619 .cons = MPSC_CONSOLE,
1620 };
1621
1622 static int
1623 mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd)
1624 {
1625 struct resource *r;
1626
1627 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) &&
1628 request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){
1629
1630 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1631 pi->mpsc_base_p = r->start;
1632 }
1633 else {
1634 mpsc_resource_err("MPSC base");
1635 return -ENOMEM;
1636 }
1637
1638 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1639 MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start,
1640 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1641
1642 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1643 pi->sdma_base_p = r->start;
1644 }
1645 else {
1646 mpsc_resource_err("SDMA base");
1647 return -ENOMEM;
1648 }
1649
1650 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
1651 && request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE,
1652 "brg_regs")) {
1653
1654 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1655 pi->brg_base_p = r->start;
1656 }
1657 else {
1658 mpsc_resource_err("BRG base");
1659 return -ENOMEM;
1660 }
1661
1662 return 0;
1663 }
1664
1665 static void
1666 mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
1667 {
1668 if (!pi->mpsc_base) {
1669 iounmap(pi->mpsc_base);
1670 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
1671 }
1672 if (!pi->sdma_base) {
1673 iounmap(pi->sdma_base);
1674 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
1675 }
1676 if (!pi->brg_base) {
1677 iounmap(pi->brg_base);
1678 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
1679 }
1680
1681 pi->mpsc_base = NULL;
1682 pi->sdma_base = NULL;
1683 pi->brg_base = NULL;
1684
1685 pi->mpsc_base_p = 0;
1686 pi->sdma_base_p = 0;
1687 pi->brg_base_p = 0;
1688
1689 return;
1690 }
1691
1692 static void
1693 mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
1694 struct platform_device *pd, int num)
1695 {
1696 struct mpsc_pdata *pdata;
1697
1698 pdata = (struct mpsc_pdata *)pd->dev.platform_data;
1699
1700 pi->port.uartclk = pdata->brg_clk_freq;
1701 pi->port.iotype = UPIO_MEM;
1702 pi->port.line = num;
1703 pi->port.type = PORT_MPSC;
1704 pi->port.fifosize = MPSC_TXBE_SIZE;
1705 pi->port.membase = pi->mpsc_base;
1706 pi->port.mapbase = (ulong)pi->mpsc_base;
1707 pi->port.ops = &mpsc_pops;
1708
1709 pi->mirror_regs = pdata->mirror_regs;
1710 pi->cache_mgmt = pdata->cache_mgmt;
1711 pi->brg_can_tune = pdata->brg_can_tune;
1712 pi->brg_clk_src = pdata->brg_clk_src;
1713 pi->mpsc_max_idle = pdata->max_idle;
1714 pi->default_baud = pdata->default_baud;
1715 pi->default_bits = pdata->default_bits;
1716 pi->default_parity = pdata->default_parity;
1717 pi->default_flow = pdata->default_flow;
1718
1719 /* Initial values of mirrored regs */
1720 pi->MPSC_CHR_1_m = pdata->chr_1_val;
1721 pi->MPSC_CHR_2_m = pdata->chr_2_val;
1722 pi->MPSC_CHR_10_m = pdata->chr_10_val;
1723 pi->MPSC_MPCR_m = pdata->mpcr_val;
1724 pi->BRG_BCR_m = pdata->bcr_val;
1725
1726 pi->shared_regs = &mpsc_shared_regs;
1727
1728 pi->port.irq = platform_get_irq(pd, 0);
1729
1730 return;
1731 }
1732
1733 static int
1734 mpsc_drv_probe(struct platform_device *dev)
1735 {
1736 struct mpsc_port_info *pi;
1737 int rc = -ENODEV;
1738
1739 pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id);
1740
1741 if (dev->id < MPSC_NUM_CTLRS) {
1742 pi = &mpsc_ports[dev->id];
1743
1744 if (!(rc = mpsc_drv_map_regs(pi, dev))) {
1745 mpsc_drv_get_platform_data(pi, dev, dev->id);
1746
1747 if (!(rc = mpsc_make_ready(pi)))
1748 if (!(rc = uart_add_one_port(&mpsc_reg,
1749 &pi->port)))
1750 rc = 0;
1751 else {
1752 mpsc_release_port(
1753 (struct uart_port *)pi);
1754 mpsc_drv_unmap_regs(pi);
1755 }
1756 else
1757 mpsc_drv_unmap_regs(pi);
1758 }
1759 }
1760
1761 return rc;
1762 }
1763
1764 static int
1765 mpsc_drv_remove(struct platform_device *dev)
1766 {
1767 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
1768
1769 if (dev->id < MPSC_NUM_CTLRS) {
1770 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
1771 mpsc_release_port((struct uart_port *)&mpsc_ports[dev->id].port);
1772 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
1773 return 0;
1774 }
1775 else
1776 return -ENODEV;
1777 }
1778
1779 static struct platform_driver mpsc_driver = {
1780 .probe = mpsc_drv_probe,
1781 .remove = mpsc_drv_remove,
1782 .driver = {
1783 .name = MPSC_CTLR_NAME,
1784 },
1785 };
1786
1787 static int __init
1788 mpsc_drv_init(void)
1789 {
1790 int rc;
1791
1792 printk(KERN_INFO "Serial: MPSC driver $Revision: 1.00 $\n");
1793
1794 memset(mpsc_ports, 0, sizeof(mpsc_ports));
1795 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
1796
1797 if (!(rc = uart_register_driver(&mpsc_reg))) {
1798 if (!(rc = platform_driver_register(&mpsc_shared_driver))) {
1799 if ((rc = platform_driver_register(&mpsc_driver))) {
1800 platform_driver_unregister(&mpsc_shared_driver);
1801 uart_unregister_driver(&mpsc_reg);
1802 }
1803 }
1804 else
1805 uart_unregister_driver(&mpsc_reg);
1806 }
1807
1808 return rc;
1809
1810 }
1811
1812 static void __exit
1813 mpsc_drv_exit(void)
1814 {
1815 platform_driver_unregister(&mpsc_driver);
1816 platform_driver_unregister(&mpsc_shared_driver);
1817 uart_unregister_driver(&mpsc_reg);
1818 memset(mpsc_ports, 0, sizeof(mpsc_ports));
1819 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
1820 return;
1821 }
1822
1823 module_init(mpsc_drv_init);
1824 module_exit(mpsc_drv_exit);
1825
1826 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1827 MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver $Revision: 1.00 $");
1828 MODULE_VERSION(MPSC_VERSION);
1829 MODULE_LICENSE("GPL");
1830 MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR);
Support for the Chinese Samsung S3C2440 based development boards