[CPUFREQ] Fix the p4-clockmod N60 errata workaround.
[linux-2.6/mini2440.git] / drivers / serial / ioc4_serial.c
blobf3763d2ccb866e31de2d3ff06ddda631f20eac7c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
7 */
11 * This file contains a module version of the ioc4 serial driver. This
12 * includes all the support functions needed (support functions, etc.)
13 * and the serial driver itself.
15 #include <linux/errno.h>
16 #include <linux/tty.h>
17 #include <linux/serial.h>
18 #include <linux/serialP.h>
19 #include <linux/circ_buf.h>
20 #include <linux/serial_reg.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/ioc4.h>
24 #include <linux/serial_core.h>
27 * interesting things about the ioc4
30 #define IOC4_NUM_SERIAL_PORTS 4 /* max ports per card */
31 #define IOC4_NUM_CARDS 8 /* max cards per partition */
33 #define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
34 (_n == 1) ? (IOC4_SIO_IR_S1) : \
35 (_n == 2) ? (IOC4_SIO_IR_S2) : \
36 (IOC4_SIO_IR_S3)
38 #define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
39 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
40 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
41 (IOC4_OTHER_IR_S3_MEMERR)
45 * All IOC4 registers are 32 bits wide.
49 * PCI Memory Space Map
51 #define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */
52 #define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
53 #define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
54 #define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
55 #define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
56 #define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
57 #define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
59 /* Interrupt types */
60 #define IOC4_SIO_INTR_TYPE 0
61 #define IOC4_OTHER_INTR_TYPE 1
62 #define IOC4_NUM_INTR_TYPES 2
64 /* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */
65 #define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */
66 #define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */
67 #define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */
68 #define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */
69 #define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */
70 #define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */
71 #define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */
72 #define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */
73 #define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */
74 #define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */
75 #define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */
76 #define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */
77 #define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */
78 #define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */
79 #define IOC4_SIO_IR_S1_INT 0x00004000 /* */
80 #define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */
81 #define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */
82 #define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */
83 #define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */
84 #define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */
85 #define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */
86 #define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */
87 #define IOC4_SIO_IR_S2_INT 0x00400000 /* */
88 #define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */
89 #define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */
90 #define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */
91 #define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */
92 #define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */
93 #define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */
94 #define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */
95 #define IOC4_SIO_IR_S3_INT 0x40000000 /* */
96 #define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */
98 /* Per device interrupt masks */
99 #define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
100 IOC4_SIO_IR_S0_RX_FULL | \
101 IOC4_SIO_IR_S0_RX_HIGH | \
102 IOC4_SIO_IR_S0_RX_TIMER | \
103 IOC4_SIO_IR_S0_DELTA_DCD | \
104 IOC4_SIO_IR_S0_DELTA_CTS | \
105 IOC4_SIO_IR_S0_INT | \
106 IOC4_SIO_IR_S0_TX_EXPLICIT)
107 #define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
108 IOC4_SIO_IR_S1_RX_FULL | \
109 IOC4_SIO_IR_S1_RX_HIGH | \
110 IOC4_SIO_IR_S1_RX_TIMER | \
111 IOC4_SIO_IR_S1_DELTA_DCD | \
112 IOC4_SIO_IR_S1_DELTA_CTS | \
113 IOC4_SIO_IR_S1_INT | \
114 IOC4_SIO_IR_S1_TX_EXPLICIT)
115 #define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
116 IOC4_SIO_IR_S2_RX_FULL | \
117 IOC4_SIO_IR_S2_RX_HIGH | \
118 IOC4_SIO_IR_S2_RX_TIMER | \
119 IOC4_SIO_IR_S2_DELTA_DCD | \
120 IOC4_SIO_IR_S2_DELTA_CTS | \
121 IOC4_SIO_IR_S2_INT | \
122 IOC4_SIO_IR_S2_TX_EXPLICIT)
123 #define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
124 IOC4_SIO_IR_S3_RX_FULL | \
125 IOC4_SIO_IR_S3_RX_HIGH | \
126 IOC4_SIO_IR_S3_RX_TIMER | \
127 IOC4_SIO_IR_S3_DELTA_DCD | \
128 IOC4_SIO_IR_S3_DELTA_CTS | \
129 IOC4_SIO_IR_S3_INT | \
130 IOC4_SIO_IR_S3_TX_EXPLICIT)
132 /* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */
133 #define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */
134 #define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */
135 #define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */
136 #define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */
137 #define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */
138 #define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */
139 #define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Keyboard/mouse */
140 #define IOC4_OTHER_IR_RESERVED 0x007fff80 /* Reserved */
141 #define IOC4_OTHER_IR_RT_INT 0x00800000 /* INT_OUT section output */
142 #define IOC4_OTHER_IR_GEN_INT 0xff000000 /* Generic pins */
144 #define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
145 IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
147 /* Bitmasks for IOC4_SIO_CR */
148 #define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 /* byte bus strobe shift */
149 #define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
150 #define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
151 #define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
152 #define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
153 #define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
154 #define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
155 #define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
156 #define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
157 #define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among
158 serial ports (ro) */
159 /* Defs for some of the generic I/O pins */
160 #define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0
161 mode sel */
162 #define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1
163 mode sel */
164 #define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2
165 mode sel */
166 #define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3
167 mode sel */
169 #define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling
170 uart 0 mode select */
171 #define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling
172 uart 1 mode select */
173 #define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling
174 uart 2 mode select */
175 #define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling
176 uart 3 mode select */
178 /* Bitmasks for serial RX status byte */
179 #define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */
180 #define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */
181 #define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */
182 #define IOC4_RXSB_BREAK 0x08 /* Break character */
183 #define IOC4_RXSB_CTS 0x10 /* State of CTS */
184 #define IOC4_RXSB_DCD 0x20 /* State of DCD */
185 #define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */
186 #define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR
187 * & BREAK valid */
189 /* Bitmasks for serial TX control byte */
190 #define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */
191 #define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */
192 #define IOC4_TXCB_VALID 0x40 /* Byte is valid */
193 #define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */
194 #define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */
196 /* Bitmasks for IOC4_SBBR_L */
197 #define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
199 /* Bitmasks for IOC4_SSCR_<3:0> */
200 #define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */
201 #define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
202 #define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
203 #define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */
204 #define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */
205 #define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */
206 #define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */
207 #define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */
208 #define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */
209 #define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */
210 #define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */
212 /* All producer/comsumer pointers are the same bitfield */
213 #define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */
214 #define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */
215 #define IOC4_PROD_CONS_PTR_OFF 3
217 /* Bitmasks for IOC4_SRCIR_<3:0> */
218 #define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */
220 /* Bitmasks for IOC4_SHADOW_<3:0> */
221 #define IOC4_SHADOW_DR 0x00000001 /* Data ready */
222 #define IOC4_SHADOW_OE 0x00000002 /* Overrun error */
223 #define IOC4_SHADOW_PE 0x00000004 /* Parity error */
224 #define IOC4_SHADOW_FE 0x00000008 /* Framing error */
225 #define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */
226 #define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */
227 #define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */
228 #define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */
229 #define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */
230 #define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */
231 #define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */
232 #define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */
233 #define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */
234 #define IOC4_SHADOW_RTS 0x02000000 /* Request to send */
235 #define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
236 #define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
237 #define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */
239 /* Bitmasks for IOC4_SRTR_<3:0> */
240 #define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */
241 #define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */
242 #define IOC4_SRTR_CNT_VAL_SHIFT 16
243 #define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */
245 /* Serial port register map used for DMA and PIO serial I/O */
246 struct ioc4_serialregs {
247 uint32_t sscr;
248 uint32_t stpir;
249 uint32_t stcir;
250 uint32_t srpir;
251 uint32_t srcir;
252 uint32_t srtr;
253 uint32_t shadow;
256 /* IOC4 UART register map */
257 struct ioc4_uartregs {
258 char i4u_lcr;
259 union {
260 char iir; /* read only */
261 char fcr; /* write only */
262 } u3;
263 union {
264 char ier; /* DLAB == 0 */
265 char dlm; /* DLAB == 1 */
266 } u2;
267 union {
268 char rbr; /* read only, DLAB == 0 */
269 char thr; /* write only, DLAB == 0 */
270 char dll; /* DLAB == 1 */
271 } u1;
272 char i4u_scr;
273 char i4u_msr;
274 char i4u_lsr;
275 char i4u_mcr;
278 /* short names */
279 #define i4u_dll u1.dll
280 #define i4u_ier u2.ier
281 #define i4u_dlm u2.dlm
282 #define i4u_fcr u3.fcr
284 /* Serial port registers used for DMA serial I/O */
285 struct ioc4_serial {
286 uint32_t sbbr01_l;
287 uint32_t sbbr01_h;
288 uint32_t sbbr23_l;
289 uint32_t sbbr23_h;
291 struct ioc4_serialregs port_0;
292 struct ioc4_serialregs port_1;
293 struct ioc4_serialregs port_2;
294 struct ioc4_serialregs port_3;
295 struct ioc4_uartregs uart_0;
296 struct ioc4_uartregs uart_1;
297 struct ioc4_uartregs uart_2;
298 struct ioc4_uartregs uart_3;
299 } ioc4_serial;
301 /* UART clock speed */
302 #define IOC4_SER_XIN_CLK_66 66666667
303 #define IOC4_SER_XIN_CLK_33 33333333
305 #define IOC4_W_IES 0
306 #define IOC4_W_IEC 1
308 typedef void ioc4_intr_func_f(void *, uint32_t);
309 typedef ioc4_intr_func_f *ioc4_intr_func_t;
311 static unsigned int Num_of_ioc4_cards;
313 /* defining this will get you LOTS of great debug info */
314 //#define DEBUG_INTERRUPTS
315 #define DPRINT_CONFIG(_x...) ;
316 //#define DPRINT_CONFIG(_x...) printk _x
318 /* number of characters left in xmit buffer before we ask for more */
319 #define WAKEUP_CHARS 256
321 /* number of characters we want to transmit to the lower level at a time */
322 #define IOC4_MAX_CHARS 256
323 #define IOC4_FIFO_CHARS 255
325 /* Device name we're using */
326 #define DEVICE_NAME "ttyIOC"
327 #define DEVICE_MAJOR 204
328 #define DEVICE_MINOR 50
330 /* register offsets */
331 #define IOC4_SERIAL_OFFSET 0x300
333 /* flags for next_char_state */
334 #define NCS_BREAK 0x1
335 #define NCS_PARITY 0x2
336 #define NCS_FRAMING 0x4
337 #define NCS_OVERRUN 0x8
339 /* cause we need SOME parameters ... */
340 #define MIN_BAUD_SUPPORTED 1200
341 #define MAX_BAUD_SUPPORTED 115200
343 /* protocol types supported */
344 enum sio_proto {
345 PROTO_RS232,
346 PROTO_RS422
349 /* Notification types */
350 #define N_DATA_READY 0x01
351 #define N_OUTPUT_LOWAT 0x02
352 #define N_BREAK 0x04
353 #define N_PARITY_ERROR 0x08
354 #define N_FRAMING_ERROR 0x10
355 #define N_OVERRUN_ERROR 0x20
356 #define N_DDCD 0x40
357 #define N_DCTS 0x80
359 #define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
360 N_PARITY_ERROR | N_FRAMING_ERROR | \
361 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
363 #define N_ALL_OUTPUT N_OUTPUT_LOWAT
365 #define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
367 #define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
368 N_PARITY_ERROR | N_FRAMING_ERROR | \
369 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
371 #define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
372 #define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
374 /* Some masks */
375 #define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
376 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
377 #define LCR_MASK_STOP_BITS (UART_LCR_STOP)
379 #define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
380 #define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
382 /* Default to 4k buffers */
383 #ifdef IOC4_1K_BUFFERS
384 #define RING_BUF_SIZE 1024
385 #define IOC4_BUF_SIZE_BIT 0
386 #define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
387 #else
388 #define RING_BUF_SIZE 4096
389 #define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
390 #define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
391 #endif
393 #define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
396 * This is the entry saved by the driver - one per card
398 struct ioc4_control {
399 int ic_irq;
400 struct {
401 /* uart ports are allocated here */
402 struct uart_port icp_uart_port;
403 /* Handy reference material */
404 struct ioc4_port *icp_port;
405 } ic_port[IOC4_NUM_SERIAL_PORTS];
406 struct ioc4_soft *ic_soft;
410 * per-IOC4 data structure
412 #define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
413 struct ioc4_soft {
414 struct ioc4_misc_regs __iomem *is_ioc4_misc_addr;
415 struct ioc4_serial __iomem *is_ioc4_serial_addr;
417 /* Each interrupt type has an entry in the array */
418 struct ioc4_intr_type {
421 * Each in-use entry in this array contains at least
422 * one nonzero bit in sd_bits; no two entries in this
423 * array have overlapping sd_bits values.
425 struct ioc4_intr_info {
426 uint32_t sd_bits;
427 ioc4_intr_func_f *sd_intr;
428 void *sd_info;
429 } is_intr_info[MAX_IOC4_INTR_ENTS];
431 /* Number of entries active in the above array */
432 atomic_t is_num_intrs;
433 } is_intr_type[IOC4_NUM_INTR_TYPES];
435 /* is_ir_lock must be held while
436 * modifying sio_ie values, so
437 * we can be sure that sio_ie is
438 * not changing when we read it
439 * along with sio_ir.
441 spinlock_t is_ir_lock; /* SIO_IE[SC] mod lock */
444 /* Local port info for each IOC4 serial ports */
445 struct ioc4_port {
446 struct uart_port *ip_port;
447 /* Back ptrs for this port */
448 struct ioc4_control *ip_control;
449 struct pci_dev *ip_pdev;
450 struct ioc4_soft *ip_ioc4_soft;
452 /* pci mem addresses */
453 struct ioc4_misc_regs __iomem *ip_mem;
454 struct ioc4_serial __iomem *ip_serial;
455 struct ioc4_serialregs __iomem *ip_serial_regs;
456 struct ioc4_uartregs __iomem *ip_uart_regs;
458 /* Ring buffer page for this port */
459 dma_addr_t ip_dma_ringbuf;
460 /* vaddr of ring buffer */
461 struct ring_buffer *ip_cpu_ringbuf;
463 /* Rings for this port */
464 struct ring *ip_inring;
465 struct ring *ip_outring;
467 /* Hook to port specific values */
468 struct hooks *ip_hooks;
470 spinlock_t ip_lock;
472 /* Various rx/tx parameters */
473 int ip_baud;
474 int ip_tx_lowat;
475 int ip_rx_timeout;
477 /* Copy of notification bits */
478 int ip_notify;
480 /* Shadow copies of various registers so we don't need to PIO
481 * read them constantly
483 uint32_t ip_ienb; /* Enabled interrupts */
484 uint32_t ip_sscr;
485 uint32_t ip_tx_prod;
486 uint32_t ip_rx_cons;
487 int ip_pci_bus_speed;
488 unsigned char ip_flags;
491 /* tx low water mark. We need to notify the driver whenever tx is getting
492 * close to empty so it can refill the tx buffer and keep things going.
493 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
494 * have no trouble getting in more chars in time (I certainly hope so).
496 #define TX_LOWAT_LATENCY 1000
497 #define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
498 #define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
500 /* Flags per port */
501 #define INPUT_HIGH 0x01
502 #define DCD_ON 0x02
503 #define LOWAT_WRITTEN 0x04
504 #define READ_ABORTED 0x08
506 /* Since each port has different register offsets and bitmasks
507 * for everything, we'll store those that we need in tables so we
508 * don't have to be constantly checking the port we are dealing with.
510 struct hooks {
511 uint32_t intr_delta_dcd;
512 uint32_t intr_delta_cts;
513 uint32_t intr_tx_mt;
514 uint32_t intr_rx_timer;
515 uint32_t intr_rx_high;
516 uint32_t intr_tx_explicit;
517 uint32_t intr_dma_error;
518 uint32_t intr_clear;
519 uint32_t intr_all;
520 int rs422_select_pin;
523 static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
524 /* Values for port 0 */
526 IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
527 IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
528 IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
529 IOC4_OTHER_IR_S0_MEMERR,
530 (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
531 IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
532 IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
533 IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
534 IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
537 /* Values for port 1 */
539 IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
540 IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
541 IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
542 IOC4_OTHER_IR_S1_MEMERR,
543 (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
544 IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
545 IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
546 IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
547 IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
550 /* Values for port 2 */
552 IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
553 IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
554 IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
555 IOC4_OTHER_IR_S2_MEMERR,
556 (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
557 IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
558 IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
559 IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
560 IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
563 /* Values for port 3 */
565 IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
566 IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
567 IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
568 IOC4_OTHER_IR_S3_MEMERR,
569 (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
570 IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
571 IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
572 IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
573 IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
577 /* A ring buffer entry */
578 struct ring_entry {
579 union {
580 struct {
581 uint32_t alldata;
582 uint32_t allsc;
583 } all;
584 struct {
585 char data[4]; /* data bytes */
586 char sc[4]; /* status/control */
587 } s;
588 } u;
591 /* Test the valid bits in any of the 4 sc chars using "allsc" member */
592 #define RING_ANY_VALID \
593 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
595 #define ring_sc u.s.sc
596 #define ring_data u.s.data
597 #define ring_allsc u.all.allsc
599 /* Number of entries per ring buffer. */
600 #define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
602 /* An individual ring */
603 struct ring {
604 struct ring_entry entries[ENTRIES_PER_RING];
607 /* The whole enchilada */
608 struct ring_buffer {
609 struct ring TX_0_OR_2;
610 struct ring RX_0_OR_2;
611 struct ring TX_1_OR_3;
612 struct ring RX_1_OR_3;
615 /* Get a ring from a port struct */
616 #define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
618 /* Infinite loop detection.
620 #define MAXITER 10000000
622 /* Prototypes */
623 static void receive_chars(struct uart_port *);
624 static void handle_intr(void *arg, uint32_t sio_ir);
627 * write_ireg - write the interrupt regs
628 * @ioc4_soft: ptr to soft struct for this port
629 * @val: value to write
630 * @which: which register
631 * @type: which ireg set
633 static inline void
634 write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
636 struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr;
637 unsigned long flags;
639 spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
641 switch (type) {
642 case IOC4_SIO_INTR_TYPE:
643 switch (which) {
644 case IOC4_W_IES:
645 writel(val, &mem->sio_ies.raw);
646 break;
648 case IOC4_W_IEC:
649 writel(val, &mem->sio_iec.raw);
650 break;
652 break;
654 case IOC4_OTHER_INTR_TYPE:
655 switch (which) {
656 case IOC4_W_IES:
657 writel(val, &mem->other_ies.raw);
658 break;
660 case IOC4_W_IEC:
661 writel(val, &mem->other_iec.raw);
662 break;
664 break;
666 default:
667 break;
669 spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
673 * set_baud - Baud rate setting code
674 * @port: port to set
675 * @baud: baud rate to use
677 static int set_baud(struct ioc4_port *port, int baud)
679 int actual_baud;
680 int diff;
681 int lcr;
682 unsigned short divisor;
683 struct ioc4_uartregs __iomem *uart;
685 divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
686 if (!divisor)
687 return 1;
688 actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
690 diff = actual_baud - baud;
691 if (diff < 0)
692 diff = -diff;
694 /* If we're within 1%, we've found a match */
695 if (diff * 100 > actual_baud)
696 return 1;
698 uart = port->ip_uart_regs;
699 lcr = readb(&uart->i4u_lcr);
700 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
701 writeb((unsigned char)divisor, &uart->i4u_dll);
702 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
703 writeb(lcr, &uart->i4u_lcr);
704 return 0;
709 * get_ioc4_port - given a uart port, return the control structure
710 * @port: uart port
712 static struct ioc4_port *get_ioc4_port(struct uart_port *the_port)
714 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
715 struct ioc4_control *control = idd->idd_serial_data;
716 int ii;
718 if (control) {
719 for ( ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++ ) {
720 if (!control->ic_port[ii].icp_port)
721 continue;
722 if (the_port == control->ic_port[ii].icp_port->ip_port)
723 return control->ic_port[ii].icp_port;
726 return NULL;
729 /* The IOC4 hardware provides no atomic way to determine if interrupts
730 * are pending since two reads are required to do so. The handler must
731 * read the SIO_IR and the SIO_IES, and take the logical and of the
732 * two. When this value is zero, all interrupts have been serviced and
733 * the handler may return.
735 * This has the unfortunate "hole" that, if some other CPU or
736 * some other thread or some higher level interrupt manages to
737 * modify SIO_IE between our reads of SIO_IR and SIO_IE, we may
738 * think we have observed SIO_IR&SIO_IE==0 when in fact this
739 * condition never really occurred.
741 * To solve this, we use a simple spinlock that must be held
742 * whenever modifying SIO_IE; holding this lock while observing
743 * both SIO_IR and SIO_IE guarantees that we do not falsely
744 * conclude that no enabled interrupts are pending.
747 static inline uint32_t
748 pending_intrs(struct ioc4_soft *soft, int type)
750 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
751 unsigned long flag;
752 uint32_t intrs = 0;
754 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
755 || (type == IOC4_OTHER_INTR_TYPE)));
757 spin_lock_irqsave(&soft->is_ir_lock, flag);
759 switch (type) {
760 case IOC4_SIO_INTR_TYPE:
761 intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw);
762 break;
764 case IOC4_OTHER_INTR_TYPE:
765 intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw);
767 /* Don't process any ATA interrupte */
768 intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
769 break;
771 default:
772 break;
774 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
775 return intrs;
779 * port_init - Initialize the sio and ioc4 hardware for a given port
780 * called per port from attach...
781 * @port: port to initialize
783 static int inline port_init(struct ioc4_port *port)
785 uint32_t sio_cr;
786 struct hooks *hooks = port->ip_hooks;
787 struct ioc4_uartregs __iomem *uart;
789 /* Idle the IOC4 serial interface */
790 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
792 /* Wait until any pending bus activity for this port has ceased */
794 sio_cr = readl(&port->ip_mem->sio_cr.raw);
795 while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
797 /* Finish reset sequence */
798 writel(0, &port->ip_serial_regs->sscr);
800 /* Once RESET is done, reload cached tx_prod and rx_cons values
801 * and set rings to empty by making prod == cons
803 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
804 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
805 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
806 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
808 /* Disable interrupts for this 16550 */
809 uart = port->ip_uart_regs;
810 writeb(0, &uart->i4u_lcr);
811 writeb(0, &uart->i4u_ier);
813 /* Set the default baud */
814 set_baud(port, port->ip_baud);
816 /* Set line control to 8 bits no parity */
817 writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
818 /* UART_LCR_STOP == 1 stop */
820 /* Enable the FIFOs */
821 writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
822 /* then reset 16550 FIFOs */
823 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
824 &uart->i4u_fcr);
826 /* Clear modem control register */
827 writeb(0, &uart->i4u_mcr);
829 /* Clear deltas in modem status register */
830 readb(&uart->i4u_msr);
832 /* Only do this once per port pair */
833 if (port->ip_hooks == &hooks_array[0]
834 || port->ip_hooks == &hooks_array[2]) {
835 unsigned long ring_pci_addr;
836 uint32_t __iomem *sbbr_l;
837 uint32_t __iomem *sbbr_h;
839 if (port->ip_hooks == &hooks_array[0]) {
840 sbbr_l = &port->ip_serial->sbbr01_l;
841 sbbr_h = &port->ip_serial->sbbr01_h;
842 } else {
843 sbbr_l = &port->ip_serial->sbbr23_l;
844 sbbr_h = &port->ip_serial->sbbr23_h;
847 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
848 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
849 __FUNCTION__, ring_pci_addr));
851 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
852 writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
855 /* Set the receive timeout value to 10 msec */
856 writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
858 /* Set rx threshold, enable DMA */
859 /* Set high water mark at 3/4 of full ring */
860 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
861 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
863 /* Disable and clear all serial related interrupt bits */
864 write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
865 IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
866 port->ip_ienb &= ~hooks->intr_clear;
867 writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw);
868 return 0;
872 * handle_dma_error_intr - service any pending DMA error interrupts for the
873 * given port - 2nd level called via sd_intr
874 * @arg: handler arg
875 * @other_ir: ioc4regs
877 static void handle_dma_error_intr(void *arg, uint32_t other_ir)
879 struct ioc4_port *port = (struct ioc4_port *)arg;
880 struct hooks *hooks = port->ip_hooks;
881 unsigned int flags;
883 spin_lock_irqsave(&port->ip_lock, flags);
885 /* ACK the interrupt */
886 writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw);
888 if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) {
889 printk(KERN_ERR
890 "PCI error address is 0x%lx, "
891 "master is serial port %c %s\n",
892 (((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
893 << 32)
894 | readl(&port->ip_mem->pci_err_addr_l.raw))
895 & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
896 ((char)(readl(&port->ip_mem->pci_err_addr_l.raw) &
897 IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
898 (readl(&port->ip_mem->pci_err_addr_l.raw)
899 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
900 ? "RX" : "TX");
902 if (readl(&port->ip_mem->pci_err_addr_l.raw)
903 & IOC4_PCI_ERR_ADDR_MUL_ERR) {
904 printk(KERN_ERR
905 "Multiple errors occurred\n");
908 spin_unlock_irqrestore(&port->ip_lock, flags);
910 /* Re-enable DMA error interrupts */
911 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
912 IOC4_OTHER_INTR_TYPE);
916 * intr_connect - interrupt connect function
917 * @soft: soft struct for this card
918 * @type: interrupt type
919 * @intrbits: bit pattern to set
920 * @intr: handler function
921 * @info: handler arg
923 static void
924 intr_connect(struct ioc4_soft *soft, int type,
925 uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
927 int i;
928 struct ioc4_intr_info *intr_ptr;
930 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
931 || (type == IOC4_OTHER_INTR_TYPE)));
933 i = atomic_inc(&soft-> is_intr_type[type].is_num_intrs) - 1;
934 BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
936 /* Save off the lower level interrupt handler */
937 intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
938 intr_ptr->sd_bits = intrbits;
939 intr_ptr->sd_intr = intr;
940 intr_ptr->sd_info = info;
944 * ioc4_intr - Top level IOC4 interrupt handler.
945 * @irq: irq value
946 * @arg: handler arg
947 * @regs: registers
949 static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
951 struct ioc4_soft *soft;
952 uint32_t this_ir, this_mir;
953 int xx, num_intrs = 0;
954 int intr_type;
955 int handled = 0;
956 struct ioc4_intr_info *ii;
958 soft = arg;
959 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
960 num_intrs = (int)atomic_read(
961 &soft->is_intr_type[intr_type].is_num_intrs);
963 this_mir = this_ir = pending_intrs(soft, intr_type);
965 /* Farm out the interrupt to the various drivers depending on
966 * which interrupt bits are set.
968 for (xx = 0; xx < num_intrs; xx++) {
969 ii = &soft->is_intr_type[intr_type].is_intr_info[xx];
970 if ((this_mir = this_ir & ii->sd_bits)) {
971 /* Disable owned interrupts, call handler */
972 handled++;
973 write_ireg(soft, ii->sd_bits, IOC4_W_IEC,
974 intr_type);
975 ii->sd_intr(ii->sd_info, this_mir);
976 this_ir &= ~this_mir;
980 #ifdef DEBUG_INTERRUPTS
982 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
983 spinlock_t *lp = &soft->is_ir_lock;
984 unsigned long flag;
986 spin_lock_irqsave(&soft->is_ir_lock, flag);
987 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
988 "other_ir 0x%x other_ies 0x%x mask 0x%x\n",
989 __FUNCTION__, __LINE__,
990 (void *)mem, readl(&mem->sio_ir.raw),
991 readl(&mem->sio_ies.raw),
992 readl(&mem->other_ir.raw),
993 readl(&mem->other_ies.raw),
994 IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
995 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
997 #endif
998 return handled ? IRQ_HANDLED : IRQ_NONE;
1002 * ioc4_attach_local - Device initialization.
1003 * Called at *_attach() time for each
1004 * IOC4 with serial ports in the system.
1005 * @idd: Master module data for this IOC4
1007 static int inline ioc4_attach_local(struct ioc4_driver_data *idd)
1009 struct ioc4_port *port;
1010 struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1011 int port_number;
1012 uint16_t ioc4_revid_min = 62;
1013 uint16_t ioc4_revid;
1014 struct pci_dev *pdev = idd->idd_pdev;
1015 struct ioc4_control* control = idd->idd_serial_data;
1016 struct ioc4_soft *soft = control->ic_soft;
1017 void __iomem *ioc4_misc = idd->idd_misc_regs;
1018 void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
1020 /* IOC4 firmware must be at least rev 62 */
1021 pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1023 printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1024 if (ioc4_revid < ioc4_revid_min) {
1025 printk(KERN_WARNING
1026 "IOC4 serial not supported on firmware rev %d, "
1027 "please upgrade to rev %d or higher\n",
1028 ioc4_revid, ioc4_revid_min);
1029 return -EPERM;
1031 BUG_ON(ioc4_misc == NULL);
1032 BUG_ON(ioc4_serial == NULL);
1034 /* Create port structures for each port */
1035 for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1036 port_number++) {
1037 port = kmalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1038 if (!port) {
1039 printk(KERN_WARNING
1040 "IOC4 serial memory not available for port\n");
1041 return -ENOMEM;
1043 memset(port, 0, sizeof(struct ioc4_port));
1044 spin_lock_init(&port->ip_lock);
1046 /* we need to remember the previous ones, to point back to
1047 * them farther down - setting up the ring buffers.
1049 ports[port_number] = port;
1051 /* Allocate buffers and jumpstart the hardware. */
1052 control->ic_port[port_number].icp_port = port;
1053 port->ip_ioc4_soft = soft;
1054 port->ip_pdev = pdev;
1055 port->ip_ienb = 0;
1056 /* Use baud rate calculations based on detected PCI
1057 * bus speed. Simply test whether the PCI clock is
1058 * running closer to 66MHz or 33MHz.
1060 if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
1061 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
1062 } else {
1063 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
1065 port->ip_baud = 9600;
1066 port->ip_control = control;
1067 port->ip_mem = ioc4_misc;
1068 port->ip_serial = ioc4_serial;
1070 /* point to the right hook */
1071 port->ip_hooks = &hooks_array[port_number];
1073 /* Get direct hooks to the serial regs and uart regs
1074 * for this port
1076 switch (port_number) {
1077 case 0:
1078 port->ip_serial_regs = &(port->ip_serial->port_0);
1079 port->ip_uart_regs = &(port->ip_serial->uart_0);
1080 break;
1081 case 1:
1082 port->ip_serial_regs = &(port->ip_serial->port_1);
1083 port->ip_uart_regs = &(port->ip_serial->uart_1);
1084 break;
1085 case 2:
1086 port->ip_serial_regs = &(port->ip_serial->port_2);
1087 port->ip_uart_regs = &(port->ip_serial->uart_2);
1088 break;
1089 default:
1090 case 3:
1091 port->ip_serial_regs = &(port->ip_serial->port_3);
1092 port->ip_uart_regs = &(port->ip_serial->uart_3);
1093 break;
1096 /* ring buffers are 1 to a pair of ports */
1097 if (port_number && (port_number & 1)) {
1098 /* odd use the evens buffer */
1099 port->ip_dma_ringbuf =
1100 ports[port_number - 1]->ip_dma_ringbuf;
1101 port->ip_cpu_ringbuf =
1102 ports[port_number - 1]->ip_cpu_ringbuf;
1103 port->ip_inring = RING(port, RX_1_OR_3);
1104 port->ip_outring = RING(port, TX_1_OR_3);
1106 } else {
1107 if (port->ip_dma_ringbuf == 0) {
1108 port->ip_cpu_ringbuf = pci_alloc_consistent
1109 (pdev, TOTAL_RING_BUF_SIZE,
1110 &port->ip_dma_ringbuf);
1113 BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1114 (TOTAL_RING_BUF_SIZE - 1)) == 0));
1115 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1116 "ip_dma_ringbuf 0x%p\n",
1117 __FUNCTION__,
1118 (void *)port->ip_cpu_ringbuf,
1119 (void *)port->ip_dma_ringbuf));
1120 port->ip_inring = RING(port, RX_0_OR_2);
1121 port->ip_outring = RING(port, TX_0_OR_2);
1123 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1124 __FUNCTION__,
1125 port_number, (void *)port, (void *)control));
1126 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1127 (void *)port->ip_serial_regs,
1128 (void *)port->ip_uart_regs));
1130 /* Initialize the hardware for IOC4 */
1131 port_init(port);
1133 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1134 "outring 0x%p\n",
1135 __FUNCTION__,
1136 port_number, (void *)port,
1137 (void *)port->ip_inring,
1138 (void *)port->ip_outring));
1140 /* Attach interrupt handlers */
1141 intr_connect(soft, IOC4_SIO_INTR_TYPE,
1142 GET_SIO_IR(port_number),
1143 handle_intr, port);
1145 intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1146 GET_OTHER_IR(port_number),
1147 handle_dma_error_intr, port);
1149 return 0;
1153 * enable_intrs - enable interrupts
1154 * @port: port to enable
1155 * @mask: mask to use
1157 static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1159 struct hooks *hooks = port->ip_hooks;
1161 if ((port->ip_ienb & mask) != mask) {
1162 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1163 IOC4_SIO_INTR_TYPE);
1164 port->ip_ienb |= mask;
1167 if (port->ip_ienb)
1168 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1169 IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1173 * local_open - local open a port
1174 * @port: port to open
1176 static inline int local_open(struct ioc4_port *port)
1178 int spiniter = 0;
1180 port->ip_flags = 0;
1182 /* Pause the DMA interface if necessary */
1183 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1184 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1185 &port->ip_serial_regs->sscr);
1186 while((readl(&port->ip_serial_regs-> sscr)
1187 & IOC4_SSCR_PAUSE_STATE) == 0) {
1188 spiniter++;
1189 if (spiniter > MAXITER) {
1190 return -1;
1195 /* Reset the input fifo. If the uart received chars while the port
1196 * was closed and DMA is not enabled, the uart may have a bunch of
1197 * chars hanging around in its rx fifo which will not be discarded
1198 * by rclr in the upper layer. We must get rid of them here.
1200 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1201 &port->ip_uart_regs->i4u_fcr);
1203 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1204 /* UART_LCR_STOP == 1 stop */
1206 /* Re-enable DMA, set default threshold to intr whenever there is
1207 * data available.
1209 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1210 port->ip_sscr |= 1; /* default threshold */
1212 /* Plug in the new sscr. This implicitly clears the DMA_PAUSE
1213 * flag if it was set above
1215 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1216 port->ip_tx_lowat = 1;
1217 return 0;
1221 * set_rx_timeout - Set rx timeout and threshold values.
1222 * @port: port to use
1223 * @timeout: timeout value in ticks
1225 static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1227 int threshold;
1229 port->ip_rx_timeout = timeout;
1231 /* Timeout is in ticks. Let's figure out how many chars we
1232 * can receive at the current baud rate in that interval
1233 * and set the rx threshold to that amount. There are 4 chars
1234 * per ring entry, so we'll divide the number of chars that will
1235 * arrive in timeout by 4.
1236 * So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
1238 threshold = timeout * port->ip_baud / 4000;
1239 if (threshold == 0)
1240 threshold = 1; /* otherwise we'll intr all the time! */
1242 if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1243 return 1;
1245 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1246 port->ip_sscr |= threshold;
1248 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1250 /* Now set the rx timeout to the given value
1251 * again timeout * IOC4_SRTR_HZ / HZ
1253 timeout = timeout * IOC4_SRTR_HZ / 100;
1254 if (timeout > IOC4_SRTR_CNT)
1255 timeout = IOC4_SRTR_CNT;
1257 writel(timeout, &port->ip_serial_regs->srtr);
1258 return 0;
1262 * config_port - config the hardware
1263 * @port: port to config
1264 * @baud: baud rate for the port
1265 * @byte_size: data size
1266 * @stop_bits: number of stop bits
1267 * @parenb: parity enable ?
1268 * @parodd: odd parity ?
1270 static inline int
1271 config_port(struct ioc4_port *port,
1272 int baud, int byte_size, int stop_bits, int parenb, int parodd)
1274 char lcr, sizebits;
1275 int spiniter = 0;
1277 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1278 __FUNCTION__, baud, byte_size, stop_bits, parenb, parodd));
1280 if (set_baud(port, baud))
1281 return 1;
1283 switch (byte_size) {
1284 case 5:
1285 sizebits = UART_LCR_WLEN5;
1286 break;
1287 case 6:
1288 sizebits = UART_LCR_WLEN6;
1289 break;
1290 case 7:
1291 sizebits = UART_LCR_WLEN7;
1292 break;
1293 case 8:
1294 sizebits = UART_LCR_WLEN8;
1295 break;
1296 default:
1297 return 1;
1300 /* Pause the DMA interface if necessary */
1301 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1302 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1303 &port->ip_serial_regs->sscr);
1304 while((readl(&port->ip_serial_regs->sscr)
1305 & IOC4_SSCR_PAUSE_STATE) == 0) {
1306 spiniter++;
1307 if (spiniter > MAXITER)
1308 return -1;
1312 /* Clear relevant fields in lcr */
1313 lcr = readb(&port->ip_uart_regs->i4u_lcr);
1314 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1315 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1317 /* Set byte size in lcr */
1318 lcr |= sizebits;
1320 /* Set parity */
1321 if (parenb) {
1322 lcr |= UART_LCR_PARITY;
1323 if (!parodd)
1324 lcr |= UART_LCR_EPAR;
1327 /* Set stop bits */
1328 if (stop_bits)
1329 lcr |= UART_LCR_STOP /* 2 stop bits */ ;
1331 writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1333 /* Re-enable the DMA interface if necessary */
1334 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1335 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1337 port->ip_baud = baud;
1339 /* When we get within this number of ring entries of filling the
1340 * entire ring on tx, place an EXPLICIT intr to generate a lowat
1341 * notification when output has drained.
1343 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1344 if (port->ip_tx_lowat == 0)
1345 port->ip_tx_lowat = 1;
1347 set_rx_timeout(port, 2);
1349 return 0;
1353 * do_write - Write bytes to the port. Returns the number of bytes
1354 * actually written. Called from transmit_chars
1355 * @port: port to use
1356 * @buf: the stuff to write
1357 * @len: how many bytes in 'buf'
1359 static inline int do_write(struct ioc4_port *port, char *buf, int len)
1361 int prod_ptr, cons_ptr, total = 0;
1362 struct ring *outring;
1363 struct ring_entry *entry;
1364 struct hooks *hooks = port->ip_hooks;
1366 BUG_ON(!(len >= 0));
1368 prod_ptr = port->ip_tx_prod;
1369 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1370 outring = port->ip_outring;
1372 /* Maintain a 1-entry red-zone. The ring buffer is full when
1373 * (cons - prod) % ring_size is 1. Rather than do this subtraction
1374 * in the body of the loop, I'll do it now.
1376 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1378 /* Stuff the bytes into the output */
1379 while ((prod_ptr != cons_ptr) && (len > 0)) {
1380 int xx;
1382 /* Get 4 bytes (one ring entry) at a time */
1383 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1385 /* Invalidate all entries */
1386 entry->ring_allsc = 0;
1388 /* Copy in some bytes */
1389 for (xx = 0; (xx < 4) && (len > 0); xx++) {
1390 entry->ring_data[xx] = *buf++;
1391 entry->ring_sc[xx] = IOC4_TXCB_VALID;
1392 len--;
1393 total++;
1396 /* If we are within some small threshold of filling up the
1397 * entire ring buffer, we must place an EXPLICIT intr here
1398 * to generate a lowat interrupt in case we subsequently
1399 * really do fill up the ring and the caller goes to sleep.
1400 * No need to place more than one though.
1402 if (!(port->ip_flags & LOWAT_WRITTEN) &&
1403 ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1404 <= port->ip_tx_lowat
1405 * (int)sizeof(struct ring_entry)) {
1406 port->ip_flags |= LOWAT_WRITTEN;
1407 entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1410 /* Go on to next entry */
1411 prod_ptr += sizeof(struct ring_entry);
1412 prod_ptr &= PROD_CONS_MASK;
1415 /* If we sent something, start DMA if necessary */
1416 if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1417 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1418 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1421 /* Store the new producer pointer. If tx is disabled, we stuff the
1422 * data into the ring buffer, but we don't actually start tx.
1424 if (!uart_tx_stopped(port->ip_port)) {
1425 writel(prod_ptr, &port->ip_serial_regs->stpir);
1427 /* If we are now transmitting, enable tx_mt interrupt so we
1428 * can disable DMA if necessary when the tx finishes.
1430 if (total > 0)
1431 enable_intrs(port, hooks->intr_tx_mt);
1433 port->ip_tx_prod = prod_ptr;
1434 return total;
1438 * disable_intrs - disable interrupts
1439 * @port: port to enable
1440 * @mask: mask to use
1442 static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1444 struct hooks *hooks = port->ip_hooks;
1446 if (port->ip_ienb & mask) {
1447 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1448 IOC4_SIO_INTR_TYPE);
1449 port->ip_ienb &= ~mask;
1452 if (!port->ip_ienb)
1453 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1454 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1458 * set_notification - Modify event notification
1459 * @port: port to use
1460 * @mask: events mask
1461 * @set_on: set ?
1463 static int set_notification(struct ioc4_port *port, int mask, int set_on)
1465 struct hooks *hooks = port->ip_hooks;
1466 uint32_t intrbits, sscrbits;
1468 BUG_ON(!mask);
1470 intrbits = sscrbits = 0;
1472 if (mask & N_DATA_READY)
1473 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1474 if (mask & N_OUTPUT_LOWAT)
1475 intrbits |= hooks->intr_tx_explicit;
1476 if (mask & N_DDCD) {
1477 intrbits |= hooks->intr_delta_dcd;
1478 sscrbits |= IOC4_SSCR_RX_RING_DCD;
1480 if (mask & N_DCTS)
1481 intrbits |= hooks->intr_delta_cts;
1483 if (set_on) {
1484 enable_intrs(port, intrbits);
1485 port->ip_notify |= mask;
1486 port->ip_sscr |= sscrbits;
1487 } else {
1488 disable_intrs(port, intrbits);
1489 port->ip_notify &= ~mask;
1490 port->ip_sscr &= ~sscrbits;
1493 /* We require DMA if either DATA_READY or DDCD notification is
1494 * currently requested. If neither of these is requested and
1495 * there is currently no tx in progress, DMA may be disabled.
1497 if (port->ip_notify & (N_DATA_READY | N_DDCD))
1498 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1499 else if (!(port->ip_ienb & hooks->intr_tx_mt))
1500 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1502 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1503 return 0;
1507 * set_mcr - set the master control reg
1508 * @the_port: port to use
1509 * @set: set ?
1510 * @mask1: mcr mask
1511 * @mask2: shadow mask
1513 static inline int set_mcr(struct uart_port *the_port, int set,
1514 int mask1, int mask2)
1516 struct ioc4_port *port = get_ioc4_port(the_port);
1517 uint32_t shadow;
1518 int spiniter = 0;
1519 char mcr;
1521 if (!port)
1522 return -1;
1524 /* Pause the DMA interface if necessary */
1525 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1526 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1527 &port->ip_serial_regs->sscr);
1528 while ((readl(&port->ip_serial_regs->sscr)
1529 & IOC4_SSCR_PAUSE_STATE) == 0) {
1530 spiniter++;
1531 if (spiniter > MAXITER)
1532 return -1;
1535 shadow = readl(&port->ip_serial_regs->shadow);
1536 mcr = (shadow & 0xff000000) >> 24;
1538 /* Set new value */
1539 if (set) {
1540 mcr |= mask1;
1541 shadow |= mask2;
1542 } else {
1543 mcr &= ~mask1;
1544 shadow &= ~mask2;
1546 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1547 writel(shadow, &port->ip_serial_regs->shadow);
1549 /* Re-enable the DMA interface if necessary */
1550 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1551 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1553 return 0;
1557 * ioc4_set_proto - set the protocol for the port
1558 * @port: port to use
1559 * @proto: protocol to use
1561 static int ioc4_set_proto(struct ioc4_port *port, enum sio_proto proto)
1563 struct hooks *hooks = port->ip_hooks;
1565 switch (proto) {
1566 case PROTO_RS232:
1567 /* Clear the appropriate GIO pin */
1568 writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1569 break;
1571 case PROTO_RS422:
1572 /* Set the appropriate GIO pin */
1573 writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1574 break;
1576 default:
1577 return 1;
1579 return 0;
1583 * transmit_chars - upper level write, called with ip_lock
1584 * @the_port: port to write
1586 static void transmit_chars(struct uart_port *the_port)
1588 int xmit_count, tail, head;
1589 int result;
1590 char *start;
1591 struct tty_struct *tty;
1592 struct ioc4_port *port = get_ioc4_port(the_port);
1593 struct uart_info *info;
1595 if (!the_port)
1596 return;
1597 if (!port)
1598 return;
1600 info = the_port->info;
1601 tty = info->tty;
1603 if (uart_circ_empty(&info->xmit) || uart_tx_stopped(the_port)) {
1604 /* Nothing to do or hw stopped */
1605 set_notification(port, N_ALL_OUTPUT, 0);
1606 return;
1609 head = info->xmit.head;
1610 tail = info->xmit.tail;
1611 start = (char *)&info->xmit.buf[tail];
1613 /* write out all the data or until the end of the buffer */
1614 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1615 if (xmit_count > 0) {
1616 result = do_write(port, start, xmit_count);
1617 if (result > 0) {
1618 /* booking */
1619 xmit_count -= result;
1620 the_port->icount.tx += result;
1621 /* advance the pointers */
1622 tail += result;
1623 tail &= UART_XMIT_SIZE - 1;
1624 info->xmit.tail = tail;
1625 start = (char *)&info->xmit.buf[tail];
1628 if (uart_circ_chars_pending(&info->xmit) < WAKEUP_CHARS)
1629 uart_write_wakeup(the_port);
1631 if (uart_circ_empty(&info->xmit)) {
1632 set_notification(port, N_OUTPUT_LOWAT, 0);
1633 } else {
1634 set_notification(port, N_OUTPUT_LOWAT, 1);
1639 * ioc4_change_speed - change the speed of the port
1640 * @the_port: port to change
1641 * @new_termios: new termios settings
1642 * @old_termios: old termios settings
1644 static void
1645 ioc4_change_speed(struct uart_port *the_port,
1646 struct termios *new_termios, struct termios *old_termios)
1648 struct ioc4_port *port = get_ioc4_port(the_port);
1649 int baud, bits;
1650 unsigned cflag;
1651 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1652 struct uart_info *info = the_port->info;
1654 cflag = new_termios->c_cflag;
1656 switch (cflag & CSIZE) {
1657 case CS5:
1658 new_data = 5;
1659 bits = 7;
1660 break;
1661 case CS6:
1662 new_data = 6;
1663 bits = 8;
1664 break;
1665 case CS7:
1666 new_data = 7;
1667 bits = 9;
1668 break;
1669 case CS8:
1670 new_data = 8;
1671 bits = 10;
1672 break;
1673 default:
1674 /* cuz we always need a default ... */
1675 new_data = 5;
1676 bits = 7;
1677 break;
1679 if (cflag & CSTOPB) {
1680 bits++;
1681 new_stop = 1;
1683 if (cflag & PARENB) {
1684 bits++;
1685 new_parity_enable = 1;
1686 if (cflag & PARODD)
1687 new_parity = 1;
1689 baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1690 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1691 DPRINT_CONFIG(("%s: returned baud %d\n", __FUNCTION__, baud));
1693 /* default is 9600 */
1694 if (!baud)
1695 baud = 9600;
1697 if (!the_port->fifosize)
1698 the_port->fifosize = IOC4_FIFO_CHARS;
1699 the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1700 the_port->timeout += HZ / 50; /* Add .02 seconds of slop */
1702 the_port->ignore_status_mask = N_ALL_INPUT;
1704 info->tty->low_latency = 1;
1706 if (I_IGNPAR(info->tty))
1707 the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1708 | N_FRAMING_ERROR);
1709 if (I_IGNBRK(info->tty)) {
1710 the_port->ignore_status_mask &= ~N_BREAK;
1711 if (I_IGNPAR(info->tty))
1712 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1714 if (!(cflag & CREAD)) {
1715 /* ignore everything */
1716 the_port->ignore_status_mask &= ~N_DATA_READY;
1719 if (cflag & CRTSCTS) {
1720 port->ip_sscr |= IOC4_SSCR_HFC_EN;
1722 else {
1723 port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1725 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1727 /* Set the configuration and proper notification call */
1728 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1729 "config_port(baud %d data %d stop %d p enable %d parity %d),"
1730 " notification 0x%x\n",
1731 __FUNCTION__, (void *)port, cflag, baud, new_data, new_stop,
1732 new_parity_enable, new_parity, the_port->ignore_status_mask));
1734 if ((config_port(port, baud, /* baud */
1735 new_data, /* byte size */
1736 new_stop, /* stop bits */
1737 new_parity_enable, /* set parity */
1738 new_parity)) >= 0) { /* parity 1==odd */
1739 set_notification(port, the_port->ignore_status_mask, 1);
1744 * ic4_startup_local - Start up the serial port - returns >= 0 if no errors
1745 * @the_port: Port to operate on
1747 static inline int ic4_startup_local(struct uart_port *the_port)
1749 struct ioc4_port *port;
1750 struct uart_info *info;
1752 if (!the_port)
1753 return -1;
1755 port = get_ioc4_port(the_port);
1756 if (!port)
1757 return -1;
1759 info = the_port->info;
1761 local_open(port);
1763 /* set the speed of the serial port */
1764 ioc4_change_speed(the_port, info->tty->termios, (struct termios *)0);
1766 return 0;
1770 * ioc4_cb_output_lowat - called when the output low water mark is hit
1771 * @port: port to output
1773 static void ioc4_cb_output_lowat(struct ioc4_port *port)
1775 unsigned long pflags;
1777 /* ip_lock is set on the call here */
1778 if (port->ip_port) {
1779 spin_lock_irqsave(&port->ip_port->lock, pflags);
1780 transmit_chars(port->ip_port);
1781 spin_unlock_irqrestore(&port->ip_port->lock, pflags);
1786 * handle_intr - service any interrupts for the given port - 2nd level
1787 * called via sd_intr
1788 * @arg: handler arg
1789 * @sio_ir: ioc4regs
1791 static void handle_intr(void *arg, uint32_t sio_ir)
1793 struct ioc4_port *port = (struct ioc4_port *)arg;
1794 struct hooks *hooks = port->ip_hooks;
1795 unsigned int rx_high_rd_aborted = 0;
1796 unsigned int flags;
1797 struct uart_port *the_port;
1798 int loop_counter;
1800 /* Possible race condition here: The tx_mt interrupt bit may be
1801 * cleared without the intervention of the interrupt handler,
1802 * e.g. by a write. If the top level interrupt handler reads a
1803 * tx_mt, then some other processor does a write, starting up
1804 * output, then we come in here, see the tx_mt and stop DMA, the
1805 * output started by the other processor will hang. Thus we can
1806 * only rely on tx_mt being legitimate if it is read while the
1807 * port lock is held. Therefore this bit must be ignored in the
1808 * passed in interrupt mask which was read by the top level
1809 * interrupt handler since the port lock was not held at the time
1810 * it was read. We can only rely on this bit being accurate if it
1811 * is read while the port lock is held. So we'll clear it for now,
1812 * and reload it later once we have the port lock.
1814 sio_ir &= ~(hooks->intr_tx_mt);
1816 spin_lock_irqsave(&port->ip_lock, flags);
1818 loop_counter = MAXITER; /* to avoid hangs */
1820 do {
1821 uint32_t shadow;
1823 if ( loop_counter-- <= 0 ) {
1824 printk(KERN_WARNING "IOC4 serial: "
1825 "possible hang condition/"
1826 "port stuck on interrupt.\n");
1827 break;
1830 /* Handle a DCD change */
1831 if (sio_ir & hooks->intr_delta_dcd) {
1832 /* ACK the interrupt */
1833 writel(hooks->intr_delta_dcd,
1834 &port->ip_mem->sio_ir.raw);
1836 shadow = readl(&port->ip_serial_regs->shadow);
1838 if ((port->ip_notify & N_DDCD)
1839 && (shadow & IOC4_SHADOW_DCD)
1840 && (port->ip_port)) {
1841 the_port = port->ip_port;
1842 the_port->icount.dcd = 1;
1843 wake_up_interruptible
1844 (&the_port-> info->delta_msr_wait);
1845 } else if ((port->ip_notify & N_DDCD)
1846 && !(shadow & IOC4_SHADOW_DCD)) {
1847 /* Flag delta DCD/no DCD */
1848 port->ip_flags |= DCD_ON;
1852 /* Handle a CTS change */
1853 if (sio_ir & hooks->intr_delta_cts) {
1854 /* ACK the interrupt */
1855 writel(hooks->intr_delta_cts,
1856 &port->ip_mem->sio_ir.raw);
1858 shadow = readl(&port->ip_serial_regs->shadow);
1860 if ((port->ip_notify & N_DCTS)
1861 && (port->ip_port)) {
1862 the_port = port->ip_port;
1863 the_port->icount.cts =
1864 (shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1865 wake_up_interruptible
1866 (&the_port->info->delta_msr_wait);
1870 /* rx timeout interrupt. Must be some data available. Put this
1871 * before the check for rx_high since servicing this condition
1872 * may cause that condition to clear.
1874 if (sio_ir & hooks->intr_rx_timer) {
1875 /* ACK the interrupt */
1876 writel(hooks->intr_rx_timer,
1877 &port->ip_mem->sio_ir.raw);
1879 if ((port->ip_notify & N_DATA_READY)
1880 && (port->ip_port)) {
1881 /* ip_lock is set on call here */
1882 receive_chars(port->ip_port);
1886 /* rx high interrupt. Must be after rx_timer. */
1887 else if (sio_ir & hooks->intr_rx_high) {
1888 /* Data available, notify upper layer */
1889 if ((port->ip_notify & N_DATA_READY)
1890 && port->ip_port) {
1891 /* ip_lock is set on call here */
1892 receive_chars(port->ip_port);
1895 /* We can't ACK this interrupt. If receive_chars didn't
1896 * cause the condition to clear, we'll have to disable
1897 * the interrupt until the data is drained.
1898 * If the read was aborted, don't disable the interrupt
1899 * as this may cause us to hang indefinitely. An
1900 * aborted read generally means that this interrupt
1901 * hasn't been delivered to the cpu yet anyway, even
1902 * though we see it as asserted when we read the sio_ir.
1904 if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1905 if ((port->ip_flags & READ_ABORTED) == 0) {
1906 port->ip_ienb &= ~hooks->intr_rx_high;
1907 port->ip_flags |= INPUT_HIGH;
1908 } else {
1909 rx_high_rd_aborted++;
1914 /* We got a low water interrupt: notify upper layer to
1915 * send more data. Must come before tx_mt since servicing
1916 * this condition may cause that condition to clear.
1918 if (sio_ir & hooks->intr_tx_explicit) {
1919 port->ip_flags &= ~LOWAT_WRITTEN;
1921 /* ACK the interrupt */
1922 writel(hooks->intr_tx_explicit,
1923 &port->ip_mem->sio_ir.raw);
1925 if (port->ip_notify & N_OUTPUT_LOWAT)
1926 ioc4_cb_output_lowat(port);
1929 /* Handle tx_mt. Must come after tx_explicit. */
1930 else if (sio_ir & hooks->intr_tx_mt) {
1931 /* If we are expecting a lowat notification
1932 * and we get to this point it probably means that for
1933 * some reason the tx_explicit didn't work as expected
1934 * (that can legitimately happen if the output buffer is
1935 * filled up in just the right way).
1936 * So send the notification now.
1938 if (port->ip_notify & N_OUTPUT_LOWAT) {
1939 ioc4_cb_output_lowat(port);
1941 /* We need to reload the sio_ir since the lowat
1942 * call may have caused another write to occur,
1943 * clearing the tx_mt condition.
1945 sio_ir = PENDING(port);
1948 /* If the tx_mt condition still persists even after the
1949 * lowat call, we've got some work to do.
1951 if (sio_ir & hooks->intr_tx_mt) {
1953 /* If we are not currently expecting DMA input,
1954 * and the transmitter has just gone idle,
1955 * there is no longer any reason for DMA, so
1956 * disable it.
1958 if (!(port->ip_notify
1959 & (N_DATA_READY | N_DDCD))) {
1960 BUG_ON(!(port->ip_sscr
1961 & IOC4_SSCR_DMA_EN));
1962 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1963 writel(port->ip_sscr,
1964 &port->ip_serial_regs->sscr);
1967 /* Prevent infinite tx_mt interrupt */
1968 port->ip_ienb &= ~hooks->intr_tx_mt;
1971 sio_ir = PENDING(port);
1973 /* if the read was aborted and only hooks->intr_rx_high,
1974 * clear hooks->intr_rx_high, so we do not loop forever.
1977 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
1978 sio_ir &= ~hooks->intr_rx_high;
1980 } while (sio_ir & hooks->intr_all);
1982 spin_unlock_irqrestore(&port->ip_lock, flags);
1984 /* Re-enable interrupts before returning from interrupt handler.
1985 * Getting interrupted here is okay. It'll just v() our semaphore, and
1986 * we'll come through the loop again.
1989 write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
1990 IOC4_SIO_INTR_TYPE);
1994 * ioc4_cb_post_ncs - called for some basic errors
1995 * @port: port to use
1996 * @ncs: event
1998 static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2000 struct uart_icount *icount;
2002 icount = &the_port->icount;
2004 if (ncs & NCS_BREAK)
2005 icount->brk++;
2006 if (ncs & NCS_FRAMING)
2007 icount->frame++;
2008 if (ncs & NCS_OVERRUN)
2009 icount->overrun++;
2010 if (ncs & NCS_PARITY)
2011 icount->parity++;
2015 * do_read - Read in bytes from the port. Return the number of bytes
2016 * actually read.
2017 * @the_port: port to use
2018 * @buf: place to put the stuff we read
2019 * @len: how big 'buf' is
2022 static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2023 int len)
2025 int prod_ptr, cons_ptr, total;
2026 struct ioc4_port *port = get_ioc4_port(the_port);
2027 struct ring *inring;
2028 struct ring_entry *entry;
2029 struct hooks *hooks = port->ip_hooks;
2030 int byte_num;
2031 char *sc;
2032 int loop_counter;
2034 BUG_ON(!(len >= 0));
2035 BUG_ON(!port);
2037 /* There is a nasty timing issue in the IOC4. When the rx_timer
2038 * expires or the rx_high condition arises, we take an interrupt.
2039 * At some point while servicing the interrupt, we read bytes from
2040 * the ring buffer and re-arm the rx_timer. However the rx_timer is
2041 * not started until the first byte is received *after* it is armed,
2042 * and any bytes pending in the rx construction buffers are not drained
2043 * to memory until either there are 4 bytes available or the rx_timer
2044 * expires. This leads to a potential situation where data is left
2045 * in the construction buffers forever - 1 to 3 bytes were received
2046 * after the interrupt was generated but before the rx_timer was
2047 * re-armed. At that point as long as no subsequent bytes are received
2048 * the timer will never be started and the bytes will remain in the
2049 * construction buffer forever. The solution is to execute a DRAIN
2050 * command after rearming the timer. This way any bytes received before
2051 * the DRAIN will be drained to memory, and any bytes received after
2052 * the DRAIN will start the TIMER and be drained when it expires.
2053 * Luckily, this only needs to be done when the DMA buffer is empty
2054 * since there is no requirement that this function return all
2055 * available data as long as it returns some.
2057 /* Re-arm the timer */
2058 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
2060 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2061 cons_ptr = port->ip_rx_cons;
2063 if (prod_ptr == cons_ptr) {
2064 int reset_dma = 0;
2066 /* Input buffer appears empty, do a flush. */
2068 /* DMA must be enabled for this to work. */
2069 if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2070 port->ip_sscr |= IOC4_SSCR_DMA_EN;
2071 reset_dma = 1;
2074 /* Potential race condition: we must reload the srpir after
2075 * issuing the drain command, otherwise we could think the rx
2076 * buffer is empty, then take a very long interrupt, and when
2077 * we come back it's full and we wait forever for the drain to
2078 * complete.
2080 writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2081 &port->ip_serial_regs->sscr);
2082 prod_ptr = readl(&port->ip_serial_regs->srpir)
2083 & PROD_CONS_MASK;
2085 /* We must not wait for the DRAIN to complete unless there are
2086 * at least 8 bytes (2 ring entries) available to receive the
2087 * data otherwise the DRAIN will never complete and we'll
2088 * deadlock here.
2089 * In fact, to make things easier, I'll just ignore the flush if
2090 * there is any data at all now available.
2092 if (prod_ptr == cons_ptr) {
2093 loop_counter = 0;
2094 while (readl(&port->ip_serial_regs->sscr) &
2095 IOC4_SSCR_RX_DRAIN) {
2096 loop_counter++;
2097 if (loop_counter > MAXITER)
2098 return -1;
2101 /* SIGH. We have to reload the prod_ptr *again* since
2102 * the drain may have caused it to change
2104 prod_ptr = readl(&port->ip_serial_regs->srpir)
2105 & PROD_CONS_MASK;
2107 if (reset_dma) {
2108 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2109 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2112 inring = port->ip_inring;
2113 port->ip_flags &= ~READ_ABORTED;
2115 total = 0;
2116 loop_counter = 0xfffff; /* to avoid hangs */
2118 /* Grab bytes from the hardware */
2119 while ((prod_ptr != cons_ptr) && (len > 0)) {
2120 entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2122 if ( loop_counter-- <= 0 ) {
2123 printk(KERN_WARNING "IOC4 serial: "
2124 "possible hang condition/"
2125 "port stuck on read.\n");
2126 break;
2129 /* According to the producer pointer, this ring entry
2130 * must contain some data. But if the PIO happened faster
2131 * than the DMA, the data may not be available yet, so let's
2132 * wait until it arrives.
2134 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2135 /* Indicate the read is aborted so we don't disable
2136 * the interrupt thinking that the consumer is
2137 * congested.
2139 port->ip_flags |= READ_ABORTED;
2140 len = 0;
2141 break;
2144 /* Load the bytes/status out of the ring entry */
2145 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2146 sc = &(entry->ring_sc[byte_num]);
2148 /* Check for change in modem state or overrun */
2149 if ((*sc & IOC4_RXSB_MODEM_VALID)
2150 && (port->ip_notify & N_DDCD)) {
2151 /* Notify upper layer if DCD dropped */
2153 if ((port->ip_flags & DCD_ON)
2154 && !(*sc & IOC4_RXSB_DCD)) {
2156 /* If we have already copied some data,
2157 * return it. We'll pick up the carrier
2158 * drop on the next pass. That way we
2159 * don't throw away the data that has
2160 * already been copied back to
2161 * the caller's buffer.
2163 if (total > 0) {
2164 len = 0;
2165 break;
2167 port->ip_flags &= ~DCD_ON;
2169 /* Turn off this notification so the
2170 * carrier drop protocol won't see it
2171 * again when it does a read.
2173 *sc &= ~IOC4_RXSB_MODEM_VALID;
2175 /* To keep things consistent, we need
2176 * to update the consumer pointer so
2177 * the next reader won't come in and
2178 * try to read the same ring entries
2179 * again. This must be done here before
2180 * the dcd change.
2183 if ((entry->ring_allsc & RING_ANY_VALID)
2184 == 0) {
2185 cons_ptr += (int)sizeof
2186 (struct ring_entry);
2187 cons_ptr &= PROD_CONS_MASK;
2189 writel(cons_ptr,
2190 &port->ip_serial_regs->srcir);
2191 port->ip_rx_cons = cons_ptr;
2193 /* Notify upper layer of carrier drop */
2194 if ((port->ip_notify & N_DDCD)
2195 && port->ip_port) {
2196 the_port->icount.dcd = 0;
2197 wake_up_interruptible
2198 (&the_port->info->
2199 delta_msr_wait);
2202 /* If we had any data to return, we
2203 * would have returned it above.
2205 return 0;
2208 if (*sc & IOC4_RXSB_MODEM_VALID) {
2209 /* Notify that an input overrun occurred */
2210 if ((*sc & IOC4_RXSB_OVERRUN)
2211 && (port->ip_notify & N_OVERRUN_ERROR)) {
2212 ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2214 /* Don't look at this byte again */
2215 *sc &= ~IOC4_RXSB_MODEM_VALID;
2218 /* Check for valid data or RX errors */
2219 if ((*sc & IOC4_RXSB_DATA_VALID) &&
2220 ((*sc & (IOC4_RXSB_PAR_ERR
2221 | IOC4_RXSB_FRAME_ERR
2222 | IOC4_RXSB_BREAK))
2223 && (port->ip_notify & (N_PARITY_ERROR
2224 | N_FRAMING_ERROR
2225 | N_BREAK)))) {
2226 /* There is an error condition on the next byte.
2227 * If we have already transferred some bytes,
2228 * we'll stop here. Otherwise if this is the
2229 * first byte to be read, we'll just transfer
2230 * it alone after notifying the
2231 * upper layer of its status.
2233 if (total > 0) {
2234 len = 0;
2235 break;
2236 } else {
2237 if ((*sc & IOC4_RXSB_PAR_ERR) &&
2238 (port->ip_notify & N_PARITY_ERROR)) {
2239 ioc4_cb_post_ncs(the_port,
2240 NCS_PARITY);
2242 if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2243 (port->ip_notify & N_FRAMING_ERROR)){
2244 ioc4_cb_post_ncs(the_port,
2245 NCS_FRAMING);
2247 if ((*sc & IOC4_RXSB_BREAK)
2248 && (port->ip_notify & N_BREAK)) {
2249 ioc4_cb_post_ncs
2250 (the_port,
2251 NCS_BREAK);
2253 len = 1;
2256 if (*sc & IOC4_RXSB_DATA_VALID) {
2257 *sc &= ~IOC4_RXSB_DATA_VALID;
2258 *buf = entry->ring_data[byte_num];
2259 buf++;
2260 len--;
2261 total++;
2265 /* If we used up this entry entirely, go on to the next one,
2266 * otherwise we must have run out of buffer space, so
2267 * leave the consumer pointer here for the next read in case
2268 * there are still unread bytes in this entry.
2270 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2271 cons_ptr += (int)sizeof(struct ring_entry);
2272 cons_ptr &= PROD_CONS_MASK;
2276 /* Update consumer pointer and re-arm rx timer interrupt */
2277 writel(cons_ptr, &port->ip_serial_regs->srcir);
2278 port->ip_rx_cons = cons_ptr;
2280 /* If we have now dipped below the rx high water mark and we have
2281 * rx_high interrupt turned off, we can now turn it back on again.
2283 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2284 & PROD_CONS_MASK) < ((port->ip_sscr &
2285 IOC4_SSCR_RX_THRESHOLD)
2286 << IOC4_PROD_CONS_PTR_OFF))) {
2287 port->ip_flags &= ~INPUT_HIGH;
2288 enable_intrs(port, hooks->intr_rx_high);
2290 return total;
2294 * receive_chars - upper level read. Called with ip_lock.
2295 * @the_port: port to read from
2297 static void receive_chars(struct uart_port *the_port)
2299 struct tty_struct *tty;
2300 unsigned char ch[IOC4_MAX_CHARS];
2301 int read_count, request_count = IOC4_MAX_CHARS;
2302 struct uart_icount *icount;
2303 struct uart_info *info = the_port->info;
2304 int flip = 0;
2305 unsigned long pflags;
2307 /* Make sure all the pointers are "good" ones */
2308 if (!info)
2309 return;
2310 if (!info->tty)
2311 return;
2313 spin_lock_irqsave(&the_port->lock, pflags);
2314 tty = info->tty;
2316 request_count = tty_buffer_request_room(tty, IOC4_MAX_CHARS - 2);
2318 if (request_count > 0) {
2319 icount = &the_port->icount;
2320 read_count = do_read(the_port, ch, request_count);
2321 if (read_count > 0) {
2322 tty_insert_flip_string(tty, ch, read_count);
2323 icount->rx += read_count;
2327 spin_unlock_irqrestore(&the_port->lock, pflags);
2329 if (flip)
2330 tty_flip_buffer_push(tty);
2334 * ic4_type - What type of console are we?
2335 * @port: Port to operate with (we ignore since we only have one port)
2338 static const char *ic4_type(struct uart_port *the_port)
2340 return "SGI IOC4 Serial";
2344 * ic4_tx_empty - Is the transmitter empty? We pretend we're always empty
2345 * @port: Port to operate on (we ignore since we always return 1)
2348 static unsigned int ic4_tx_empty(struct uart_port *the_port)
2350 return 1;
2354 * ic4_stop_tx - stop the transmitter
2355 * @port: Port to operate on
2358 static void ic4_stop_tx(struct uart_port *the_port)
2363 * null_void_function -
2364 * @port: Port to operate on
2367 static void null_void_function(struct uart_port *the_port)
2372 * ic4_shutdown - shut down the port - free irq and disable
2373 * @port: Port to shut down
2376 static void ic4_shutdown(struct uart_port *the_port)
2378 unsigned long port_flags;
2379 struct ioc4_port *port;
2380 struct uart_info *info;
2382 port = get_ioc4_port(the_port);
2383 if (!port)
2384 return;
2386 info = the_port->info;
2388 wake_up_interruptible(&info->delta_msr_wait);
2390 if (info->tty)
2391 set_bit(TTY_IO_ERROR, &info->tty->flags);
2393 spin_lock_irqsave(&the_port->lock, port_flags);
2394 set_notification(port, N_ALL, 0);
2395 spin_unlock_irqrestore(&the_port->lock, port_flags);
2399 * ic4_set_mctrl - set control lines (dtr, rts, etc)
2400 * @port: Port to operate on
2401 * @mctrl: Lines to set/unset
2404 static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2406 unsigned char mcr = 0;
2408 if (mctrl & TIOCM_RTS)
2409 mcr |= UART_MCR_RTS;
2410 if (mctrl & TIOCM_DTR)
2411 mcr |= UART_MCR_DTR;
2412 if (mctrl & TIOCM_OUT1)
2413 mcr |= UART_MCR_OUT1;
2414 if (mctrl & TIOCM_OUT2)
2415 mcr |= UART_MCR_OUT2;
2416 if (mctrl & TIOCM_LOOP)
2417 mcr |= UART_MCR_LOOP;
2419 set_mcr(the_port, 1, mcr, IOC4_SHADOW_DTR);
2423 * ic4_get_mctrl - get control line info
2424 * @port: port to operate on
2427 static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2429 struct ioc4_port *port = get_ioc4_port(the_port);
2430 uint32_t shadow;
2431 unsigned int ret = 0;
2433 if (!port)
2434 return 0;
2436 shadow = readl(&port->ip_serial_regs->shadow);
2437 if (shadow & IOC4_SHADOW_DCD)
2438 ret |= TIOCM_CAR;
2439 if (shadow & IOC4_SHADOW_DR)
2440 ret |= TIOCM_DSR;
2441 if (shadow & IOC4_SHADOW_CTS)
2442 ret |= TIOCM_CTS;
2443 return ret;
2447 * ic4_start_tx - Start transmitter, flush any output
2448 * @port: Port to operate on
2451 static void ic4_start_tx(struct uart_port *the_port)
2453 struct ioc4_port *port = get_ioc4_port(the_port);
2455 if (port) {
2456 set_notification(port, N_OUTPUT_LOWAT, 1);
2457 enable_intrs(port, port->ip_hooks->intr_tx_mt);
2462 * ic4_break_ctl - handle breaks
2463 * @port: Port to operate on
2464 * @break_state: Break state
2467 static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2472 * ic4_startup - Start up the serial port - always return 0 (We're always on)
2473 * @port: Port to operate on
2476 static int ic4_startup(struct uart_port *the_port)
2478 int retval;
2479 struct ioc4_port *port;
2480 struct ioc4_control *control;
2481 struct uart_info *info;
2482 unsigned long port_flags;
2484 if (!the_port) {
2485 return -ENODEV;
2487 port = get_ioc4_port(the_port);
2488 if (!port) {
2489 return -ENODEV;
2491 info = the_port->info;
2493 control = port->ip_control;
2494 if (!control) {
2495 return -ENODEV;
2498 /* Start up the serial port */
2499 spin_lock_irqsave(&the_port->lock, port_flags);
2500 retval = ic4_startup_local(the_port);
2501 spin_unlock_irqrestore(&the_port->lock, port_flags);
2502 return retval;
2506 * ic4_set_termios - set termios stuff
2507 * @port: port to operate on
2508 * @termios: New settings
2509 * @termios: Old
2512 static void
2513 ic4_set_termios(struct uart_port *the_port,
2514 struct termios *termios, struct termios *old_termios)
2516 unsigned long port_flags;
2518 spin_lock_irqsave(&the_port->lock, port_flags);
2519 ioc4_change_speed(the_port, termios, old_termios);
2520 spin_unlock_irqrestore(&the_port->lock, port_flags);
2524 * ic4_request_port - allocate resources for port - no op....
2525 * @port: port to operate on
2528 static int ic4_request_port(struct uart_port *port)
2530 return 0;
2533 /* Associate the uart functions above - given to serial core */
2535 static struct uart_ops ioc4_ops = {
2536 .tx_empty = ic4_tx_empty,
2537 .set_mctrl = ic4_set_mctrl,
2538 .get_mctrl = ic4_get_mctrl,
2539 .stop_tx = ic4_stop_tx,
2540 .start_tx = ic4_start_tx,
2541 .stop_rx = null_void_function,
2542 .enable_ms = null_void_function,
2543 .break_ctl = ic4_break_ctl,
2544 .startup = ic4_startup,
2545 .shutdown = ic4_shutdown,
2546 .set_termios = ic4_set_termios,
2547 .type = ic4_type,
2548 .release_port = null_void_function,
2549 .request_port = ic4_request_port,
2553 * Boot-time initialization code
2556 static struct uart_driver ioc4_uart = {
2557 .owner = THIS_MODULE,
2558 .driver_name = "ioc4_serial",
2559 .dev_name = DEVICE_NAME,
2560 .major = DEVICE_MAJOR,
2561 .minor = DEVICE_MINOR,
2562 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2566 * ioc4_serial_core_attach - register with serial core
2567 * This is done during pci probing
2568 * @pdev: handle for this card
2570 static inline int
2571 ioc4_serial_core_attach(struct pci_dev *pdev)
2573 struct ioc4_port *port;
2574 struct uart_port *the_port;
2575 struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2576 struct ioc4_control *control = idd->idd_serial_data;
2577 int ii;
2579 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2580 __FUNCTION__, pdev, (void *)control));
2582 if (!control)
2583 return -ENODEV;
2585 /* once around for each port on this card */
2586 for (ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++) {
2587 the_port = &control->ic_port[ii].icp_uart_port;
2588 port = control->ic_port[ii].icp_port;
2589 port->ip_port = the_port;
2591 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p\n",
2592 __FUNCTION__, (void *)the_port,
2593 (void *)port));
2595 /* membase, iobase and mapbase just need to be non-0 */
2596 the_port->membase = (unsigned char __iomem *)1;
2597 the_port->iobase = (pdev->bus->number << 16) | ii;
2598 the_port->line = (Num_of_ioc4_cards << 2) | ii;
2599 the_port->mapbase = 1;
2600 the_port->type = PORT_16550A;
2601 the_port->fifosize = IOC4_FIFO_CHARS;
2602 the_port->ops = &ioc4_ops;
2603 the_port->irq = control->ic_irq;
2604 the_port->dev = &pdev->dev;
2605 spin_lock_init(&the_port->lock);
2606 if (uart_add_one_port(&ioc4_uart, the_port) < 0) {
2607 printk(KERN_WARNING
2608 "%s: unable to add port %d bus %d\n",
2609 __FUNCTION__, the_port->line, pdev->bus->number);
2610 } else {
2611 DPRINT_CONFIG(
2612 ("IOC4 serial port %d irq = %d, bus %d\n",
2613 the_port->line, the_port->irq, pdev->bus->number));
2615 /* all ports are rs232 for now */
2616 ioc4_set_proto(port, PROTO_RS232);
2618 return 0;
2622 * ioc4_serial_attach_one - register attach function
2623 * called per card found from IOC4 master module.
2624 * @idd: Master module data for this IOC4
2627 ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2629 unsigned long tmp_addr1;
2630 struct ioc4_serial __iomem *serial;
2631 struct ioc4_soft *soft;
2632 struct ioc4_control *control;
2633 int ret = 0;
2636 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev, idd->idd_pci_id));
2638 /* request serial registers */
2639 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
2641 if (!request_region(tmp_addr1, sizeof(struct ioc4_serial),
2642 "sioc4_uart")) {
2643 printk(KERN_WARNING
2644 "ioc4 (%p): unable to get request region for "
2645 "uart space\n", (void *)idd->idd_pdev);
2646 ret = -ENODEV;
2647 goto out1;
2649 serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2650 if (!serial) {
2651 printk(KERN_WARNING
2652 "ioc4 (%p) : unable to remap ioc4 serial register\n",
2653 (void *)idd->idd_pdev);
2654 ret = -ENODEV;
2655 goto out2;
2657 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2658 __FUNCTION__, (void *)idd->idd_misc_regs, (void *)serial));
2660 /* Get memory for the new card */
2661 control = kmalloc(sizeof(struct ioc4_control) * IOC4_NUM_SERIAL_PORTS,
2662 GFP_KERNEL);
2664 if (!control) {
2665 printk(KERN_WARNING "ioc4_attach_one"
2666 ": unable to get memory for the IOC4\n");
2667 ret = -ENOMEM;
2668 goto out2;
2670 memset(control, 0, sizeof(struct ioc4_control));
2671 idd->idd_serial_data = control;
2673 /* Allocate the soft structure */
2674 soft = kmalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2675 if (!soft) {
2676 printk(KERN_WARNING
2677 "ioc4 (%p): unable to get memory for the soft struct\n",
2678 (void *)idd->idd_pdev);
2679 ret = -ENOMEM;
2680 goto out3;
2682 memset(soft, 0, sizeof(struct ioc4_soft));
2684 spin_lock_init(&soft->is_ir_lock);
2685 soft->is_ioc4_misc_addr = idd->idd_misc_regs;
2686 soft->is_ioc4_serial_addr = serial;
2688 /* Init the IOC4 */
2689 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT,
2690 &idd->idd_misc_regs->sio_cr.raw);
2692 /* Enable serial port mode select generic PIO pins as outputs */
2693 writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2694 | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
2695 &idd->idd_misc_regs->gpcr_s.raw);
2697 /* Clear and disable all serial interrupts */
2698 write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
2699 writel(~0, &idd->idd_misc_regs->sio_ir.raw);
2700 write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC,
2701 IOC4_OTHER_INTR_TYPE);
2702 writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw);
2703 control->ic_soft = soft;
2705 /* Hook up interrupt handler */
2706 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, SA_SHIRQ,
2707 "sgi-ioc4serial", (void *)soft)) {
2708 control->ic_irq = idd->idd_pdev->irq;
2709 } else {
2710 printk(KERN_WARNING
2711 "%s : request_irq fails for IRQ 0x%x\n ",
2712 __FUNCTION__, idd->idd_pdev->irq);
2714 ret = ioc4_attach_local(idd);
2715 if (ret)
2716 goto out4;
2718 /* register port with the serial core */
2720 if ((ret = ioc4_serial_core_attach(idd->idd_pdev)))
2721 goto out4;
2723 Num_of_ioc4_cards++;
2725 return ret;
2727 /* error exits that give back resources */
2728 out4:
2729 kfree(soft);
2730 out3:
2731 kfree(control);
2732 out2:
2733 release_region(tmp_addr1, sizeof(struct ioc4_serial));
2734 out1:
2736 return ret;
2741 * ioc4_serial_remove_one - detach function
2743 * @idd: IOC4 master module data for this IOC4
2746 int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2748 int ii;
2749 struct ioc4_control *control;
2750 struct uart_port *the_port;
2751 struct ioc4_port *port;
2752 struct ioc4_soft *soft;
2754 control = idd->idd_serial_data;
2756 for (ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++) {
2757 the_port = &control->ic_port[ii].icp_uart_port;
2758 if (the_port) {
2759 uart_remove_one_port(&ioc4_uart, the_port);
2761 port = control->ic_port[ii].icp_port;
2762 if (!(ii & 1) && port) {
2763 pci_free_consistent(port->ip_pdev,
2764 TOTAL_RING_BUF_SIZE,
2765 (void *)port->ip_cpu_ringbuf,
2766 port->ip_dma_ringbuf);
2767 kfree(port);
2770 soft = control->ic_soft;
2771 if (soft) {
2772 free_irq(control->ic_irq, (void *)soft);
2773 if (soft->is_ioc4_serial_addr) {
2774 release_region((unsigned long)
2775 soft->is_ioc4_serial_addr,
2776 sizeof(struct ioc4_serial));
2778 kfree(soft);
2780 kfree(control);
2781 idd->idd_serial_data = NULL;
2783 return 0;
2786 static struct ioc4_submodule ioc4_serial_submodule = {
2787 .is_name = "IOC4_serial",
2788 .is_owner = THIS_MODULE,
2789 .is_probe = ioc4_serial_attach_one,
2790 .is_remove = ioc4_serial_remove_one,
2794 * ioc4_serial_init - module init
2796 int ioc4_serial_init(void)
2798 int ret;
2800 /* register with serial core */
2801 if ((ret = uart_register_driver(&ioc4_uart)) < 0) {
2802 printk(KERN_WARNING
2803 "%s: Couldn't register IOC4 serial driver\n",
2804 __FUNCTION__);
2805 return ret;
2808 /* register with IOC4 main module */
2809 return ioc4_register_submodule(&ioc4_serial_submodule);
2812 static void __devexit ioc4_serial_exit(void)
2814 ioc4_unregister_submodule(&ioc4_serial_submodule);
2815 uart_unregister_driver(&ioc4_uart);
2818 module_init(ioc4_serial_init);
2819 module_exit(ioc4_serial_exit);
2821 MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2822 MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2823 MODULE_LICENSE("GPL");