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[CPUFREQ] Fix the p4-clockmod N60 errata workaround.
[linux-2.6/mini2440.git] / drivers / serial / amba-pl011.c
blob034a029e356edfe3e8f48d1749b03450e2196c26
1 /*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
26 *
27 * This is a generic driver for ARM AMBA-type serial ports. They
28 * have a lot of 16550-like features, but are not register compatible.
29 * Note that although they do have CTS, DCD and DSR inputs, they do
30 * not have an RI input, nor do they have DTR or RTS outputs. If
31 * required, these have to be supplied via some other means (eg, GPIO)
32 * and hooked into this driver.
33 */
34 #include <linux/config.h>
35
36 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
37 #define SUPPORT_SYSRQ
38 #endif
39
40 #include <linux/module.h>
41 #include <linux/ioport.h>
42 #include <linux/init.h>
43 #include <linux/console.h>
44 #include <linux/sysrq.h>
45 #include <linux/device.h>
46 #include <linux/tty.h>
47 #include <linux/tty_flip.h>
48 #include <linux/serial_core.h>
49 #include <linux/serial.h>
50 #include <linux/amba/bus.h>
51 #include <linux/amba/serial.h>
52 #include <linux/clk.h>
53
54 #include <asm/io.h>
55 #include <asm/sizes.h>
56
57 #define UART_NR 14
58
59 #define SERIAL_AMBA_MAJOR 204
60 #define SERIAL_AMBA_MINOR 64
61 #define SERIAL_AMBA_NR UART_NR
62
63 #define AMBA_ISR_PASS_LIMIT 256
64
65 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
66 #define UART_DUMMY_DR_RX (1 << 16)
67
68 /*
69 * We wrap our port structure around the generic uart_port.
70 */
71 struct uart_amba_port {
72 struct uart_port port;
73 struct clk *clk;
74 unsigned int im; /* interrupt mask */
75 unsigned int old_status;
76 };
77
78 static void pl011_stop_tx(struct uart_port *port)
79 {
80 struct uart_amba_port *uap = (struct uart_amba_port *)port;
81
82 uap->im &= ~UART011_TXIM;
83 writew(uap->im, uap->port.membase + UART011_IMSC);
84 }
85
86 static void pl011_start_tx(struct uart_port *port)
87 {
88 struct uart_amba_port *uap = (struct uart_amba_port *)port;
89
90 uap->im |= UART011_TXIM;
91 writew(uap->im, uap->port.membase + UART011_IMSC);
92 }
93
94 static void pl011_stop_rx(struct uart_port *port)
95 {
96 struct uart_amba_port *uap = (struct uart_amba_port *)port;
97
98 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
99 UART011_PEIM|UART011_BEIM|UART011_OEIM);
100 writew(uap->im, uap->port.membase + UART011_IMSC);
101 }
102
103 static void pl011_enable_ms(struct uart_port *port)
104 {
105 struct uart_amba_port *uap = (struct uart_amba_port *)port;
106
107 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
108 writew(uap->im, uap->port.membase + UART011_IMSC);
109 }
110
111 static void
112 #ifdef SUPPORT_SYSRQ
113 pl011_rx_chars(struct uart_amba_port *uap, struct pt_regs *regs)
114 #else
115 pl011_rx_chars(struct uart_amba_port *uap)
116 #endif
117 {
118 struct tty_struct *tty = uap->port.info->tty;
119 unsigned int status, ch, flag, max_count = 256;
120
121 status = readw(uap->port.membase + UART01x_FR);
122 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
123 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
124 flag = TTY_NORMAL;
125 uap->port.icount.rx++;
126
127 /*
128 * Note that the error handling code is
129 * out of the main execution path
130 */
131 if (unlikely(ch & UART_DR_ERROR)) {
132 if (ch & UART011_DR_BE) {
133 ch &= ~(UART011_DR_FE | UART011_DR_PE);
134 uap->port.icount.brk++;
135 if (uart_handle_break(&uap->port))
136 goto ignore_char;
137 } else if (ch & UART011_DR_PE)
138 uap->port.icount.parity++;
139 else if (ch & UART011_DR_FE)
140 uap->port.icount.frame++;
141 if (ch & UART011_DR_OE)
142 uap->port.icount.overrun++;
143
144 ch &= uap->port.read_status_mask;
145
146 if (ch & UART011_DR_BE)
147 flag = TTY_BREAK;
148 else if (ch & UART011_DR_PE)
149 flag = TTY_PARITY;
150 else if (ch & UART011_DR_FE)
151 flag = TTY_FRAME;
152 }
153
154 if (uart_handle_sysrq_char(&uap->port, ch & 255, regs))
155 goto ignore_char;
156
157 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
158
159 ignore_char:
160 status = readw(uap->port.membase + UART01x_FR);
161 }
162 tty_flip_buffer_push(tty);
163 return;
164 }
165
166 static void pl011_tx_chars(struct uart_amba_port *uap)
167 {
168 struct circ_buf *xmit = &uap->port.info->xmit;
169 int count;
170
171 if (uap->port.x_char) {
172 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
173 uap->port.icount.tx++;
174 uap->port.x_char = 0;
175 return;
176 }
177 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
178 pl011_stop_tx(&uap->port);
179 return;
180 }
181
182 count = uap->port.fifosize >> 1;
183 do {
184 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
185 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
186 uap->port.icount.tx++;
187 if (uart_circ_empty(xmit))
188 break;
189 } while (--count > 0);
190
191 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
192 uart_write_wakeup(&uap->port);
193
194 if (uart_circ_empty(xmit))
195 pl011_stop_tx(&uap->port);
196 }
197
198 static void pl011_modem_status(struct uart_amba_port *uap)
199 {
200 unsigned int status, delta;
201
202 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
203
204 delta = status ^ uap->old_status;
205 uap->old_status = status;
206
207 if (!delta)
208 return;
209
210 if (delta & UART01x_FR_DCD)
211 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
212
213 if (delta & UART01x_FR_DSR)
214 uap->port.icount.dsr++;
215
216 if (delta & UART01x_FR_CTS)
217 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
218
219 wake_up_interruptible(&uap->port.info->delta_msr_wait);
220 }
221
222 static irqreturn_t pl011_int(int irq, void *dev_id, struct pt_regs *regs)
223 {
224 struct uart_amba_port *uap = dev_id;
225 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
226 int handled = 0;
227
228 spin_lock(&uap->port.lock);
229
230 status = readw(uap->port.membase + UART011_MIS);
231 if (status) {
232 do {
233 writew(status & ~(UART011_TXIS|UART011_RTIS|
234 UART011_RXIS),
235 uap->port.membase + UART011_ICR);
236
237 if (status & (UART011_RTIS|UART011_RXIS))
238 #ifdef SUPPORT_SYSRQ
239 pl011_rx_chars(uap, regs);
240 #else
241 pl011_rx_chars(uap);
242 #endif
243 if (status & (UART011_DSRMIS|UART011_DCDMIS|
244 UART011_CTSMIS|UART011_RIMIS))
245 pl011_modem_status(uap);
246 if (status & UART011_TXIS)
247 pl011_tx_chars(uap);
248
249 if (pass_counter-- == 0)
250 break;
251
252 status = readw(uap->port.membase + UART011_MIS);
253 } while (status != 0);
254 handled = 1;
255 }
256
257 spin_unlock(&uap->port.lock);
258
259 return IRQ_RETVAL(handled);
260 }
261
262 static unsigned int pl01x_tx_empty(struct uart_port *port)
263 {
264 struct uart_amba_port *uap = (struct uart_amba_port *)port;
265 unsigned int status = readw(uap->port.membase + UART01x_FR);
266 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
267 }
268
269 static unsigned int pl01x_get_mctrl(struct uart_port *port)
270 {
271 struct uart_amba_port *uap = (struct uart_amba_port *)port;
272 unsigned int result = 0;
273 unsigned int status = readw(uap->port.membase + UART01x_FR);
274
275 #define BIT(uartbit, tiocmbit) \
276 if (status & uartbit) \
277 result |= tiocmbit
278
279 BIT(UART01x_FR_DCD, TIOCM_CAR);
280 BIT(UART01x_FR_DSR, TIOCM_DSR);
281 BIT(UART01x_FR_CTS, TIOCM_CTS);
282 BIT(UART011_FR_RI, TIOCM_RNG);
283 #undef BIT
284 return result;
285 }
286
287 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
288 {
289 struct uart_amba_port *uap = (struct uart_amba_port *)port;
290 unsigned int cr;
291
292 cr = readw(uap->port.membase + UART011_CR);
293
294 #define BIT(tiocmbit, uartbit) \
295 if (mctrl & tiocmbit) \
296 cr |= uartbit; \
297 else \
298 cr &= ~uartbit
299
300 BIT(TIOCM_RTS, UART011_CR_RTS);
301 BIT(TIOCM_DTR, UART011_CR_DTR);
302 BIT(TIOCM_OUT1, UART011_CR_OUT1);
303 BIT(TIOCM_OUT2, UART011_CR_OUT2);
304 BIT(TIOCM_LOOP, UART011_CR_LBE);
305 #undef BIT
306
307 writew(cr, uap->port.membase + UART011_CR);
308 }
309
310 static void pl011_break_ctl(struct uart_port *port, int break_state)
311 {
312 struct uart_amba_port *uap = (struct uart_amba_port *)port;
313 unsigned long flags;
314 unsigned int lcr_h;
315
316 spin_lock_irqsave(&uap->port.lock, flags);
317 lcr_h = readw(uap->port.membase + UART011_LCRH);
318 if (break_state == -1)
319 lcr_h |= UART01x_LCRH_BRK;
320 else
321 lcr_h &= ~UART01x_LCRH_BRK;
322 writew(lcr_h, uap->port.membase + UART011_LCRH);
323 spin_unlock_irqrestore(&uap->port.lock, flags);
324 }
325
326 static int pl011_startup(struct uart_port *port)
327 {
328 struct uart_amba_port *uap = (struct uart_amba_port *)port;
329 unsigned int cr;
330 int retval;
331
332 /*
333 * Try to enable the clock producer.
334 */
335 retval = clk_enable(uap->clk);
336 if (retval)
337 goto out;
338
339 uap->port.uartclk = clk_get_rate(uap->clk);
340
341 /*
342 * Allocate the IRQ
343 */
344 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
345 if (retval)
346 goto clk_dis;
347
348 writew(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
349 uap->port.membase + UART011_IFLS);
350
351 /*
352 * Provoke TX FIFO interrupt into asserting.
353 */
354 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
355 writew(cr, uap->port.membase + UART011_CR);
356 writew(0, uap->port.membase + UART011_FBRD);
357 writew(1, uap->port.membase + UART011_IBRD);
358 writew(0, uap->port.membase + UART011_LCRH);
359 writew(0, uap->port.membase + UART01x_DR);
360 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
361 barrier();
362
363 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
364 writew(cr, uap->port.membase + UART011_CR);
365
366 /*
367 * initialise the old status of the modem signals
368 */
369 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
370
371 /*
372 * Finally, enable interrupts
373 */
374 spin_lock_irq(&uap->port.lock);
375 uap->im = UART011_RXIM | UART011_RTIM;
376 writew(uap->im, uap->port.membase + UART011_IMSC);
377 spin_unlock_irq(&uap->port.lock);
378
379 return 0;
380
381 clk_dis:
382 clk_disable(uap->clk);
383 out:
384 return retval;
385 }
386
387 static void pl011_shutdown(struct uart_port *port)
388 {
389 struct uart_amba_port *uap = (struct uart_amba_port *)port;
390 unsigned long val;
391
392 /*
393 * disable all interrupts
394 */
395 spin_lock_irq(&uap->port.lock);
396 uap->im = 0;
397 writew(uap->im, uap->port.membase + UART011_IMSC);
398 writew(0xffff, uap->port.membase + UART011_ICR);
399 spin_unlock_irq(&uap->port.lock);
400
401 /*
402 * Free the interrupt
403 */
404 free_irq(uap->port.irq, uap);
405
406 /*
407 * disable the port
408 */
409 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
410
411 /*
412 * disable break condition and fifos
413 */
414 val = readw(uap->port.membase + UART011_LCRH);
415 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
416 writew(val, uap->port.membase + UART011_LCRH);
417
418 /*
419 * Shut down the clock producer
420 */
421 clk_disable(uap->clk);
422 }
423
424 static void
425 pl011_set_termios(struct uart_port *port, struct termios *termios,
426 struct termios *old)
427 {
428 unsigned int lcr_h, old_cr;
429 unsigned long flags;
430 unsigned int baud, quot;
431
432 /*
433 * Ask the core to calculate the divisor for us.
434 */
435 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
436 quot = port->uartclk * 4 / baud;
437
438 switch (termios->c_cflag & CSIZE) {
439 case CS5:
440 lcr_h = UART01x_LCRH_WLEN_5;
441 break;
442 case CS6:
443 lcr_h = UART01x_LCRH_WLEN_6;
444 break;
445 case CS7:
446 lcr_h = UART01x_LCRH_WLEN_7;
447 break;
448 default: // CS8
449 lcr_h = UART01x_LCRH_WLEN_8;
450 break;
451 }
452 if (termios->c_cflag & CSTOPB)
453 lcr_h |= UART01x_LCRH_STP2;
454 if (termios->c_cflag & PARENB) {
455 lcr_h |= UART01x_LCRH_PEN;
456 if (!(termios->c_cflag & PARODD))
457 lcr_h |= UART01x_LCRH_EPS;
458 }
459 if (port->fifosize > 1)
460 lcr_h |= UART01x_LCRH_FEN;
461
462 spin_lock_irqsave(&port->lock, flags);
463
464 /*
465 * Update the per-port timeout.
466 */
467 uart_update_timeout(port, termios->c_cflag, baud);
468
469 port->read_status_mask = UART011_DR_OE | 255;
470 if (termios->c_iflag & INPCK)
471 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
472 if (termios->c_iflag & (BRKINT | PARMRK))
473 port->read_status_mask |= UART011_DR_BE;
474
475 /*
476 * Characters to ignore
477 */
478 port->ignore_status_mask = 0;
479 if (termios->c_iflag & IGNPAR)
480 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
481 if (termios->c_iflag & IGNBRK) {
482 port->ignore_status_mask |= UART011_DR_BE;
483 /*
484 * If we're ignoring parity and break indicators,
485 * ignore overruns too (for real raw support).
486 */
487 if (termios->c_iflag & IGNPAR)
488 port->ignore_status_mask |= UART011_DR_OE;
489 }
490
491 /*
492 * Ignore all characters if CREAD is not set.
493 */
494 if ((termios->c_cflag & CREAD) == 0)
495 port->ignore_status_mask |= UART_DUMMY_DR_RX;
496
497 if (UART_ENABLE_MS(port, termios->c_cflag))
498 pl011_enable_ms(port);
499
500 /* first, disable everything */
501 old_cr = readw(port->membase + UART011_CR);
502 writew(0, port->membase + UART011_CR);
503
504 /* Set baud rate */
505 writew(quot & 0x3f, port->membase + UART011_FBRD);
506 writew(quot >> 6, port->membase + UART011_IBRD);
507
508 /*
509 * ----------v----------v----------v----------v-----
510 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
511 * ----------^----------^----------^----------^-----
512 */
513 writew(lcr_h, port->membase + UART011_LCRH);
514 writew(old_cr, port->membase + UART011_CR);
515
516 spin_unlock_irqrestore(&port->lock, flags);
517 }
518
519 static const char *pl011_type(struct uart_port *port)
520 {
521 return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
522 }
523
524 /*
525 * Release the memory region(s) being used by 'port'
526 */
527 static void pl010_release_port(struct uart_port *port)
528 {
529 release_mem_region(port->mapbase, SZ_4K);
530 }
531
532 /*
533 * Request the memory region(s) being used by 'port'
534 */
535 static int pl010_request_port(struct uart_port *port)
536 {
537 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
538 != NULL ? 0 : -EBUSY;
539 }
540
541 /*
542 * Configure/autoconfigure the port.
543 */
544 static void pl010_config_port(struct uart_port *port, int flags)
545 {
546 if (flags & UART_CONFIG_TYPE) {
547 port->type = PORT_AMBA;
548 pl010_request_port(port);
549 }
550 }
551
552 /*
553 * verify the new serial_struct (for TIOCSSERIAL).
554 */
555 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
556 {
557 int ret = 0;
558 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
559 ret = -EINVAL;
560 if (ser->irq < 0 || ser->irq >= NR_IRQS)
561 ret = -EINVAL;
562 if (ser->baud_base < 9600)
563 ret = -EINVAL;
564 return ret;
565 }
566
567 static struct uart_ops amba_pl011_pops = {
568 .tx_empty = pl01x_tx_empty,
569 .set_mctrl = pl011_set_mctrl,
570 .get_mctrl = pl01x_get_mctrl,
571 .stop_tx = pl011_stop_tx,
572 .start_tx = pl011_start_tx,
573 .stop_rx = pl011_stop_rx,
574 .enable_ms = pl011_enable_ms,
575 .break_ctl = pl011_break_ctl,
576 .startup = pl011_startup,
577 .shutdown = pl011_shutdown,
578 .set_termios = pl011_set_termios,
579 .type = pl011_type,
580 .release_port = pl010_release_port,
581 .request_port = pl010_request_port,
582 .config_port = pl010_config_port,
583 .verify_port = pl010_verify_port,
584 };
585
586 static struct uart_amba_port *amba_ports[UART_NR];
587
588 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
589
590 static inline void
591 pl011_console_write_char(struct uart_amba_port *uap, char ch)
592 {
593 unsigned int status;
594
595 do {
596 status = readw(uap->port.membase + UART01x_FR);
597 } while (status & UART01x_FR_TXFF);
598 writew(ch, uap->port.membase + UART01x_DR);
599 }
600
601 static void
602 pl011_console_write(struct console *co, const char *s, unsigned int count)
603 {
604 struct uart_amba_port *uap = amba_ports[co->index];
605 unsigned int status, old_cr, new_cr;
606 int i;
607
608 clk_enable(uap->clk);
609
610 /*
611 * First save the CR then disable the interrupts
612 */
613 old_cr = readw(uap->port.membase + UART011_CR);
614 new_cr = old_cr & ~UART011_CR_CTSEN;
615 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
616 writew(new_cr, uap->port.membase + UART011_CR);
617
618 /*
619 * Now, do each character
620 */
621 for (i = 0; i < count; i++) {
622 pl011_console_write_char(uap, s[i]);
623 if (s[i] == '\n')
624 pl011_console_write_char(uap, '\r');
625 }
626
627 /*
628 * Finally, wait for transmitter to become empty
629 * and restore the TCR
630 */
631 do {
632 status = readw(uap->port.membase + UART01x_FR);
633 } while (status & UART01x_FR_BUSY);
634 writew(old_cr, uap->port.membase + UART011_CR);
635
636 clk_disable(uap->clk);
637 }
638
639 static void __init
640 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
641 int *parity, int *bits)
642 {
643 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
644 unsigned int lcr_h, ibrd, fbrd;
645
646 lcr_h = readw(uap->port.membase + UART011_LCRH);
647
648 *parity = 'n';
649 if (lcr_h & UART01x_LCRH_PEN) {
650 if (lcr_h & UART01x_LCRH_EPS)
651 *parity = 'e';
652 else
653 *parity = 'o';
654 }
655
656 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
657 *bits = 7;
658 else
659 *bits = 8;
660
661 ibrd = readw(uap->port.membase + UART011_IBRD);
662 fbrd = readw(uap->port.membase + UART011_FBRD);
663
664 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
665 }
666 }
667
668 static int __init pl011_console_setup(struct console *co, char *options)
669 {
670 struct uart_amba_port *uap;
671 int baud = 38400;
672 int bits = 8;
673 int parity = 'n';
674 int flow = 'n';
675
676 /*
677 * Check whether an invalid uart number has been specified, and
678 * if so, search for the first available port that does have
679 * console support.
680 */
681 if (co->index >= UART_NR)
682 co->index = 0;
683 uap = amba_ports[co->index];
684
685 uap->port.uartclk = clk_get_rate(uap->clk);
686
687 if (options)
688 uart_parse_options(options, &baud, &parity, &bits, &flow);
689 else
690 pl011_console_get_options(uap, &baud, &parity, &bits);
691
692 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
693 }
694
695 static struct uart_driver amba_reg;
696 static struct console amba_console = {
697 .name = "ttyAMA",
698 .write = pl011_console_write,
699 .device = uart_console_device,
700 .setup = pl011_console_setup,
701 .flags = CON_PRINTBUFFER,
702 .index = -1,
703 .data = &amba_reg,
704 };
705
706 #define AMBA_CONSOLE (&amba_console)
707 #else
708 #define AMBA_CONSOLE NULL
709 #endif
710
711 static struct uart_driver amba_reg = {
712 .owner = THIS_MODULE,
713 .driver_name = "ttyAMA",
714 .dev_name = "ttyAMA",
715 .major = SERIAL_AMBA_MAJOR,
716 .minor = SERIAL_AMBA_MINOR,
717 .nr = UART_NR,
718 .cons = AMBA_CONSOLE,
719 };
720
721 static int pl011_probe(struct amba_device *dev, void *id)
722 {
723 struct uart_amba_port *uap;
724 void __iomem *base;
725 int i, ret;
726
727 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
728 if (amba_ports[i] == NULL)
729 break;
730
731 if (i == ARRAY_SIZE(amba_ports)) {
732 ret = -EBUSY;
733 goto out;
734 }
735
736 uap = kmalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
737 if (uap == NULL) {
738 ret = -ENOMEM;
739 goto out;
740 }
741
742 base = ioremap(dev->res.start, PAGE_SIZE);
743 if (!base) {
744 ret = -ENOMEM;
745 goto free;
746 }
747
748 memset(uap, 0, sizeof(struct uart_amba_port));
749 uap->clk = clk_get(&dev->dev, "UARTCLK");
750 if (IS_ERR(uap->clk)) {
751 ret = PTR_ERR(uap->clk);
752 goto unmap;
753 }
754
755 uap->port.dev = &dev->dev;
756 uap->port.mapbase = dev->res.start;
757 uap->port.membase = base;
758 uap->port.iotype = UPIO_MEM;
759 uap->port.irq = dev->irq[0];
760 uap->port.fifosize = 16;
761 uap->port.ops = &amba_pl011_pops;
762 uap->port.flags = UPF_BOOT_AUTOCONF;
763 uap->port.line = i;
764
765 amba_ports[i] = uap;
766
767 amba_set_drvdata(dev, uap);
768 ret = uart_add_one_port(&amba_reg, &uap->port);
769 if (ret) {
770 amba_set_drvdata(dev, NULL);
771 amba_ports[i] = NULL;
772 clk_put(uap->clk);
773 unmap:
774 iounmap(base);
775 free:
776 kfree(uap);
777 }
778 out:
779 return ret;
780 }
781
782 static int pl011_remove(struct amba_device *dev)
783 {
784 struct uart_amba_port *uap = amba_get_drvdata(dev);
785 int i;
786
787 amba_set_drvdata(dev, NULL);
788
789 uart_remove_one_port(&amba_reg, &uap->port);
790
791 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
792 if (amba_ports[i] == uap)
793 amba_ports[i] = NULL;
794
795 iounmap(uap->port.membase);
796 clk_put(uap->clk);
797 kfree(uap);
798 return 0;
799 }
800
801 static struct amba_id pl011_ids[] __initdata = {
802 {
803 .id = 0x00041011,
804 .mask = 0x000fffff,
805 },
806 { 0, 0 },
807 };
808
809 static struct amba_driver pl011_driver = {
810 .drv = {
811 .name = "uart-pl011",
812 },
813 .id_table = pl011_ids,
814 .probe = pl011_probe,
815 .remove = pl011_remove,
816 };
817
818 static int __init pl011_init(void)
819 {
820 int ret;
821 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
822
823 ret = uart_register_driver(&amba_reg);
824 if (ret == 0) {
825 ret = amba_driver_register(&pl011_driver);
826 if (ret)
827 uart_unregister_driver(&amba_reg);
828 }
829 return ret;
830 }
831
832 static void __exit pl011_exit(void)
833 {
834 amba_driver_unregister(&pl011_driver);
835 uart_unregister_driver(&amba_reg);
836 }
837
838 module_init(pl011_init);
839 module_exit(pl011_exit);
840
841 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
842 MODULE_DESCRIPTION("ARM AMBA serial port driver");
843 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards