drivers/serial/21285.c

   1 /*
   2  * linux/drivers/char/21285.c
   3  *
   4  * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
   5  *
   6  * Based on drivers/char/serial.c
   7  *
   8  *  $Id: 21285.c,v 1.37 2002/07/28 10:03:27 rmk Exp $
   9  */
  10 #include <linux/config.h>
  11 #include <linux/module.h>
  12 #include <linux/tty.h>
  13 #include <linux/ioport.h>
  14 #include <linux/init.h>
  15 #include <linux/console.h>
  16 #include <linux/device.h>
  17 #include <linux/tty_flip.h>
  18 #include <linux/serial_core.h>
  19 #include <linux/serial.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/irq.h>
  23 #include <asm/mach-types.h>
  24 #include <asm/hardware/dec21285.h>
  25 #include <asm/hardware.h>
  26
  27 #define BAUD_BASE               (mem_fclk_21285/64)
  28
  29 #define SERIAL_21285_NAME       "ttyFB"
  30 #define SERIAL_21285_MAJOR      204
  31 #define SERIAL_21285_MINOR      4
  32
  33 #define RXSTAT_DUMMY_READ       0x80000000
  34 #define RXSTAT_FRAME            (1 << 0)
  35 #define RXSTAT_PARITY           (1 << 1)
  36 #define RXSTAT_OVERRUN          (1 << 2)
  37 #define RXSTAT_ANYERR           (RXSTAT_FRAME|RXSTAT_PARITY|RXSTAT_OVERRUN)
  38
  39 #define H_UBRLCR_BREAK          (1 << 0)
  40 #define H_UBRLCR_PARENB         (1 << 1)
  41 #define H_UBRLCR_PAREVN         (1 << 2)
  42 #define H_UBRLCR_STOPB          (1 << 3)
  43 #define H_UBRLCR_FIFO           (1 << 4)
  44
  45 static const char serial21285_name[] = "Footbridge UART";
  46
  47 #define tx_enabled(port)        ((port)->unused[0])
  48 #define rx_enabled(port)        ((port)->unused[1])
  49
  50 /*
  51  * The documented expression for selecting the divisor is:
  52  *  BAUD_BASE / baud - 1
  53  * However, typically BAUD_BASE is not divisible by baud, so
  54  * we want to select the divisor that gives us the minimum
  55  * error.  Therefore, we want:
  56  *  int(BAUD_BASE / baud - 0.5) ->
  57  *  int(BAUD_BASE / baud - (baud >> 1) / baud) ->
  58  *  int((BAUD_BASE - (baud >> 1)) / baud)
  59  */
  60
  61 static void serial21285_stop_tx(struct uart_port *port)
  62 {
  63         if (tx_enabled(port)) {
  64                 disable_irq(IRQ_CONTX);
  65                 tx_enabled(port) = 0;
  66         }
  67 }
  68
  69 static void serial21285_start_tx(struct uart_port *port)
  70 {
  71         if (!tx_enabled(port)) {
  72                 enable_irq(IRQ_CONTX);
  73                 tx_enabled(port) = 1;
  74         }
  75 }
  76
  77 static void serial21285_stop_rx(struct uart_port *port)
  78 {
  79         if (rx_enabled(port)) {
  80                 disable_irq(IRQ_CONRX);
  81                 rx_enabled(port) = 0;
  82         }
  83 }
  84
  85 static void serial21285_enable_ms(struct uart_port *port)
  86 {
  87 }
  88
  89 static irqreturn_t serial21285_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
  90 {
  91         struct uart_port *port = dev_id;
  92         struct tty_struct *tty = port->info->tty;
  93         unsigned int status, ch, flag, rxs, max_count = 256;
  94
  95         status = *CSR_UARTFLG;
  96         while (!(status & 0x10) && max_count--) {
  97                 ch = *CSR_UARTDR;
  98                 flag = TTY_NORMAL;
  99                 port->icount.rx++;
 100
 101                 rxs = *CSR_RXSTAT | RXSTAT_DUMMY_READ;
 102                 if (unlikely(rxs & RXSTAT_ANYERR)) {
 103                         if (rxs & RXSTAT_PARITY)
 104                                 port->icount.parity++;
 105                         else if (rxs & RXSTAT_FRAME)
 106                                 port->icount.frame++;
 107                         if (rxs & RXSTAT_OVERRUN)
 108                                 port->icount.overrun++;
 109
 110                         rxs &= port->read_status_mask;
 111
 112                         if (rxs & RXSTAT_PARITY)
 113                                 flag = TTY_PARITY;
 114                         else if (rxs & RXSTAT_FRAME)
 115                                 flag = TTY_FRAME;
 116                 }
 117
 118                 uart_insert_char(port, rxs, RXSTAT_OVERRUN, ch, flag);
 119
 120                 status = *CSR_UARTFLG;
 121         }
 122         tty_flip_buffer_push(tty);
 123
 124         return IRQ_HANDLED;
 125 }
 126
 127 static irqreturn_t serial21285_tx_chars(int irq, void *dev_id, struct pt_regs *regs)
 128 {
 129         struct uart_port *port = dev_id;
 130         struct circ_buf *xmit = &port->info->xmit;
 131         int count = 256;
 132
 133         if (port->x_char) {
 134                 *CSR_UARTDR = port->x_char;
 135                 port->icount.tx++;
 136                 port->x_char = 0;
 137                 goto out;
 138         }
 139         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 140                 serial21285_stop_tx(port);
 141                 goto out;
 142         }
 143
 144         do {
 145                 *CSR_UARTDR = xmit->buf[xmit->tail];
 146                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 147                 port->icount.tx++;
 148                 if (uart_circ_empty(xmit))
 149                         break;
 150         } while (--count > 0 && !(*CSR_UARTFLG & 0x20));
 151
 152         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 153                 uart_write_wakeup(port);
 154
 155         if (uart_circ_empty(xmit))
 156                 serial21285_stop_tx(port);
 157
 158  out:
 159         return IRQ_HANDLED;
 160 }
 161
 162 static unsigned int serial21285_tx_empty(struct uart_port *port)
 163 {
 164         return (*CSR_UARTFLG & 8) ? 0 : TIOCSER_TEMT;
 165 }
 166
 167 /* no modem control lines */
 168 static unsigned int serial21285_get_mctrl(struct uart_port *port)
 169 {
 170         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 171 }
 172
 173 static void serial21285_set_mctrl(struct uart_port *port, unsigned int mctrl)
 174 {
 175 }
 176
 177 static void serial21285_break_ctl(struct uart_port *port, int break_state)
 178 {
 179         unsigned long flags;
 180         unsigned int h_lcr;
 181
 182         spin_lock_irqsave(&port->lock, flags);
 183         h_lcr = *CSR_H_UBRLCR;
 184         if (break_state)
 185                 h_lcr |= H_UBRLCR_BREAK;
 186         else
 187                 h_lcr &= ~H_UBRLCR_BREAK;
 188         *CSR_H_UBRLCR = h_lcr;
 189         spin_unlock_irqrestore(&port->lock, flags);
 190 }
 191
 192 static int serial21285_startup(struct uart_port *port)
 193 {
 194         int ret;
 195
 196         tx_enabled(port) = 1;
 197         rx_enabled(port) = 1;
 198
 199         ret = request_irq(IRQ_CONRX, serial21285_rx_chars, 0,
 200                           serial21285_name, port);
 201         if (ret == 0) {
 202                 ret = request_irq(IRQ_CONTX, serial21285_tx_chars, 0,
 203                                   serial21285_name, port);
 204                 if (ret)
 205                         free_irq(IRQ_CONRX, port);
 206         }
 207
 208         return ret;
 209 }
 210
 211 static void serial21285_shutdown(struct uart_port *port)
 212 {
 213         free_irq(IRQ_CONTX, port);
 214         free_irq(IRQ_CONRX, port);
 215 }
 216
 217 static void
 218 serial21285_set_termios(struct uart_port *port, struct termios *termios,
 219                         struct termios *old)
 220 {
 221         unsigned long flags;
 222         unsigned int baud, quot, h_lcr;
 223
 224         /*
 225          * We don't support modem control lines.
 226          */
 227         termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
 228         termios->c_cflag |= CLOCAL;
 229
 230         /*
 231          * We don't support BREAK character recognition.
 232          */
 233         termios->c_iflag &= ~(IGNBRK | BRKINT);
 234
 235         /*
 236          * Ask the core to calculate the divisor for us.
 237          */
 238         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
 239         quot = uart_get_divisor(port, baud);
 240
 241         switch (termios->c_cflag & CSIZE) {
 242         case CS5:
 243                 h_lcr = 0x00;
 244                 break;
 245         case CS6:
 246                 h_lcr = 0x20;
 247                 break;
 248         case CS7:
 249                 h_lcr = 0x40;
 250                 break;
 251         default: /* CS8 */
 252                 h_lcr = 0x60;
 253                 break;
 254         }
 255
 256         if (termios->c_cflag & CSTOPB)
 257                 h_lcr |= H_UBRLCR_STOPB;
 258         if (termios->c_cflag & PARENB) {
 259                 h_lcr |= H_UBRLCR_PARENB;
 260                 if (!(termios->c_cflag & PARODD))
 261                         h_lcr |= H_UBRLCR_PAREVN;
 262         }
 263
 264         if (port->fifosize)
 265                 h_lcr |= H_UBRLCR_FIFO;
 266
 267         spin_lock_irqsave(&port->lock, flags);
 268
 269         /*
 270          * Update the per-port timeout.
 271          */
 272         uart_update_timeout(port, termios->c_cflag, baud);
 273
 274         /*
 275          * Which character status flags are we interested in?
 276          */
 277         port->read_status_mask = RXSTAT_OVERRUN;
 278         if (termios->c_iflag & INPCK)
 279                 port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
 280
 281         /*
 282          * Which character status flags should we ignore?
 283          */
 284         port->ignore_status_mask = 0;
 285         if (termios->c_iflag & IGNPAR)
 286                 port->ignore_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
 287         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
 288                 port->ignore_status_mask |= RXSTAT_OVERRUN;
 289
 290         /*
 291          * Ignore all characters if CREAD is not set.
 292          */
 293         if ((termios->c_cflag & CREAD) == 0)
 294                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
 295
 296         quot -= 1;
 297
 298         *CSR_UARTCON = 0;
 299         *CSR_L_UBRLCR = quot & 0xff;
 300         *CSR_M_UBRLCR = (quot >> 8) & 0x0f;
 301         *CSR_H_UBRLCR = h_lcr;
 302         *CSR_UARTCON = 1;
 303
 304         spin_unlock_irqrestore(&port->lock, flags);
 305 }
 306
 307 static const char *serial21285_type(struct uart_port *port)
 308 {
 309         return port->type == PORT_21285 ? "DC21285" : NULL;
 310 }
 311
 312 static void serial21285_release_port(struct uart_port *port)
 313 {
 314         release_mem_region(port->mapbase, 32);
 315 }
 316
 317 static int serial21285_request_port(struct uart_port *port)
 318 {
 319         return request_mem_region(port->mapbase, 32, serial21285_name)
 320                          != NULL ? 0 : -EBUSY;
 321 }
 322
 323 static void serial21285_config_port(struct uart_port *port, int flags)
 324 {
 325         if (flags & UART_CONFIG_TYPE && serial21285_request_port(port) == 0)
 326                 port->type = PORT_21285;
 327 }
 328
 329 /*
 330  * verify the new serial_struct (for TIOCSSERIAL).
 331  */
 332 static int serial21285_verify_port(struct uart_port *port, struct serial_struct *ser)
 333 {
 334         int ret = 0;
 335         if (ser->type != PORT_UNKNOWN && ser->type != PORT_21285)
 336                 ret = -EINVAL;
 337         if (ser->irq != NO_IRQ)
 338                 ret = -EINVAL;
 339         if (ser->baud_base != port->uartclk / 16)
 340                 ret = -EINVAL;
 341         return ret;
 342 }
 343
 344 static struct uart_ops serial21285_ops = {
 345         .tx_empty       = serial21285_tx_empty,
 346         .get_mctrl      = serial21285_get_mctrl,
 347         .set_mctrl      = serial21285_set_mctrl,
 348         .stop_tx        = serial21285_stop_tx,
 349         .start_tx       = serial21285_start_tx,
 350         .stop_rx        = serial21285_stop_rx,
 351         .enable_ms      = serial21285_enable_ms,
 352         .break_ctl      = serial21285_break_ctl,
 353         .startup        = serial21285_startup,
 354         .shutdown       = serial21285_shutdown,
 355         .set_termios    = serial21285_set_termios,
 356         .type           = serial21285_type,
 357         .release_port   = serial21285_release_port,
 358         .request_port   = serial21285_request_port,
 359         .config_port    = serial21285_config_port,
 360         .verify_port    = serial21285_verify_port,
 361 };
 362
 363 static struct uart_port serial21285_port = {
 364         .mapbase        = 0x42000160,
 365         .iotype         = UPIO_MEM,
 366         .irq            = NO_IRQ,
 367         .fifosize       = 16,
 368         .ops            = &serial21285_ops,
 369         .flags          = UPF_BOOT_AUTOCONF,
 370 };
 371
 372 static void serial21285_setup_ports(void)
 373 {
 374         serial21285_port.uartclk = mem_fclk_21285 / 4;
 375 }
 376
 377 #ifdef CONFIG_SERIAL_21285_CONSOLE
 378
 379 static void
 380 serial21285_console_write(struct console *co, const char *s,
 381                           unsigned int count)
 382 {
 383         int i;
 384
 385         for (i = 0; i < count; i++) {
 386                 while (*CSR_UARTFLG & 0x20)
 387                         barrier();
 388                 *CSR_UARTDR = s[i];
 389                 if (s[i] == '\n') {
 390                         while (*CSR_UARTFLG & 0x20)
 391                                 barrier();
 392                         *CSR_UARTDR = '\r';
 393                 }
 394         }
 395 }
 396
 397 static void __init
 398 serial21285_get_options(struct uart_port *port, int *baud,
 399                         int *parity, int *bits)
 400 {
 401         if (*CSR_UARTCON == 1) {
 402                 unsigned int tmp;
 403
 404                 tmp = *CSR_H_UBRLCR;
 405                 switch (tmp & 0x60) {
 406                 case 0x00:
 407                         *bits = 5;
 408                         break;
 409                 case 0x20:
 410                         *bits = 6;
 411                         break;
 412                 case 0x40:
 413                         *bits = 7;
 414                         break;
 415                 default:
 416                 case 0x60:
 417                         *bits = 8;
 418                         break;
 419                 }
 420
 421                 if (tmp & H_UBRLCR_PARENB) {
 422                         *parity = 'o';
 423                         if (tmp & H_UBRLCR_PAREVN)
 424                                 *parity = 'e';
 425                 }
 426
 427                 tmp = *CSR_L_UBRLCR | (*CSR_M_UBRLCR << 8);
 428
 429                 *baud = port->uartclk / (16 * (tmp + 1));
 430         }
 431 }
 432
 433 static int __init serial21285_console_setup(struct console *co, char *options)
 434 {
 435         struct uart_port *port = &serial21285_port;
 436         int baud = 9600;
 437         int bits = 8;
 438         int parity = 'n';
 439         int flow = 'n';
 440
 441         if (machine_is_personal_server())
 442                 baud = 57600;
 443
 444         /*
 445          * Check whether an invalid uart number has been specified, and
 446          * if so, search for the first available port that does have
 447          * console support.
 448          */
 449         if (options)
 450                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 451         else
 452                 serial21285_get_options(port, &baud, &parity, &bits);
 453
 454         return uart_set_options(port, co, baud, parity, bits, flow);
 455 }
 456
 457 static struct uart_driver serial21285_reg;
 458
 459 static struct console serial21285_console =
 460 {
 461         .name           = SERIAL_21285_NAME,
 462         .write          = serial21285_console_write,
 463         .device         = uart_console_device,
 464         .setup          = serial21285_console_setup,
 465         .flags          = CON_PRINTBUFFER,
 466         .index          = -1,
 467         .data           = &serial21285_reg,
 468 };
 469
 470 static int __init rs285_console_init(void)
 471 {
 472         serial21285_setup_ports();
 473         register_console(&serial21285_console);
 474         return 0;
 475 }
 476 console_initcall(rs285_console_init);
 477
 478 #define SERIAL_21285_CONSOLE    &serial21285_console
 479 #else
 480 #define SERIAL_21285_CONSOLE    NULL
 481 #endif
 482
 483 static struct uart_driver serial21285_reg = {
 484         .owner                  = THIS_MODULE,
 485         .driver_name            = "ttyFB",
 486         .dev_name               = "ttyFB",
 487         .devfs_name             = "ttyFB",
 488         .major                  = SERIAL_21285_MAJOR,
 489         .minor                  = SERIAL_21285_MINOR,
 490         .nr                     = 1,
 491         .cons                   = SERIAL_21285_CONSOLE,
 492 };
 493
 494 static int __init serial21285_init(void)
 495 {
 496         int ret;
 497
 498         printk(KERN_INFO "Serial: 21285 driver $Revision: 1.37 $\n");
 499
 500         serial21285_setup_ports();
 501
 502         ret = uart_register_driver(&serial21285_reg);
 503         if (ret == 0)
 504                 uart_add_one_port(&serial21285_reg, &serial21285_port);
 505
 506         return ret;
 507 }
 508
 509 static void __exit serial21285_exit(void)
 510 {
 511         uart_remove_one_port(&serial21285_reg, &serial21285_port);
 512         uart_unregister_driver(&serial21285_reg);
 513 }
 514
 515 module_init(serial21285_init);
 516 module_exit(serial21285_exit);
 517
 518 MODULE_LICENSE("GPL");
 519 MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver $Revision: 1.37 $");
 520 MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);