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[CPUFREQ] Fix the p4-clockmod N60 errata workaround.
[linux-2.6/mini2440.git] / drivers / scsi / sata_qstor.c
blob80480f0fb2b82abf2ebdcbe156abd994d9b9ff27
1 /*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 *
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/sched.h>
38 #include <linux/device.h>
39 #include <scsi/scsi_host.h>
40 #include <asm/io.h>
41 #include <linux/libata.h>
42
43 #define DRV_NAME "sata_qstor"
44 #define DRV_VERSION "0.05"
45
46 enum {
47 QS_PORTS = 4,
48 QS_MAX_PRD = LIBATA_MAX_PRD,
49 QS_CPB_ORDER = 6,
50 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
51 QS_PRD_BYTES = QS_MAX_PRD * 16,
52 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
53
54 /* global register offsets */
55 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
56 QS_HID_HPHY = 0x0004, /* host physical interface info */
57 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
58 QS_HST_SFF = 0x0100, /* host status fifo offset */
59 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
60
61 /* global control bits */
62 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
63 QS_CNFG3_GSRST = 0x01, /* global chip reset */
64 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
65
66 /* per-channel register offsets */
67 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
68 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
69 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
70 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
71 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
72 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
73 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
74 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
75 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
76
77 /* channel control bits */
78 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
79 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
80 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
81 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
82 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
83
84 /* pkt sub-field headers */
85 QS_HCB_HDR = 0x01, /* Host Control Block header */
86 QS_DCB_HDR = 0x02, /* Device Control Block header */
87
88 /* pkt HCB flag bits */
89 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
90 QS_HF_DAT = (1 << 3), /* DATa pkt */
91 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
92 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
93
94 /* pkt DCB flag bits */
95 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
96 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
97
98 /* PCI device IDs */
99 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
100 };
101
102 enum {
103 QS_DMA_BOUNDARY = ~0UL
104 };
105
106 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
107
108 struct qs_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 qs_state_t state;
112 };
113
114 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg);
115 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
116 static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
117 static irqreturn_t qs_intr (int irq, void *dev_instance, struct pt_regs *regs);
118 static int qs_port_start(struct ata_port *ap);
119 static void qs_host_stop(struct ata_host_set *host_set);
120 static void qs_port_stop(struct ata_port *ap);
121 static void qs_phy_reset(struct ata_port *ap);
122 static void qs_qc_prep(struct ata_queued_cmd *qc);
123 static int qs_qc_issue(struct ata_queued_cmd *qc);
124 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
125 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
126 static u8 qs_bmdma_status(struct ata_port *ap);
127 static void qs_irq_clear(struct ata_port *ap);
128 static void qs_eng_timeout(struct ata_port *ap);
129
130 static struct scsi_host_template qs_ata_sht = {
131 .module = THIS_MODULE,
132 .name = DRV_NAME,
133 .ioctl = ata_scsi_ioctl,
134 .queuecommand = ata_scsi_queuecmd,
135 .eh_strategy_handler = ata_scsi_error,
136 .can_queue = ATA_DEF_QUEUE,
137 .this_id = ATA_SHT_THIS_ID,
138 .sg_tablesize = QS_MAX_PRD,
139 .max_sectors = ATA_MAX_SECTORS,
140 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
141 .emulated = ATA_SHT_EMULATED,
142 //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING,
143 .use_clustering = ENABLE_CLUSTERING,
144 .proc_name = DRV_NAME,
145 .dma_boundary = QS_DMA_BOUNDARY,
146 .slave_configure = ata_scsi_slave_config,
147 .bios_param = ata_std_bios_param,
148 };
149
150 static const struct ata_port_operations qs_ata_ops = {
151 .port_disable = ata_port_disable,
152 .tf_load = ata_tf_load,
153 .tf_read = ata_tf_read,
154 .check_status = ata_check_status,
155 .check_atapi_dma = qs_check_atapi_dma,
156 .exec_command = ata_exec_command,
157 .dev_select = ata_std_dev_select,
158 .phy_reset = qs_phy_reset,
159 .qc_prep = qs_qc_prep,
160 .qc_issue = qs_qc_issue,
161 .eng_timeout = qs_eng_timeout,
162 .irq_handler = qs_intr,
163 .irq_clear = qs_irq_clear,
164 .scr_read = qs_scr_read,
165 .scr_write = qs_scr_write,
166 .port_start = qs_port_start,
167 .port_stop = qs_port_stop,
168 .host_stop = qs_host_stop,
169 .bmdma_stop = qs_bmdma_stop,
170 .bmdma_status = qs_bmdma_status,
171 };
172
173 static const struct ata_port_info qs_port_info[] = {
174 /* board_2068_idx */
175 {
176 .sht = &qs_ata_sht,
177 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
178 ATA_FLAG_SATA_RESET |
179 //FIXME ATA_FLAG_SRST |
180 ATA_FLAG_MMIO,
181 .pio_mask = 0x10, /* pio4 */
182 .udma_mask = 0x7f, /* udma0-6 */
183 .port_ops = &qs_ata_ops,
184 },
185 };
186
187 static const struct pci_device_id qs_ata_pci_tbl[] = {
188 { PCI_VENDOR_ID_PDC, 0x2068, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
189 board_2068_idx },
190
191 { } /* terminate list */
192 };
193
194 static struct pci_driver qs_ata_pci_driver = {
195 .name = DRV_NAME,
196 .id_table = qs_ata_pci_tbl,
197 .probe = qs_ata_init_one,
198 .remove = ata_pci_remove_one,
199 };
200
201 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
202 {
203 return 1; /* ATAPI DMA not supported */
204 }
205
206 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
207 {
208 /* nothing */
209 }
210
211 static u8 qs_bmdma_status(struct ata_port *ap)
212 {
213 return 0;
214 }
215
216 static void qs_irq_clear(struct ata_port *ap)
217 {
218 /* nothing */
219 }
220
221 static inline void qs_enter_reg_mode(struct ata_port *ap)
222 {
223 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
224
225 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
226 readb(chan + QS_CCT_CTR0); /* flush */
227 }
228
229 static inline void qs_reset_channel_logic(struct ata_port *ap)
230 {
231 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
232
233 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
234 readb(chan + QS_CCT_CTR0); /* flush */
235 qs_enter_reg_mode(ap);
236 }
237
238 static void qs_phy_reset(struct ata_port *ap)
239 {
240 struct qs_port_priv *pp = ap->private_data;
241
242 pp->state = qs_state_idle;
243 qs_reset_channel_logic(ap);
244 sata_phy_reset(ap);
245 }
246
247 static void qs_eng_timeout(struct ata_port *ap)
248 {
249 struct qs_port_priv *pp = ap->private_data;
250
251 if (pp->state != qs_state_idle) /* healthy paranoia */
252 pp->state = qs_state_mmio;
253 qs_reset_channel_logic(ap);
254 ata_eng_timeout(ap);
255 }
256
257 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg)
258 {
259 if (sc_reg > SCR_CONTROL)
260 return ~0U;
261 return readl((void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
262 }
263
264 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
265 {
266 if (sc_reg > SCR_CONTROL)
267 return;
268 writel(val, (void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
269 }
270
271 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
272 {
273 struct scatterlist *sg;
274 struct ata_port *ap = qc->ap;
275 struct qs_port_priv *pp = ap->private_data;
276 unsigned int nelem;
277 u8 *prd = pp->pkt + QS_CPB_BYTES;
278
279 assert(qc->__sg != NULL);
280 assert(qc->n_elem > 0 || qc->pad_len > 0);
281
282 nelem = 0;
283 ata_for_each_sg(sg, qc) {
284 u64 addr;
285 u32 len;
286
287 addr = sg_dma_address(sg);
288 *(__le64 *)prd = cpu_to_le64(addr);
289 prd += sizeof(u64);
290
291 len = sg_dma_len(sg);
292 *(__le32 *)prd = cpu_to_le32(len);
293 prd += sizeof(u64);
294
295 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
296 (unsigned long long)addr, len);
297 nelem++;
298 }
299
300 return nelem;
301 }
302
303 static void qs_qc_prep(struct ata_queued_cmd *qc)
304 {
305 struct qs_port_priv *pp = qc->ap->private_data;
306 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
307 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
308 u64 addr;
309 unsigned int nelem;
310
311 VPRINTK("ENTER\n");
312
313 qs_enter_reg_mode(qc->ap);
314 if (qc->tf.protocol != ATA_PROT_DMA) {
315 ata_qc_prep(qc);
316 return;
317 }
318
319 nelem = qs_fill_sg(qc);
320
321 if ((qc->tf.flags & ATA_TFLAG_WRITE))
322 hflags |= QS_HF_DIRO;
323 if ((qc->tf.flags & ATA_TFLAG_LBA48))
324 dflags |= QS_DF_ELBA;
325
326 /* host control block (HCB) */
327 buf[ 0] = QS_HCB_HDR;
328 buf[ 1] = hflags;
329 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nsect * ATA_SECT_SIZE);
330 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
331 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
332 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
333
334 /* device control block (DCB) */
335 buf[24] = QS_DCB_HDR;
336 buf[28] = dflags;
337
338 /* frame information structure (FIS) */
339 ata_tf_to_fis(&qc->tf, &buf[32], 0);
340 }
341
342 static inline void qs_packet_start(struct ata_queued_cmd *qc)
343 {
344 struct ata_port *ap = qc->ap;
345 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
346
347 VPRINTK("ENTER, ap %p\n", ap);
348
349 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
350 wmb(); /* flush PRDs and pkt to memory */
351 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
352 readl(chan + QS_CCT_CFF); /* flush */
353 }
354
355 static int qs_qc_issue(struct ata_queued_cmd *qc)
356 {
357 struct qs_port_priv *pp = qc->ap->private_data;
358
359 switch (qc->tf.protocol) {
360 case ATA_PROT_DMA:
361
362 pp->state = qs_state_pkt;
363 qs_packet_start(qc);
364 return 0;
365
366 case ATA_PROT_ATAPI_DMA:
367 BUG();
368 break;
369
370 default:
371 break;
372 }
373
374 pp->state = qs_state_mmio;
375 return ata_qc_issue_prot(qc);
376 }
377
378 static inline unsigned int qs_intr_pkt(struct ata_host_set *host_set)
379 {
380 unsigned int handled = 0;
381 u8 sFFE;
382 u8 __iomem *mmio_base = host_set->mmio_base;
383
384 do {
385 u32 sff0 = readl(mmio_base + QS_HST_SFF);
386 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
387 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
388 sFFE = sff1 >> 31; /* empty flag */
389
390 if (sEVLD) {
391 u8 sDST = sff0 >> 16; /* dev status */
392 u8 sHST = sff1 & 0x3f; /* host status */
393 unsigned int port_no = (sff1 >> 8) & 0x03;
394 struct ata_port *ap = host_set->ports[port_no];
395
396 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
397 sff1, sff0, port_no, sHST, sDST);
398 handled = 1;
399 if (ap && !(ap->flags &
400 (ATA_FLAG_PORT_DISABLED|ATA_FLAG_NOINTR))) {
401 struct ata_queued_cmd *qc;
402 struct qs_port_priv *pp = ap->private_data;
403 if (!pp || pp->state != qs_state_pkt)
404 continue;
405 qc = ata_qc_from_tag(ap, ap->active_tag);
406 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
407 switch (sHST) {
408 case 0: /* successful CPB */
409 case 3: /* device error */
410 pp->state = qs_state_idle;
411 qs_enter_reg_mode(qc->ap);
412 qc->err_mask |= ac_err_mask(sDST);
413 ata_qc_complete(qc);
414 break;
415 default:
416 break;
417 }
418 }
419 }
420 }
421 } while (!sFFE);
422 return handled;
423 }
424
425 static inline unsigned int qs_intr_mmio(struct ata_host_set *host_set)
426 {
427 unsigned int handled = 0, port_no;
428
429 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
430 struct ata_port *ap;
431 ap = host_set->ports[port_no];
432 if (ap &&
433 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
434 struct ata_queued_cmd *qc;
435 struct qs_port_priv *pp = ap->private_data;
436 if (!pp || pp->state != qs_state_mmio)
437 continue;
438 qc = ata_qc_from_tag(ap, ap->active_tag);
439 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
440
441 /* check main status, clearing INTRQ */
442 u8 status = ata_check_status(ap);
443 if ((status & ATA_BUSY))
444 continue;
445 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
446 ap->id, qc->tf.protocol, status);
447
448 /* complete taskfile transaction */
449 pp->state = qs_state_idle;
450 qc->err_mask |= ac_err_mask(status);
451 ata_qc_complete(qc);
452 handled = 1;
453 }
454 }
455 }
456 return handled;
457 }
458
459 static irqreturn_t qs_intr(int irq, void *dev_instance, struct pt_regs *regs)
460 {
461 struct ata_host_set *host_set = dev_instance;
462 unsigned int handled = 0;
463
464 VPRINTK("ENTER\n");
465
466 spin_lock(&host_set->lock);
467 handled = qs_intr_pkt(host_set) | qs_intr_mmio(host_set);
468 spin_unlock(&host_set->lock);
469
470 VPRINTK("EXIT\n");
471
472 return IRQ_RETVAL(handled);
473 }
474
475 static void qs_ata_setup_port(struct ata_ioports *port, unsigned long base)
476 {
477 port->cmd_addr =
478 port->data_addr = base + 0x400;
479 port->error_addr =
480 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
481 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
482 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
483 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
484 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
485 port->device_addr = base + 0x430;
486 port->status_addr =
487 port->command_addr = base + 0x438;
488 port->altstatus_addr =
489 port->ctl_addr = base + 0x440;
490 port->scr_addr = base + 0xc00;
491 }
492
493 static int qs_port_start(struct ata_port *ap)
494 {
495 struct device *dev = ap->host_set->dev;
496 struct qs_port_priv *pp;
497 void __iomem *mmio_base = ap->host_set->mmio_base;
498 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
499 u64 addr;
500 int rc;
501
502 rc = ata_port_start(ap);
503 if (rc)
504 return rc;
505 qs_enter_reg_mode(ap);
506 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
507 if (!pp) {
508 rc = -ENOMEM;
509 goto err_out;
510 }
511 pp->pkt = dma_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
512 GFP_KERNEL);
513 if (!pp->pkt) {
514 rc = -ENOMEM;
515 goto err_out_kfree;
516 }
517 memset(pp->pkt, 0, QS_PKT_BYTES);
518 ap->private_data = pp;
519
520 addr = (u64)pp->pkt_dma;
521 writel((u32) addr, chan + QS_CCF_CPBA);
522 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
523 return 0;
524
525 err_out_kfree:
526 kfree(pp);
527 err_out:
528 ata_port_stop(ap);
529 return rc;
530 }
531
532 static void qs_port_stop(struct ata_port *ap)
533 {
534 struct device *dev = ap->host_set->dev;
535 struct qs_port_priv *pp = ap->private_data;
536
537 if (pp != NULL) {
538 ap->private_data = NULL;
539 if (pp->pkt != NULL)
540 dma_free_coherent(dev, QS_PKT_BYTES, pp->pkt,
541 pp->pkt_dma);
542 kfree(pp);
543 }
544 ata_port_stop(ap);
545 }
546
547 static void qs_host_stop(struct ata_host_set *host_set)
548 {
549 void __iomem *mmio_base = host_set->mmio_base;
550 struct pci_dev *pdev = to_pci_dev(host_set->dev);
551
552 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
553 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
554
555 pci_iounmap(pdev, mmio_base);
556 }
557
558 static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
559 {
560 void __iomem *mmio_base = pe->mmio_base;
561 unsigned int port_no;
562
563 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
564 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
565
566 /* reset each channel in turn */
567 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
568 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
569 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
570 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
571 readb(chan + QS_CCT_CTR0); /* flush */
572 }
573 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
574
575 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
576 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
577 /* set FIFO depths to same settings as Windows driver */
578 writew(32, chan + QS_CFC_HUFT);
579 writew(32, chan + QS_CFC_HDFT);
580 writew(10, chan + QS_CFC_DUFT);
581 writew( 8, chan + QS_CFC_DDFT);
582 /* set CPB size in bytes, as a power of two */
583 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
584 }
585 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
586 }
587
588 /*
589 * The QStor understands 64-bit buses, and uses 64-bit fields
590 * for DMA pointers regardless of bus width. We just have to
591 * make sure our DMA masks are set appropriately for whatever
592 * bridge lies between us and the QStor, and then the DMA mapping
593 * code will ensure we only ever "see" appropriate buffer addresses.
594 * If we're 32-bit limited somewhere, then our 64-bit fields will
595 * just end up with zeros in the upper 32-bits, without any special
596 * logic required outside of this routine (below).
597 */
598 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
599 {
600 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
601 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
602
603 if (have_64bit_bus &&
604 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
605 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
606 if (rc) {
607 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
608 if (rc) {
609 dev_printk(KERN_ERR, &pdev->dev,
610 "64-bit DMA enable failed\n");
611 return rc;
612 }
613 }
614 } else {
615 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
616 if (rc) {
617 dev_printk(KERN_ERR, &pdev->dev,
618 "32-bit DMA enable failed\n");
619 return rc;
620 }
621 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
622 if (rc) {
623 dev_printk(KERN_ERR, &pdev->dev,
624 "32-bit consistent DMA enable failed\n");
625 return rc;
626 }
627 }
628 return 0;
629 }
630
631 static int qs_ata_init_one(struct pci_dev *pdev,
632 const struct pci_device_id *ent)
633 {
634 static int printed_version;
635 struct ata_probe_ent *probe_ent = NULL;
636 void __iomem *mmio_base;
637 unsigned int board_idx = (unsigned int) ent->driver_data;
638 int rc, port_no;
639
640 if (!printed_version++)
641 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
642
643 rc = pci_enable_device(pdev);
644 if (rc)
645 return rc;
646
647 rc = pci_request_regions(pdev, DRV_NAME);
648 if (rc)
649 goto err_out;
650
651 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
652 rc = -ENODEV;
653 goto err_out_regions;
654 }
655
656 mmio_base = pci_iomap(pdev, 4, 0);
657 if (mmio_base == NULL) {
658 rc = -ENOMEM;
659 goto err_out_regions;
660 }
661
662 rc = qs_set_dma_masks(pdev, mmio_base);
663 if (rc)
664 goto err_out_iounmap;
665
666 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
667 if (probe_ent == NULL) {
668 rc = -ENOMEM;
669 goto err_out_iounmap;
670 }
671
672 memset(probe_ent, 0, sizeof(*probe_ent));
673 probe_ent->dev = pci_dev_to_dev(pdev);
674 INIT_LIST_HEAD(&probe_ent->node);
675
676 probe_ent->sht = qs_port_info[board_idx].sht;
677 probe_ent->host_flags = qs_port_info[board_idx].host_flags;
678 probe_ent->pio_mask = qs_port_info[board_idx].pio_mask;
679 probe_ent->mwdma_mask = qs_port_info[board_idx].mwdma_mask;
680 probe_ent->udma_mask = qs_port_info[board_idx].udma_mask;
681 probe_ent->port_ops = qs_port_info[board_idx].port_ops;
682
683 probe_ent->irq = pdev->irq;
684 probe_ent->irq_flags = SA_SHIRQ;
685 probe_ent->mmio_base = mmio_base;
686 probe_ent->n_ports = QS_PORTS;
687
688 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
689 unsigned long chan = (unsigned long)mmio_base +
690 (port_no * 0x4000);
691 qs_ata_setup_port(&probe_ent->port[port_no], chan);
692 }
693
694 pci_set_master(pdev);
695
696 /* initialize adapter */
697 qs_host_init(board_idx, probe_ent);
698
699 rc = ata_device_add(probe_ent);
700 kfree(probe_ent);
701 if (rc != QS_PORTS)
702 goto err_out_iounmap;
703 return 0;
704
705 err_out_iounmap:
706 pci_iounmap(pdev, mmio_base);
707 err_out_regions:
708 pci_release_regions(pdev);
709 err_out:
710 pci_disable_device(pdev);
711 return rc;
712 }
713
714 static int __init qs_ata_init(void)
715 {
716 return pci_module_init(&qs_ata_pci_driver);
717 }
718
719 static void __exit qs_ata_exit(void)
720 {
721 pci_unregister_driver(&qs_ata_pci_driver);
722 }
723
724 MODULE_AUTHOR("Mark Lord");
725 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
726 MODULE_LICENSE("GPL");
727 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
728 MODULE_VERSION(DRV_VERSION);
729
730 module_init(qs_ata_init);
731 module_exit(qs_ata_exit);
Support for the Chinese Samsung S3C2440 based development boards