arch/sh/kernel/timers/timer-cmt.c

   1 /*
   2  * arch/sh/kernel/timers/timer-cmt.c - CMT Timer Support
   3  *
   4  *  Copyright (C) 2005  Yoshinori Sato
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/seqlock.h>
  15 #include <asm/timer.h>
  16 #include <asm/rtc.h>
  17 #include <asm/io.h>
  18 #include <asm/irq.h>
  19 #include <asm/clock.h>
  20
  21 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
  22 #define CMT_CMSTR       0xf84a0070
  23 #define CMT_CMCSR_0     0xf84a0072
  24 #define CMT_CMCNT_0     0xf84a0074
  25 #define CMT_CMCOR_0     0xf84a0076
  26 #define CMT_CMCSR_1     0xf84a0078
  27 #define CMT_CMCNT_1     0xf84a007a
  28 #define CMT_CMCOR_1     0xf84a007c
  29
  30 #define STBCR3          0xf80a0000
  31 #define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0)
  32 #define CMT_CMCSR_INIT  0x0040
  33 #define CMT_CMCSR_CALIB 0x0000
  34 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || defined(CONFIG_CPU_SUBTYPE_SH7206)
  35 #define CMT_CMSTR       0xfffec000
  36 #define CMT_CMCSR_0     0xfffec002
  37 #define CMT_CMCNT_0     0xfffec004
  38 #define CMT_CMCOR_0     0xfffec006
  39
  40 #define STBCR4          0xfffe040c
  41 #define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR4) & ~0x04, STBCR4); } while(0)
  42 #define CMT_CMCSR_INIT  0x0040
  43 #define CMT_CMCSR_CALIB 0x0000
  44 #else
  45 #error "Unknown CPU SUBTYPE"
  46 #endif
  47
  48 static unsigned long cmt_timer_get_offset(void)
  49 {
  50         int count;
  51         static unsigned short count_p = 0xffff;    /* for the first call after boot */
  52         static unsigned long jiffies_p = 0;
  53
  54         /*
  55          * cache volatile jiffies temporarily; we have IRQs turned off.
  56          */
  57         unsigned long jiffies_t;
  58
  59         /* timer count may underflow right here */
  60         count =  ctrl_inw(CMT_CMCOR_0);
  61         count -= ctrl_inw(CMT_CMCNT_0);
  62
  63         jiffies_t = jiffies;
  64
  65         /*
  66          * avoiding timer inconsistencies (they are rare, but they happen)...
  67          * there is one kind of problem that must be avoided here:
  68          *  1. the timer counter underflows
  69          */
  70
  71         if (jiffies_t == jiffies_p) {
  72                 if (count > count_p) {
  73                         /* the nutcase */
  74                         if (ctrl_inw(CMT_CMCSR_0) & 0x80) { /* Check CMF bit */
  75                                 count -= LATCH;
  76                         } else {
  77                                 printk("%s (): hardware timer problem?\n",
  78                                        __FUNCTION__);
  79                         }
  80                 }
  81         } else
  82                 jiffies_p = jiffies_t;
  83
  84         count_p = count;
  85
  86         count = ((LATCH-1) - count) * TICK_SIZE;
  87         count = (count + LATCH/2) / LATCH;
  88
  89         return count;
  90 }
  91
  92 static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id)
  93 {
  94         unsigned long timer_status;
  95
  96         /* Clear CMF bit */
  97         timer_status = ctrl_inw(CMT_CMCSR_0);
  98         timer_status &= ~0x80;
  99         ctrl_outw(timer_status, CMT_CMCSR_0);
 100
 101         /*
 102          * Here we are in the timer irq handler. We just have irqs locally
 103          * disabled but we don't know if the timer_bh is running on the other
 104          * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
 105          * the irq version of write_lock because as just said we have irq
 106          * locally disabled. -arca
 107          */
 108         write_seqlock(&xtime_lock);
 109         handle_timer_tick();
 110         write_sequnlock(&xtime_lock);
 111
 112         return IRQ_HANDLED;
 113 }
 114
 115 static struct irqaction cmt_irq = {
 116         .name           = "timer",
 117         .handler        = cmt_timer_interrupt,
 118         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 119         .mask           = CPU_MASK_NONE,
 120 };
 121
 122 static void cmt_clk_init(struct clk *clk)
 123 {
 124         u8 divisor = CMT_CMCSR_INIT & 0x3;
 125         ctrl_inw(CMT_CMCSR_0);
 126         ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0);
 127         clk->parent = clk_get(NULL, "module_clk");
 128         clk->rate = clk->parent->rate / (8 << (divisor << 1));
 129 }
 130
 131 static void cmt_clk_recalc(struct clk *clk)
 132 {
 133         u8 divisor = ctrl_inw(CMT_CMCSR_0) & 0x3;
 134         clk->rate = clk->parent->rate / (8 << (divisor << 1));
 135 }
 136
 137 static struct clk_ops cmt_clk_ops = {
 138         .init           = cmt_clk_init,
 139         .recalc         = cmt_clk_recalc,
 140 };
 141
 142 static struct clk cmt0_clk = {
 143         .name           = "cmt0_clk",
 144         .ops            = &cmt_clk_ops,
 145 };
 146
 147 static int cmt_timer_start(void)
 148 {
 149         ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
 150         return 0;
 151 }
 152
 153 static int cmt_timer_stop(void)
 154 {
 155         ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR);
 156         return 0;
 157 }
 158
 159 static int cmt_timer_init(void)
 160 {
 161         unsigned long interval;
 162
 163         cmt_clock_enable();
 164
 165         setup_irq(CONFIG_SH_TIMER_IRQ, &cmt_irq);
 166
 167         cmt0_clk.parent = clk_get(NULL, "module_clk");
 168
 169         cmt_timer_stop();
 170
 171         interval = cmt0_clk.parent->rate / 8 / HZ;
 172         printk(KERN_INFO "Interval = %ld\n", interval);
 173
 174         ctrl_outw(interval, CMT_CMCOR_0);
 175
 176         clk_register(&cmt0_clk);
 177         clk_enable(&cmt0_clk);
 178
 179         cmt_timer_start();
 180
 181         return 0;
 182 }
 183
 184 struct sys_timer_ops cmt_timer_ops = {
 185         .init           = cmt_timer_init,
 186         .start          = cmt_timer_start,
 187         .stop           = cmt_timer_stop,
 188 #ifndef CONFIG_GENERIC_TIME
 189         .get_offset     = cmt_timer_get_offset,
 190 #endif
 191 };
 192
 193 struct sys_timer cmt_timer = {
 194         .name   = "cmt",
 195         .ops    = &cmt_timer_ops,
 196 };