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PCI: PCIE ASPM support
[linux-2.6/mini2440.git] / drivers / pci / probe.c
blob9b4673df27e7bb122c3e323d523c33893ee2d8f9
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/aspm.h>
13 #include "pci.h"
14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17 #define PCI_CFG_SPACE_SIZE 256
18 #define PCI_CFG_SPACE_EXP_SIZE 4096
19
20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses);
22 EXPORT_SYMBOL(pci_root_buses);
23
24 LIST_HEAD(pci_devices);
25
26 /*
27 * Some device drivers need know if pci is initiated.
28 * Basically, we think pci is not initiated when there
29 * is no device in list of pci_devices.
30 */
31 int no_pci_devices(void)
32 {
33 return list_empty(&pci_devices);
34 }
35
36 EXPORT_SYMBOL(no_pci_devices);
37
38 #ifdef HAVE_PCI_LEGACY
39 /**
40 * pci_create_legacy_files - create legacy I/O port and memory files
41 * @b: bus to create files under
42 *
43 * Some platforms allow access to legacy I/O port and ISA memory space on
44 * a per-bus basis. This routine creates the files and ties them into
45 * their associated read, write and mmap files from pci-sysfs.c
46 */
47 static void pci_create_legacy_files(struct pci_bus *b)
48 {
49 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
50 GFP_ATOMIC);
51 if (b->legacy_io) {
52 b->legacy_io->attr.name = "legacy_io";
53 b->legacy_io->size = 0xffff;
54 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
55 b->legacy_io->read = pci_read_legacy_io;
56 b->legacy_io->write = pci_write_legacy_io;
57 class_device_create_bin_file(&b->class_dev, b->legacy_io);
58
59 /* Allocated above after the legacy_io struct */
60 b->legacy_mem = b->legacy_io + 1;
61 b->legacy_mem->attr.name = "legacy_mem";
62 b->legacy_mem->size = 1024*1024;
63 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
64 b->legacy_mem->mmap = pci_mmap_legacy_mem;
65 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
66 }
67 }
68
69 void pci_remove_legacy_files(struct pci_bus *b)
70 {
71 if (b->legacy_io) {
72 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
73 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
74 kfree(b->legacy_io); /* both are allocated here */
75 }
76 }
77 #else /* !HAVE_PCI_LEGACY */
78 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
79 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
80 #endif /* HAVE_PCI_LEGACY */
81
82 /*
83 * PCI Bus Class Devices
84 */
85 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
86 char *buf)
87 {
88 int ret;
89 cpumask_t cpumask;
90
91 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
92 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
93 if (ret < PAGE_SIZE)
94 buf[ret++] = '\n';
95 return ret;
96 }
97 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
98
99 /*
100 * PCI Bus Class
101 */
102 static void release_pcibus_dev(struct class_device *class_dev)
103 {
104 struct pci_bus *pci_bus = to_pci_bus(class_dev);
105
106 if (pci_bus->bridge)
107 put_device(pci_bus->bridge);
108 kfree(pci_bus);
109 }
110
111 static struct class pcibus_class = {
112 .name = "pci_bus",
113 .release = &release_pcibus_dev,
114 };
115
116 static int __init pcibus_class_init(void)
117 {
118 return class_register(&pcibus_class);
119 }
120 postcore_initcall(pcibus_class_init);
121
122 /*
123 * Translate the low bits of the PCI base
124 * to the resource type
125 */
126 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
127 {
128 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
129 return IORESOURCE_IO;
130
131 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
132 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
133
134 return IORESOURCE_MEM;
135 }
136
137 /*
138 * Find the extent of a PCI decode..
139 */
140 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
141 {
142 u32 size = mask & maxbase; /* Find the significant bits */
143 if (!size)
144 return 0;
145
146 /* Get the lowest of them to find the decode size, and
147 from that the extent. */
148 size = (size & ~(size-1)) - 1;
149
150 /* base == maxbase can be valid only if the BAR has
151 already been programmed with all 1s. */
152 if (base == maxbase && ((base | size) & mask) != mask)
153 return 0;
154
155 return size;
156 }
157
158 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
159 {
160 u64 size = mask & maxbase; /* Find the significant bits */
161 if (!size)
162 return 0;
163
164 /* Get the lowest of them to find the decode size, and
165 from that the extent. */
166 size = (size & ~(size-1)) - 1;
167
168 /* base == maxbase can be valid only if the BAR has
169 already been programmed with all 1s. */
170 if (base == maxbase && ((base | size) & mask) != mask)
171 return 0;
172
173 return size;
174 }
175
176 static inline int is_64bit_memory(u32 mask)
177 {
178 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
179 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
180 return 1;
181 return 0;
182 }
183
184 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
185 {
186 unsigned int pos, reg, next;
187 u32 l, sz;
188 struct resource *res;
189
190 for(pos=0; pos<howmany; pos = next) {
191 u64 l64;
192 u64 sz64;
193 u32 raw_sz;
194
195 next = pos+1;
196 res = &dev->resource[pos];
197 res->name = pci_name(dev);
198 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
199 pci_read_config_dword(dev, reg, &l);
200 pci_write_config_dword(dev, reg, ~0);
201 pci_read_config_dword(dev, reg, &sz);
202 pci_write_config_dword(dev, reg, l);
203 if (!sz || sz == 0xffffffff)
204 continue;
205 if (l == 0xffffffff)
206 l = 0;
207 raw_sz = sz;
208 if ((l & PCI_BASE_ADDRESS_SPACE) ==
209 PCI_BASE_ADDRESS_SPACE_MEMORY) {
210 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
211 /*
212 * For 64bit prefetchable memory sz could be 0, if the
213 * real size is bigger than 4G, so we need to check
214 * szhi for that.
215 */
216 if (!is_64bit_memory(l) && !sz)
217 continue;
218 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
219 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
220 } else {
221 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
222 if (!sz)
223 continue;
224 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
225 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
226 }
227 res->end = res->start + (unsigned long) sz;
228 res->flags |= pci_calc_resource_flags(l);
229 if (is_64bit_memory(l)) {
230 u32 szhi, lhi;
231
232 pci_read_config_dword(dev, reg+4, &lhi);
233 pci_write_config_dword(dev, reg+4, ~0);
234 pci_read_config_dword(dev, reg+4, &szhi);
235 pci_write_config_dword(dev, reg+4, lhi);
236 sz64 = ((u64)szhi << 32) | raw_sz;
237 l64 = ((u64)lhi << 32) | l;
238 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
239 next++;
240 #if BITS_PER_LONG == 64
241 if (!sz64) {
242 res->start = 0;
243 res->end = 0;
244 res->flags = 0;
245 continue;
246 }
247 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
248 res->end = res->start + sz64;
249 #else
250 if (sz64 > 0x100000000ULL) {
251 printk(KERN_ERR "PCI: Unable to handle 64-bit "
252 "BAR for device %s\n", pci_name(dev));
253 res->start = 0;
254 res->flags = 0;
255 } else if (lhi) {
256 /* 64-bit wide address, treat as disabled */
257 pci_write_config_dword(dev, reg,
258 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
259 pci_write_config_dword(dev, reg+4, 0);
260 res->start = 0;
261 res->end = sz;
262 }
263 #endif
264 }
265 }
266 if (rom) {
267 dev->rom_base_reg = rom;
268 res = &dev->resource[PCI_ROM_RESOURCE];
269 res->name = pci_name(dev);
270 pci_read_config_dword(dev, rom, &l);
271 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
272 pci_read_config_dword(dev, rom, &sz);
273 pci_write_config_dword(dev, rom, l);
274 if (l == 0xffffffff)
275 l = 0;
276 if (sz && sz != 0xffffffff) {
277 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
278 if (sz) {
279 res->flags = (l & IORESOURCE_ROM_ENABLE) |
280 IORESOURCE_MEM | IORESOURCE_PREFETCH |
281 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
282 res->start = l & PCI_ROM_ADDRESS_MASK;
283 res->end = res->start + (unsigned long) sz;
284 }
285 }
286 }
287 }
288
289 void pci_read_bridge_bases(struct pci_bus *child)
290 {
291 struct pci_dev *dev = child->self;
292 u8 io_base_lo, io_limit_lo;
293 u16 mem_base_lo, mem_limit_lo;
294 unsigned long base, limit;
295 struct resource *res;
296 int i;
297
298 if (!dev) /* It's a host bus, nothing to read */
299 return;
300
301 if (dev->transparent) {
302 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
303 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
304 child->resource[i] = child->parent->resource[i - 3];
305 }
306
307 for(i=0; i<3; i++)
308 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
309
310 res = child->resource[0];
311 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
312 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
313 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
314 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
315
316 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
317 u16 io_base_hi, io_limit_hi;
318 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
319 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
320 base |= (io_base_hi << 16);
321 limit |= (io_limit_hi << 16);
322 }
323
324 if (base <= limit) {
325 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
326 if (!res->start)
327 res->start = base;
328 if (!res->end)
329 res->end = limit + 0xfff;
330 }
331
332 res = child->resource[1];
333 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
334 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
335 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
336 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
337 if (base <= limit) {
338 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
339 res->start = base;
340 res->end = limit + 0xfffff;
341 }
342
343 res = child->resource[2];
344 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
345 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
346 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
347 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
348
349 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
350 u32 mem_base_hi, mem_limit_hi;
351 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
352 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
353
354 /*
355 * Some bridges set the base > limit by default, and some
356 * (broken) BIOSes do not initialize them. If we find
357 * this, just assume they are not being used.
358 */
359 if (mem_base_hi <= mem_limit_hi) {
360 #if BITS_PER_LONG == 64
361 base |= ((long) mem_base_hi) << 32;
362 limit |= ((long) mem_limit_hi) << 32;
363 #else
364 if (mem_base_hi || mem_limit_hi) {
365 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
366 return;
367 }
368 #endif
369 }
370 }
371 if (base <= limit) {
372 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
373 res->start = base;
374 res->end = limit + 0xfffff;
375 }
376 }
377
378 static struct pci_bus * pci_alloc_bus(void)
379 {
380 struct pci_bus *b;
381
382 b = kzalloc(sizeof(*b), GFP_KERNEL);
383 if (b) {
384 INIT_LIST_HEAD(&b->node);
385 INIT_LIST_HEAD(&b->children);
386 INIT_LIST_HEAD(&b->devices);
387 }
388 return b;
389 }
390
391 static struct pci_bus * __devinit
392 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
393 {
394 struct pci_bus *child;
395 int i;
396 int retval;
397
398 /*
399 * Allocate a new bus, and inherit stuff from the parent..
400 */
401 child = pci_alloc_bus();
402 if (!child)
403 return NULL;
404
405 child->self = bridge;
406 child->parent = parent;
407 child->ops = parent->ops;
408 child->sysdata = parent->sysdata;
409 child->bus_flags = parent->bus_flags;
410 child->bridge = get_device(&bridge->dev);
411
412 child->class_dev.class = &pcibus_class;
413 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
414 retval = class_device_register(&child->class_dev);
415 if (retval)
416 goto error_register;
417 retval = class_device_create_file(&child->class_dev,
418 &class_device_attr_cpuaffinity);
419 if (retval)
420 goto error_file_create;
421
422 /*
423 * Set up the primary, secondary and subordinate
424 * bus numbers.
425 */
426 child->number = child->secondary = busnr;
427 child->primary = parent->secondary;
428 child->subordinate = 0xff;
429
430 /* Set up default resource pointers and names.. */
431 for (i = 0; i < 4; i++) {
432 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
433 child->resource[i]->name = child->name;
434 }
435 bridge->subordinate = child;
436
437 return child;
438
439 error_file_create:
440 class_device_unregister(&child->class_dev);
441 error_register:
442 kfree(child);
443 return NULL;
444 }
445
446 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
447 {
448 struct pci_bus *child;
449
450 child = pci_alloc_child_bus(parent, dev, busnr);
451 if (child) {
452 down_write(&pci_bus_sem);
453 list_add_tail(&child->node, &parent->children);
454 up_write(&pci_bus_sem);
455 }
456 return child;
457 }
458
459 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
460 {
461 struct pci_bus *parent = child->parent;
462
463 /* Attempts to fix that up are really dangerous unless
464 we're going to re-assign all bus numbers. */
465 if (!pcibios_assign_all_busses())
466 return;
467
468 while (parent->parent && parent->subordinate < max) {
469 parent->subordinate = max;
470 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
471 parent = parent->parent;
472 }
473 }
474
475 /*
476 * If it's a bridge, configure it and scan the bus behind it.
477 * For CardBus bridges, we don't scan behind as the devices will
478 * be handled by the bridge driver itself.
479 *
480 * We need to process bridges in two passes -- first we scan those
481 * already configured by the BIOS and after we are done with all of
482 * them, we proceed to assigning numbers to the remaining buses in
483 * order to avoid overlaps between old and new bus numbers.
484 */
485 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
486 {
487 struct pci_bus *child;
488 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
489 u32 buses, i, j = 0;
490 u16 bctl;
491
492 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
493
494 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
495 pci_name(dev), buses & 0xffffff, pass);
496
497 /* Disable MasterAbortMode during probing to avoid reporting
498 of bus errors (in some architectures) */
499 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
500 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
501 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
502
503 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
504 unsigned int cmax, busnr;
505 /*
506 * Bus already configured by firmware, process it in the first
507 * pass and just note the configuration.
508 */
509 if (pass)
510 goto out;
511 busnr = (buses >> 8) & 0xFF;
512
513 /*
514 * If we already got to this bus through a different bridge,
515 * ignore it. This can happen with the i450NX chipset.
516 */
517 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
518 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
519 pci_domain_nr(bus), busnr);
520 goto out;
521 }
522
523 child = pci_add_new_bus(bus, dev, busnr);
524 if (!child)
525 goto out;
526 child->primary = buses & 0xFF;
527 child->subordinate = (buses >> 16) & 0xFF;
528 child->bridge_ctl = bctl;
529
530 cmax = pci_scan_child_bus(child);
531 if (cmax > max)
532 max = cmax;
533 if (child->subordinate > max)
534 max = child->subordinate;
535 } else {
536 /*
537 * We need to assign a number to this bus which we always
538 * do in the second pass.
539 */
540 if (!pass) {
541 if (pcibios_assign_all_busses())
542 /* Temporarily disable forwarding of the
543 configuration cycles on all bridges in
544 this bus segment to avoid possible
545 conflicts in the second pass between two
546 bridges programmed with overlapping
547 bus ranges. */
548 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
549 buses & ~0xffffff);
550 goto out;
551 }
552
553 /* Clear errors */
554 pci_write_config_word(dev, PCI_STATUS, 0xffff);
555
556 /* Prevent assigning a bus number that already exists.
557 * This can happen when a bridge is hot-plugged */
558 if (pci_find_bus(pci_domain_nr(bus), max+1))
559 goto out;
560 child = pci_add_new_bus(bus, dev, ++max);
561 buses = (buses & 0xff000000)
562 | ((unsigned int)(child->primary) << 0)
563 | ((unsigned int)(child->secondary) << 8)
564 | ((unsigned int)(child->subordinate) << 16);
565
566 /*
567 * yenta.c forces a secondary latency timer of 176.
568 * Copy that behaviour here.
569 */
570 if (is_cardbus) {
571 buses &= ~0xff000000;
572 buses |= CARDBUS_LATENCY_TIMER << 24;
573 }
574
575 /*
576 * We need to blast all three values with a single write.
577 */
578 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
579
580 if (!is_cardbus) {
581 child->bridge_ctl = bctl;
582 /*
583 * Adjust subordinate busnr in parent buses.
584 * We do this before scanning for children because
585 * some devices may not be detected if the bios
586 * was lazy.
587 */
588 pci_fixup_parent_subordinate_busnr(child, max);
589 /* Now we can scan all subordinate buses... */
590 max = pci_scan_child_bus(child);
591 /*
592 * now fix it up again since we have found
593 * the real value of max.
594 */
595 pci_fixup_parent_subordinate_busnr(child, max);
596 } else {
597 /*
598 * For CardBus bridges, we leave 4 bus numbers
599 * as cards with a PCI-to-PCI bridge can be
600 * inserted later.
601 */
602 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
603 struct pci_bus *parent = bus;
604 if (pci_find_bus(pci_domain_nr(bus),
605 max+i+1))
606 break;
607 while (parent->parent) {
608 if ((!pcibios_assign_all_busses()) &&
609 (parent->subordinate > max) &&
610 (parent->subordinate <= max+i)) {
611 j = 1;
612 }
613 parent = parent->parent;
614 }
615 if (j) {
616 /*
617 * Often, there are two cardbus bridges
618 * -- try to leave one valid bus number
619 * for each one.
620 */
621 i /= 2;
622 break;
623 }
624 }
625 max += i;
626 pci_fixup_parent_subordinate_busnr(child, max);
627 }
628 /*
629 * Set the subordinate bus number to its real value.
630 */
631 child->subordinate = max;
632 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
633 }
634
635 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
636
637 /* Has only triggered on CardBus, fixup is in yenta_socket */
638 while (bus->parent) {
639 if ((child->subordinate > bus->subordinate) ||
640 (child->number > bus->subordinate) ||
641 (child->number < bus->number) ||
642 (child->subordinate < bus->number)) {
643 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
644 "hidden behind%s bridge #%02x (-#%02x)\n",
645 child->number, child->subordinate,
646 (bus->number > child->subordinate &&
647 bus->subordinate < child->number) ?
648 "wholly" : "partially",
649 bus->self->transparent ? " transparent" : "",
650 bus->number, bus->subordinate);
651 }
652 bus = bus->parent;
653 }
654
655 out:
656 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
657
658 return max;
659 }
660
661 /*
662 * Read interrupt line and base address registers.
663 * The architecture-dependent code can tweak these, of course.
664 */
665 static void pci_read_irq(struct pci_dev *dev)
666 {
667 unsigned char irq;
668
669 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
670 dev->pin = irq;
671 if (irq)
672 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
673 dev->irq = irq;
674 }
675
676 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
677
678 /**
679 * pci_setup_device - fill in class and map information of a device
680 * @dev: the device structure to fill
681 *
682 * Initialize the device structure with information about the device's
683 * vendor,class,memory and IO-space addresses,IRQ lines etc.
684 * Called at initialisation of the PCI subsystem and by CardBus services.
685 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
686 * or CardBus).
687 */
688 static int pci_setup_device(struct pci_dev * dev)
689 {
690 u32 class;
691
692 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
693 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
694
695 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
696 dev->revision = class & 0xff;
697 class >>= 8; /* upper 3 bytes */
698 dev->class = class;
699 class >>= 8;
700
701 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
702 dev->vendor, dev->device, class, dev->hdr_type);
703
704 /* "Unknown power state" */
705 dev->current_state = PCI_UNKNOWN;
706
707 /* Early fixups, before probing the BARs */
708 pci_fixup_device(pci_fixup_early, dev);
709 class = dev->class >> 8;
710
711 switch (dev->hdr_type) { /* header type */
712 case PCI_HEADER_TYPE_NORMAL: /* standard header */
713 if (class == PCI_CLASS_BRIDGE_PCI)
714 goto bad;
715 pci_read_irq(dev);
716 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
717 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
718 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
719
720 /*
721 * Do the ugly legacy mode stuff here rather than broken chip
722 * quirk code. Legacy mode ATA controllers have fixed
723 * addresses. These are not always echoed in BAR0-3, and
724 * BAR0-3 in a few cases contain junk!
725 */
726 if (class == PCI_CLASS_STORAGE_IDE) {
727 u8 progif;
728 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
729 if ((progif & 1) == 0) {
730 dev->resource[0].start = 0x1F0;
731 dev->resource[0].end = 0x1F7;
732 dev->resource[0].flags = LEGACY_IO_RESOURCE;
733 dev->resource[1].start = 0x3F6;
734 dev->resource[1].end = 0x3F6;
735 dev->resource[1].flags = LEGACY_IO_RESOURCE;
736 }
737 if ((progif & 4) == 0) {
738 dev->resource[2].start = 0x170;
739 dev->resource[2].end = 0x177;
740 dev->resource[2].flags = LEGACY_IO_RESOURCE;
741 dev->resource[3].start = 0x376;
742 dev->resource[3].end = 0x376;
743 dev->resource[3].flags = LEGACY_IO_RESOURCE;
744 }
745 }
746 break;
747
748 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
749 if (class != PCI_CLASS_BRIDGE_PCI)
750 goto bad;
751 /* The PCI-to-PCI bridge spec requires that subtractive
752 decoding (i.e. transparent) bridge must have programming
753 interface code of 0x01. */
754 pci_read_irq(dev);
755 dev->transparent = ((dev->class & 0xff) == 1);
756 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
757 break;
758
759 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
760 if (class != PCI_CLASS_BRIDGE_CARDBUS)
761 goto bad;
762 pci_read_irq(dev);
763 pci_read_bases(dev, 1, 0);
764 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
765 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
766 break;
767
768 default: /* unknown header */
769 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
770 pci_name(dev), dev->hdr_type);
771 return -1;
772
773 bad:
774 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
775 pci_name(dev), class, dev->hdr_type);
776 dev->class = PCI_CLASS_NOT_DEFINED;
777 }
778
779 /* We found a fine healthy device, go go go... */
780 return 0;
781 }
782
783 /**
784 * pci_release_dev - free a pci device structure when all users of it are finished.
785 * @dev: device that's been disconnected
786 *
787 * Will be called only by the device core when all users of this pci device are
788 * done.
789 */
790 static void pci_release_dev(struct device *dev)
791 {
792 struct pci_dev *pci_dev;
793
794 pci_dev = to_pci_dev(dev);
795 kfree(pci_dev);
796 }
797
798 static void set_pcie_port_type(struct pci_dev *pdev)
799 {
800 int pos;
801 u16 reg16;
802
803 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
804 if (!pos)
805 return;
806 pdev->is_pcie = 1;
807 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
808 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
809 }
810
811 /**
812 * pci_cfg_space_size - get the configuration space size of the PCI device.
813 * @dev: PCI device
814 *
815 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
816 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
817 * access it. Maybe we don't have a way to generate extended config space
818 * accesses, or the device is behind a reverse Express bridge. So we try
819 * reading the dword at 0x100 which must either be 0 or a valid extended
820 * capability header.
821 */
822 int pci_cfg_space_size(struct pci_dev *dev)
823 {
824 int pos;
825 u32 status;
826
827 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
828 if (!pos) {
829 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
830 if (!pos)
831 goto fail;
832
833 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
834 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
835 goto fail;
836 }
837
838 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
839 goto fail;
840 if (status == 0xffffffff)
841 goto fail;
842
843 return PCI_CFG_SPACE_EXP_SIZE;
844
845 fail:
846 return PCI_CFG_SPACE_SIZE;
847 }
848
849 static void pci_release_bus_bridge_dev(struct device *dev)
850 {
851 kfree(dev);
852 }
853
854 struct pci_dev *alloc_pci_dev(void)
855 {
856 struct pci_dev *dev;
857
858 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
859 if (!dev)
860 return NULL;
861
862 INIT_LIST_HEAD(&dev->global_list);
863 INIT_LIST_HEAD(&dev->bus_list);
864
865 pci_msi_init_pci_dev(dev);
866
867 return dev;
868 }
869 EXPORT_SYMBOL(alloc_pci_dev);
870
871 /*
872 * Read the config data for a PCI device, sanity-check it
873 * and fill in the dev structure...
874 */
875 static struct pci_dev * __devinit
876 pci_scan_device(struct pci_bus *bus, int devfn)
877 {
878 struct pci_dev *dev;
879 u32 l;
880 u8 hdr_type;
881 int delay = 1;
882
883 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
884 return NULL;
885
886 /* some broken boards return 0 or ~0 if a slot is empty: */
887 if (l == 0xffffffff || l == 0x00000000 ||
888 l == 0x0000ffff || l == 0xffff0000)
889 return NULL;
890
891 /* Configuration request Retry Status */
892 while (l == 0xffff0001) {
893 msleep(delay);
894 delay *= 2;
895 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
896 return NULL;
897 /* Card hasn't responded in 60 seconds? Must be stuck. */
898 if (delay > 60 * 1000) {
899 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
900 "responding\n", pci_domain_nr(bus),
901 bus->number, PCI_SLOT(devfn),
902 PCI_FUNC(devfn));
903 return NULL;
904 }
905 }
906
907 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
908 return NULL;
909
910 dev = alloc_pci_dev();
911 if (!dev)
912 return NULL;
913
914 dev->bus = bus;
915 dev->sysdata = bus->sysdata;
916 dev->dev.parent = bus->bridge;
917 dev->dev.bus = &pci_bus_type;
918 dev->devfn = devfn;
919 dev->hdr_type = hdr_type & 0x7f;
920 dev->multifunction = !!(hdr_type & 0x80);
921 dev->vendor = l & 0xffff;
922 dev->device = (l >> 16) & 0xffff;
923 dev->cfg_size = pci_cfg_space_size(dev);
924 dev->error_state = pci_channel_io_normal;
925 set_pcie_port_type(dev);
926
927 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
928 set this higher, assuming the system even supports it. */
929 dev->dma_mask = 0xffffffff;
930 if (pci_setup_device(dev) < 0) {
931 kfree(dev);
932 return NULL;
933 }
934
935 return dev;
936 }
937
938 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
939 {
940 device_initialize(&dev->dev);
941 dev->dev.release = pci_release_dev;
942 pci_dev_get(dev);
943
944 set_dev_node(&dev->dev, pcibus_to_node(bus));
945 dev->dev.dma_mask = &dev->dma_mask;
946 dev->dev.coherent_dma_mask = 0xffffffffull;
947
948 /* Fix up broken headers */
949 pci_fixup_device(pci_fixup_header, dev);
950
951 /*
952 * Add the device to our list of discovered devices
953 * and the bus list for fixup functions, etc.
954 */
955 INIT_LIST_HEAD(&dev->global_list);
956 down_write(&pci_bus_sem);
957 list_add_tail(&dev->bus_list, &bus->devices);
958 up_write(&pci_bus_sem);
959 }
960
961 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
962 {
963 struct pci_dev *dev;
964
965 dev = pci_scan_device(bus, devfn);
966 if (!dev)
967 return NULL;
968
969 pci_device_add(dev, bus);
970
971 return dev;
972 }
973 EXPORT_SYMBOL(pci_scan_single_device);
974
975 /**
976 * pci_scan_slot - scan a PCI slot on a bus for devices.
977 * @bus: PCI bus to scan
978 * @devfn: slot number to scan (must have zero function.)
979 *
980 * Scan a PCI slot on the specified PCI bus for devices, adding
981 * discovered devices to the @bus->devices list. New devices
982 * will have an empty dev->global_list head.
983 */
984 int pci_scan_slot(struct pci_bus *bus, int devfn)
985 {
986 int func, nr = 0;
987 int scan_all_fns;
988
989 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
990
991 for (func = 0; func < 8; func++, devfn++) {
992 struct pci_dev *dev;
993
994 dev = pci_scan_single_device(bus, devfn);
995 if (dev) {
996 nr++;
997
998 /*
999 * If this is a single function device,
1000 * don't scan past the first function.
1001 */
1002 if (!dev->multifunction) {
1003 if (func > 0) {
1004 dev->multifunction = 1;
1005 } else {
1006 break;
1007 }
1008 }
1009 } else {
1010 if (func == 0 && !scan_all_fns)
1011 break;
1012 }
1013 }
1014
1015 if (bus->self)
1016 pcie_aspm_init_link_state(bus->self);
1017
1018 return nr;
1019 }
1020
1021 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1022 {
1023 unsigned int devfn, pass, max = bus->secondary;
1024 struct pci_dev *dev;
1025
1026 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1027
1028 /* Go find them, Rover! */
1029 for (devfn = 0; devfn < 0x100; devfn += 8)
1030 pci_scan_slot(bus, devfn);
1031
1032 /*
1033 * After performing arch-dependent fixup of the bus, look behind
1034 * all PCI-to-PCI bridges on this bus.
1035 */
1036 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1037 pcibios_fixup_bus(bus);
1038 for (pass=0; pass < 2; pass++)
1039 list_for_each_entry(dev, &bus->devices, bus_list) {
1040 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1041 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1042 max = pci_scan_bridge(bus, dev, max, pass);
1043 }
1044
1045 /*
1046 * We've scanned the bus and so we know all about what's on
1047 * the other side of any bridges that may be on this bus plus
1048 * any devices.
1049 *
1050 * Return how far we've got finding sub-buses.
1051 */
1052 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1053 pci_domain_nr(bus), bus->number, max);
1054 return max;
1055 }
1056
1057 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
1058 {
1059 unsigned int max;
1060
1061 max = pci_scan_child_bus(bus);
1062
1063 /*
1064 * Make the discovered devices available.
1065 */
1066 pci_bus_add_devices(bus);
1067
1068 return max;
1069 }
1070
1071 struct pci_bus * pci_create_bus(struct device *parent,
1072 int bus, struct pci_ops *ops, void *sysdata)
1073 {
1074 int error;
1075 struct pci_bus *b;
1076 struct device *dev;
1077
1078 b = pci_alloc_bus();
1079 if (!b)
1080 return NULL;
1081
1082 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1083 if (!dev){
1084 kfree(b);
1085 return NULL;
1086 }
1087
1088 b->sysdata = sysdata;
1089 b->ops = ops;
1090
1091 if (pci_find_bus(pci_domain_nr(b), bus)) {
1092 /* If we already got to this bus through a different bridge, ignore it */
1093 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1094 goto err_out;
1095 }
1096
1097 down_write(&pci_bus_sem);
1098 list_add_tail(&b->node, &pci_root_buses);
1099 up_write(&pci_bus_sem);
1100
1101 memset(dev, 0, sizeof(*dev));
1102 dev->parent = parent;
1103 dev->release = pci_release_bus_bridge_dev;
1104 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1105 error = device_register(dev);
1106 if (error)
1107 goto dev_reg_err;
1108 b->bridge = get_device(dev);
1109
1110 b->class_dev.class = &pcibus_class;
1111 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
1112 error = class_device_register(&b->class_dev);
1113 if (error)
1114 goto class_dev_reg_err;
1115 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
1116 if (error)
1117 goto class_dev_create_file_err;
1118
1119 /* Create legacy_io and legacy_mem files for this bus */
1120 pci_create_legacy_files(b);
1121
1122 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1123 if (error)
1124 goto sys_create_link_err;
1125
1126 b->number = b->secondary = bus;
1127 b->resource[0] = &ioport_resource;
1128 b->resource[1] = &iomem_resource;
1129
1130 return b;
1131
1132 sys_create_link_err:
1133 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1134 class_dev_create_file_err:
1135 class_device_unregister(&b->class_dev);
1136 class_dev_reg_err:
1137 device_unregister(dev);
1138 dev_reg_err:
1139 down_write(&pci_bus_sem);
1140 list_del(&b->node);
1141 up_write(&pci_bus_sem);
1142 err_out:
1143 kfree(dev);
1144 kfree(b);
1145 return NULL;
1146 }
1147
1148 struct pci_bus *pci_scan_bus_parented(struct device *parent,
1149 int bus, struct pci_ops *ops, void *sysdata)
1150 {
1151 struct pci_bus *b;
1152
1153 b = pci_create_bus(parent, bus, ops, sysdata);
1154 if (b)
1155 b->subordinate = pci_scan_child_bus(b);
1156 return b;
1157 }
1158 EXPORT_SYMBOL(pci_scan_bus_parented);
1159
1160 #ifdef CONFIG_HOTPLUG
1161 EXPORT_SYMBOL(pci_add_new_bus);
1162 EXPORT_SYMBOL(pci_do_scan_bus);
1163 EXPORT_SYMBOL(pci_scan_slot);
1164 EXPORT_SYMBOL(pci_scan_bridge);
1165 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1166 #endif
1167
1168 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1169 {
1170 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1171 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1172
1173 if (a->bus->number < b->bus->number) return -1;
1174 else if (a->bus->number > b->bus->number) return 1;
1175
1176 if (a->devfn < b->devfn) return -1;
1177 else if (a->devfn > b->devfn) return 1;
1178
1179 return 0;
1180 }
1181
1182 /*
1183 * Yes, this forcably breaks the klist abstraction temporarily. It
1184 * just wants to sort the klist, not change reference counts and
1185 * take/drop locks rapidly in the process. It does all this while
1186 * holding the lock for the list, so objects can't otherwise be
1187 * added/removed while we're swizzling.
1188 */
1189 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1190 {
1191 struct list_head *pos;
1192 struct klist_node *n;
1193 struct device *dev;
1194 struct pci_dev *b;
1195
1196 list_for_each(pos, list) {
1197 n = container_of(pos, struct klist_node, n_node);
1198 dev = container_of(n, struct device, knode_bus);
1199 b = to_pci_dev(dev);
1200 if (pci_sort_bf_cmp(a, b) <= 0) {
1201 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1202 return;
1203 }
1204 }
1205 list_move_tail(&a->dev.knode_bus.n_node, list);
1206 }
1207
1208 static void __init pci_sort_breadthfirst_klist(void)
1209 {
1210 LIST_HEAD(sorted_devices);
1211 struct list_head *pos, *tmp;
1212 struct klist_node *n;
1213 struct device *dev;
1214 struct pci_dev *pdev;
1215 struct klist *device_klist;
1216
1217 device_klist = bus_get_device_klist(&pci_bus_type);
1218
1219 spin_lock(&device_klist->k_lock);
1220 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1221 n = container_of(pos, struct klist_node, n_node);
1222 dev = container_of(n, struct device, knode_bus);
1223 pdev = to_pci_dev(dev);
1224 pci_insertion_sort_klist(pdev, &sorted_devices);
1225 }
1226 list_splice(&sorted_devices, &device_klist->k_list);
1227 spin_unlock(&device_klist->k_lock);
1228 }
1229
1230 static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list)
1231 {
1232 struct pci_dev *b;
1233
1234 list_for_each_entry(b, list, global_list) {
1235 if (pci_sort_bf_cmp(a, b) <= 0) {
1236 list_move_tail(&a->global_list, &b->global_list);
1237 return;
1238 }
1239 }
1240 list_move_tail(&a->global_list, list);
1241 }
1242
1243 static void __init pci_sort_breadthfirst_devices(void)
1244 {
1245 LIST_HEAD(sorted_devices);
1246 struct pci_dev *dev, *tmp;
1247
1248 down_write(&pci_bus_sem);
1249 list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) {
1250 pci_insertion_sort_devices(dev, &sorted_devices);
1251 }
1252 list_splice(&sorted_devices, &pci_devices);
1253 up_write(&pci_bus_sem);
1254 }
1255
1256 void __init pci_sort_breadthfirst(void)
1257 {
1258 pci_sort_breadthfirst_devices();
1259 pci_sort_breadthfirst_klist();
1260 }
1261
Support for the Chinese Samsung S3C2440 based development boards