2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
17 #include <linux/module.h>
18 #include <linux/spinlock.h>
19 #include <linux/string.h>
20 #include <linux/log2.h>
21 #include <linux/aspm.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
25 unsigned int pci_pm_d3_delay
= 10;
27 #ifdef CONFIG_PCI_DOMAINS
28 int pci_domains_supported
= 1;
31 #define DEFAULT_CARDBUS_IO_SIZE (256)
32 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
33 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
34 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
35 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
38 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
39 * @bus: pointer to PCI bus structure to search
41 * Given a PCI bus, returns the highest PCI bus number present in the set
42 * including the given PCI bus and its list of child PCI buses.
44 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
46 struct list_head
*tmp
;
49 max
= bus
->subordinate
;
50 list_for_each(tmp
, &bus
->children
) {
51 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
57 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
61 * pci_max_busnr - returns maximum PCI bus number
63 * Returns the highest PCI bus number present in the system global list of
66 unsigned char __devinit
69 struct pci_bus
*bus
= NULL
;
73 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
74 n
= pci_bus_max_busnr(bus
);
83 #define PCI_FIND_CAP_TTL 48
85 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
86 u8 pos
, int cap
, int *ttl
)
91 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
95 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
101 pos
+= PCI_CAP_LIST_NEXT
;
106 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
109 int ttl
= PCI_FIND_CAP_TTL
;
111 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
114 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
116 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
117 pos
+ PCI_CAP_LIST_NEXT
, cap
);
119 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
121 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
122 unsigned int devfn
, u8 hdr_type
)
126 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
127 if (!(status
& PCI_STATUS_CAP_LIST
))
131 case PCI_HEADER_TYPE_NORMAL
:
132 case PCI_HEADER_TYPE_BRIDGE
:
133 return PCI_CAPABILITY_LIST
;
134 case PCI_HEADER_TYPE_CARDBUS
:
135 return PCI_CB_CAPABILITY_LIST
;
144 * pci_find_capability - query for devices' capabilities
145 * @dev: PCI device to query
146 * @cap: capability code
148 * Tell if a device supports a given PCI capability.
149 * Returns the address of the requested capability structure within the
150 * device's PCI configuration space or 0 in case the device does not
151 * support it. Possible values for @cap:
153 * %PCI_CAP_ID_PM Power Management
154 * %PCI_CAP_ID_AGP Accelerated Graphics Port
155 * %PCI_CAP_ID_VPD Vital Product Data
156 * %PCI_CAP_ID_SLOTID Slot Identification
157 * %PCI_CAP_ID_MSI Message Signalled Interrupts
158 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
159 * %PCI_CAP_ID_PCIX PCI-X
160 * %PCI_CAP_ID_EXP PCI Express
162 int pci_find_capability(struct pci_dev
*dev
, int cap
)
166 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
168 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
174 * pci_bus_find_capability - query for devices' capabilities
175 * @bus: the PCI bus to query
176 * @devfn: PCI device to query
177 * @cap: capability code
179 * Like pci_find_capability() but works for pci devices that do not have a
180 * pci_dev structure set up yet.
182 * Returns the address of the requested capability structure within the
183 * device's PCI configuration space or 0 in case the device does not
186 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
191 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
193 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
195 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
201 * pci_find_ext_capability - Find an extended capability
202 * @dev: PCI device to query
203 * @cap: capability code
205 * Returns the address of the requested extended capability structure
206 * within the device's PCI configuration space or 0 if the device does
207 * not support it. Possible values for @cap:
209 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
210 * %PCI_EXT_CAP_ID_VC Virtual Channel
211 * %PCI_EXT_CAP_ID_DSN Device Serial Number
212 * %PCI_EXT_CAP_ID_PWR Power Budgeting
214 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
217 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
220 if (dev
->cfg_size
<= 256)
223 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
227 * If we have no capabilities, this is indicated by cap ID,
228 * cap version and next pointer all being 0.
234 if (PCI_EXT_CAP_ID(header
) == cap
)
237 pos
= PCI_EXT_CAP_NEXT(header
);
241 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
247 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
249 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
251 int rc
, ttl
= PCI_FIND_CAP_TTL
;
254 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
255 mask
= HT_3BIT_CAP_MASK
;
257 mask
= HT_5BIT_CAP_MASK
;
259 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
260 PCI_CAP_ID_HT
, &ttl
);
262 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
263 if (rc
!= PCIBIOS_SUCCESSFUL
)
266 if ((cap
& mask
) == ht_cap
)
269 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
270 pos
+ PCI_CAP_LIST_NEXT
,
271 PCI_CAP_ID_HT
, &ttl
);
277 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
278 * @dev: PCI device to query
279 * @pos: Position from which to continue searching
280 * @ht_cap: Hypertransport capability code
282 * To be used in conjunction with pci_find_ht_capability() to search for
283 * all capabilities matching @ht_cap. @pos should always be a value returned
284 * from pci_find_ht_capability().
286 * NB. To be 100% safe against broken PCI devices, the caller should take
287 * steps to avoid an infinite loop.
289 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
291 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
293 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
296 * pci_find_ht_capability - query a device's Hypertransport capabilities
297 * @dev: PCI device to query
298 * @ht_cap: Hypertransport capability code
300 * Tell if a device supports a given Hypertransport capability.
301 * Returns an address within the device's PCI configuration space
302 * or 0 in case the device does not support the request capability.
303 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
304 * which has a Hypertransport capability matching @ht_cap.
306 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
310 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
312 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
316 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
318 void pcie_wait_pending_transaction(struct pci_dev
*dev
)
323 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
327 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, ®16
);
328 if (!(reg16
& PCI_EXP_DEVSTA_TRPND
))
334 EXPORT_SYMBOL_GPL(pcie_wait_pending_transaction
);
337 * pci_find_parent_resource - return resource region of parent bus of given region
338 * @dev: PCI device structure contains resources to be searched
339 * @res: child resource record for which parent is sought
341 * For given resource region of given device, return the resource
342 * region of parent bus the given region is contained in or where
343 * it should be allocated from.
346 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
348 const struct pci_bus
*bus
= dev
->bus
;
350 struct resource
*best
= NULL
;
352 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
353 struct resource
*r
= bus
->resource
[i
];
356 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
357 continue; /* Not contained */
358 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
359 continue; /* Wrong type */
360 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
361 return r
; /* Exact match */
362 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
363 best
= r
; /* Approximating prefetchable by non-prefetchable */
369 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
370 * @dev: PCI device to have its BARs restored
372 * Restore the BAR values for a given device, so as to make it
373 * accessible by its driver.
376 pci_restore_bars(struct pci_dev
*dev
)
380 switch (dev
->hdr_type
) {
381 case PCI_HEADER_TYPE_NORMAL
:
384 case PCI_HEADER_TYPE_BRIDGE
:
387 case PCI_HEADER_TYPE_CARDBUS
:
391 /* Should never get here, but just in case... */
395 for (i
= 0; i
< numres
; i
++)
396 pci_update_resource(dev
, &dev
->resource
[i
], i
);
399 int (*platform_pci_set_power_state
)(struct pci_dev
*dev
, pci_power_t t
);
402 * pci_set_power_state - Set the power state of a PCI device
403 * @dev: PCI device to be suspended
404 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
406 * Transition a device to a new power state, using the Power Management
407 * Capabilities in the device's config space.
410 * -EINVAL if trying to enter a lower state than we're already in.
411 * 0 if we're already in the requested state.
412 * -EIO if device does not support PCI PM.
413 * 0 if we can successfully change the power state.
416 pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
418 int pm
, need_restore
= 0;
421 /* bound the state we're entering */
422 if (state
> PCI_D3hot
)
426 * If the device or the parent bridge can't support PCI PM, ignore
427 * the request if we're doing anything besides putting it into D0
428 * (which would only happen on boot).
430 if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
433 /* find PCI PM capability in list */
434 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
436 /* abort if the device doesn't support PM capabilities */
440 /* Validate current state:
441 * Can enter D0 from any state, but if we can only go deeper
442 * to sleep if we're already in a low power state
444 if (state
!= PCI_D0
&& dev
->current_state
> state
) {
445 printk(KERN_ERR
"%s(): %s: state=%d, current state=%d\n",
446 __FUNCTION__
, pci_name(dev
), state
, dev
->current_state
);
448 } else if (dev
->current_state
== state
)
449 return 0; /* we're already there */
452 pci_read_config_word(dev
,pm
+ PCI_PM_PMC
,&pmc
);
453 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
455 "PCI: %s has unsupported PM cap regs version (%u)\n",
456 pci_name(dev
), pmc
& PCI_PM_CAP_VER_MASK
);
460 /* check if this device supports the desired state */
461 if (state
== PCI_D1
&& !(pmc
& PCI_PM_CAP_D1
))
463 else if (state
== PCI_D2
&& !(pmc
& PCI_PM_CAP_D2
))
466 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
468 /* If we're (effectively) in D3, force entire word to 0.
469 * This doesn't affect PME_Status, disables PME_En, and
470 * sets PowerState to 0.
472 switch (dev
->current_state
) {
476 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
479 case PCI_UNKNOWN
: /* Boot-up */
480 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
481 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
483 /* Fall-through: force to D0 */
489 /* enter specified state */
490 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, pmcsr
);
492 /* Mandatory power management transition delays */
493 /* see PCI PM 1.1 5.6.1 table 18 */
494 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
495 msleep(pci_pm_d3_delay
);
496 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
500 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
501 * Firmware method after native method ?
503 if (platform_pci_set_power_state
)
504 platform_pci_set_power_state(dev
, state
);
506 dev
->current_state
= state
;
508 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
509 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
510 * from D3hot to D0 _may_ perform an internal reset, thereby
511 * going to "D0 Uninitialized" rather than "D0 Initialized".
512 * For example, at least some versions of the 3c905B and the
513 * 3c556B exhibit this behaviour.
515 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
516 * devices in a D3hot state at boot. Consequently, we need to
517 * restore at least the BARs so that the device will be
518 * accessible to its driver.
521 pci_restore_bars(dev
);
524 pcie_aspm_pm_state_change(dev
->bus
->self
);
529 pci_power_t (*platform_pci_choose_state
)(struct pci_dev
*dev
, pm_message_t state
);
532 * pci_choose_state - Choose the power state of a PCI device
533 * @dev: PCI device to be suspended
534 * @state: target sleep state for the whole system. This is the value
535 * that is passed to suspend() function.
537 * Returns PCI power state suitable for given device and given system
541 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
545 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
548 if (platform_pci_choose_state
) {
549 ret
= platform_pci_choose_state(dev
, state
);
550 if (ret
!= PCI_POWER_ERROR
)
554 switch (state
.event
) {
557 case PM_EVENT_FREEZE
:
558 case PM_EVENT_PRETHAW
:
559 /* REVISIT both freeze and pre-thaw "should" use D0 */
560 case PM_EVENT_SUSPEND
:
563 printk("Unrecognized suspend event %d\n", state
.event
);
569 EXPORT_SYMBOL(pci_choose_state
);
571 static int pci_save_pcie_state(struct pci_dev
*dev
)
574 struct pci_cap_saved_state
*save_state
;
578 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
582 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
584 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
) * 4, GFP_KERNEL
);
588 dev_err(&dev
->dev
, "Out of memory in pci_save_pcie_state\n");
591 cap
= (u16
*)&save_state
->data
[0];
593 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
594 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
595 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
596 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
597 save_state
->cap_nr
= PCI_CAP_ID_EXP
;
599 pci_add_saved_cap(dev
, save_state
);
603 static void pci_restore_pcie_state(struct pci_dev
*dev
)
606 struct pci_cap_saved_state
*save_state
;
609 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
610 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
611 if (!save_state
|| pos
<= 0)
613 cap
= (u16
*)&save_state
->data
[0];
615 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
616 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
617 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
618 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
622 static int pci_save_pcix_state(struct pci_dev
*dev
)
625 struct pci_cap_saved_state
*save_state
;
629 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
633 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
635 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
), GFP_KERNEL
);
639 dev_err(&dev
->dev
, "Out of memory in pci_save_pcie_state\n");
642 cap
= (u16
*)&save_state
->data
[0];
644 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, &cap
[i
++]);
645 save_state
->cap_nr
= PCI_CAP_ID_PCIX
;
647 pci_add_saved_cap(dev
, save_state
);
651 static void pci_restore_pcix_state(struct pci_dev
*dev
)
654 struct pci_cap_saved_state
*save_state
;
657 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
658 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
659 if (!save_state
|| pos
<= 0)
661 cap
= (u16
*)&save_state
->data
[0];
663 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
668 * pci_save_state - save the PCI configuration space of a device before suspending
669 * @dev: - PCI device that we're dealing with
672 pci_save_state(struct pci_dev
*dev
)
675 /* XXX: 100% dword access ok here? */
676 for (i
= 0; i
< 16; i
++)
677 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
678 if ((i
= pci_save_pcie_state(dev
)) != 0)
680 if ((i
= pci_save_pcix_state(dev
)) != 0)
686 * pci_restore_state - Restore the saved state of a PCI device
687 * @dev: - PCI device that we're dealing with
690 pci_restore_state(struct pci_dev
*dev
)
695 /* PCI Express register must be restored first */
696 pci_restore_pcie_state(dev
);
699 * The Base Address register should be programmed before the command
702 for (i
= 15; i
>= 0; i
--) {
703 pci_read_config_dword(dev
, i
* 4, &val
);
704 if (val
!= dev
->saved_config_space
[i
]) {
705 printk(KERN_DEBUG
"PM: Writing back config space on "
706 "device %s at offset %x (was %x, writing %x)\n",
708 val
, (int)dev
->saved_config_space
[i
]);
709 pci_write_config_dword(dev
,i
* 4,
710 dev
->saved_config_space
[i
]);
713 pci_restore_pcix_state(dev
);
714 pci_restore_msi_state(dev
);
719 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
723 err
= pci_set_power_state(dev
, PCI_D0
);
724 if (err
< 0 && err
!= -EIO
)
726 err
= pcibios_enable_device(dev
, bars
);
729 pci_fixup_device(pci_fixup_enable
, dev
);
735 * pci_reenable_device - Resume abandoned device
736 * @dev: PCI device to be resumed
738 * Note this function is a backend of pci_default_resume and is not supposed
739 * to be called by normal code, write proper resume handler and use it instead.
741 int pci_reenable_device(struct pci_dev
*dev
)
743 if (atomic_read(&dev
->enable_cnt
))
744 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
748 static int __pci_enable_device_flags(struct pci_dev
*dev
,
749 resource_size_t flags
)
754 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
755 return 0; /* already enabled */
757 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
758 if (dev
->resource
[i
].flags
& flags
)
761 err
= do_pci_enable_device(dev
, bars
);
763 atomic_dec(&dev
->enable_cnt
);
768 * pci_enable_device_io - Initialize a device for use with IO space
769 * @dev: PCI device to be initialized
771 * Initialize device before it's used by a driver. Ask low-level code
772 * to enable I/O resources. Wake up the device if it was suspended.
773 * Beware, this function can fail.
775 int pci_enable_device_io(struct pci_dev
*dev
)
777 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
781 * pci_enable_device_mem - Initialize a device for use with Memory space
782 * @dev: PCI device to be initialized
784 * Initialize device before it's used by a driver. Ask low-level code
785 * to enable Memory resources. Wake up the device if it was suspended.
786 * Beware, this function can fail.
788 int pci_enable_device_mem(struct pci_dev
*dev
)
790 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
794 * pci_enable_device - Initialize device before it's used by a driver.
795 * @dev: PCI device to be initialized
797 * Initialize device before it's used by a driver. Ask low-level code
798 * to enable I/O and memory. Wake up the device if it was suspended.
799 * Beware, this function can fail.
801 * Note we don't actually enable the device many times if we call
802 * this function repeatedly (we just increment the count).
804 int pci_enable_device(struct pci_dev
*dev
)
806 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
810 * Managed PCI resources. This manages device on/off, intx/msi/msix
811 * on/off and BAR regions. pci_dev itself records msi/msix status, so
812 * there's no need to track it separately. pci_devres is initialized
813 * when a device is enabled using managed PCI device enable interface.
816 unsigned int enabled
:1;
817 unsigned int pinned
:1;
818 unsigned int orig_intx
:1;
819 unsigned int restore_intx
:1;
823 static void pcim_release(struct device
*gendev
, void *res
)
825 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
826 struct pci_devres
*this = res
;
829 if (dev
->msi_enabled
)
830 pci_disable_msi(dev
);
831 if (dev
->msix_enabled
)
832 pci_disable_msix(dev
);
834 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
835 if (this->region_mask
& (1 << i
))
836 pci_release_region(dev
, i
);
838 if (this->restore_intx
)
839 pci_intx(dev
, this->orig_intx
);
841 if (this->enabled
&& !this->pinned
)
842 pci_disable_device(dev
);
845 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
847 struct pci_devres
*dr
, *new_dr
;
849 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
853 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
856 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
859 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
861 if (pci_is_managed(pdev
))
862 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
867 * pcim_enable_device - Managed pci_enable_device()
868 * @pdev: PCI device to be initialized
870 * Managed pci_enable_device().
872 int pcim_enable_device(struct pci_dev
*pdev
)
874 struct pci_devres
*dr
;
877 dr
= get_pci_dr(pdev
);
880 WARN_ON(!!dr
->enabled
);
882 rc
= pci_enable_device(pdev
);
884 pdev
->is_managed
= 1;
891 * pcim_pin_device - Pin managed PCI device
892 * @pdev: PCI device to pin
894 * Pin managed PCI device @pdev. Pinned device won't be disabled on
895 * driver detach. @pdev must have been enabled with
896 * pcim_enable_device().
898 void pcim_pin_device(struct pci_dev
*pdev
)
900 struct pci_devres
*dr
;
902 dr
= find_pci_dr(pdev
);
903 WARN_ON(!dr
|| !dr
->enabled
);
909 * pcibios_disable_device - disable arch specific PCI resources for device dev
910 * @dev: the PCI device to disable
912 * Disables architecture specific PCI resources for the device. This
913 * is the default implementation. Architecture implementations can
916 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
919 * pci_disable_device - Disable PCI device after use
920 * @dev: PCI device to be disabled
922 * Signal to the system that the PCI device is not in use by the system
923 * anymore. This only involves disabling PCI bus-mastering, if active.
925 * Note we don't actually disable the device until all callers of
926 * pci_device_enable() have called pci_device_disable().
929 pci_disable_device(struct pci_dev
*dev
)
931 struct pci_devres
*dr
;
934 dr
= find_pci_dr(dev
);
938 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
941 /* Wait for all transactions are finished before disabling the device */
942 pcie_wait_pending_transaction(dev
);
944 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
945 if (pci_command
& PCI_COMMAND_MASTER
) {
946 pci_command
&= ~PCI_COMMAND_MASTER
;
947 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
949 dev
->is_busmaster
= 0;
951 pcibios_disable_device(dev
);
955 * pcibios_set_pcie_reset_state - set reset state for device dev
956 * @dev: the PCI-E device reset
957 * @state: Reset state to enter into
960 * Sets the PCI-E reset state for the device. This is the default
961 * implementation. Architecture implementations can override this.
963 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
964 enum pcie_reset_state state
)
970 * pci_set_pcie_reset_state - set reset state for device dev
971 * @dev: the PCI-E device reset
972 * @state: Reset state to enter into
975 * Sets the PCI reset state for the device.
977 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
979 return pcibios_set_pcie_reset_state(dev
, state
);
983 * pci_enable_wake - enable PCI device as wakeup event source
984 * @dev: PCI device affected
985 * @state: PCI state from which device will issue wakeup events
986 * @enable: True to enable event generation; false to disable
988 * This enables the device as a wakeup event source, or disables it.
989 * When such events involves platform-specific hooks, those hooks are
990 * called automatically by this routine.
992 * Devices with legacy power management (no standard PCI PM capabilities)
993 * always require such platform hooks. Depending on the platform, devices
994 * supporting the standard PCI PME# signal may require such platform hooks;
995 * they always update bits in config space to allow PME# generation.
997 * -EIO is returned if the device can't ever be a wakeup event source.
998 * -EINVAL is returned if the device can't generate wakeup events from
999 * the specified PCI state. Returns zero if the operation is successful.
1001 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1007 /* Note that drivers should verify device_may_wakeup(&dev->dev)
1008 * before calling this function. Platform code should report
1009 * errors when drivers try to enable wakeup on devices that
1010 * can't issue wakeups, or on which wakeups were disabled by
1011 * userspace updating the /sys/devices.../power/wakeup file.
1014 status
= call_platform_enable_wakeup(&dev
->dev
, enable
);
1016 /* find PCI PM capability in list */
1017 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1019 /* If device doesn't support PM Capabilities, but caller wants to
1020 * disable wake events, it's a NOP. Otherwise fail unless the
1021 * platform hooks handled this legacy device already.
1024 return enable
? status
: 0;
1026 /* Check device's ability to generate PME# */
1027 pci_read_config_word(dev
,pm
+PCI_PM_PMC
,&value
);
1029 value
&= PCI_PM_CAP_PME_MASK
;
1030 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
1032 /* Check if it can generate PME# from requested state. */
1033 if (!value
|| !(value
& (1 << state
))) {
1034 /* if it can't, revert what the platform hook changed,
1035 * always reporting the base "EINVAL, can't PME#" error
1038 call_platform_enable_wakeup(&dev
->dev
, 0);
1039 return enable
? -EINVAL
: 0;
1042 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
);
1044 /* Clear PME_Status by writing 1 to it and enable PME# */
1045 value
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1048 value
&= ~PCI_PM_CTRL_PME_ENABLE
;
1050 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, value
);
1056 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1064 while (dev
->bus
->self
) {
1065 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
1066 dev
= dev
->bus
->self
;
1073 * pci_release_region - Release a PCI bar
1074 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1075 * @bar: BAR to release
1077 * Releases the PCI I/O and memory resources previously reserved by a
1078 * successful call to pci_request_region. Call this function only
1079 * after all use of the PCI regions has ceased.
1081 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1083 struct pci_devres
*dr
;
1085 if (pci_resource_len(pdev
, bar
) == 0)
1087 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1088 release_region(pci_resource_start(pdev
, bar
),
1089 pci_resource_len(pdev
, bar
));
1090 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1091 release_mem_region(pci_resource_start(pdev
, bar
),
1092 pci_resource_len(pdev
, bar
));
1094 dr
= find_pci_dr(pdev
);
1096 dr
->region_mask
&= ~(1 << bar
);
1100 * pci_request_region - Reserved PCI I/O and memory resource
1101 * @pdev: PCI device whose resources are to be reserved
1102 * @bar: BAR to be reserved
1103 * @res_name: Name to be associated with resource.
1105 * Mark the PCI region associated with PCI device @pdev BR @bar as
1106 * being reserved by owner @res_name. Do not access any
1107 * address inside the PCI regions unless this call returns
1110 * Returns 0 on success, or %EBUSY on error. A warning
1111 * message is also printed on failure.
1113 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1115 struct pci_devres
*dr
;
1117 if (pci_resource_len(pdev
, bar
) == 0)
1120 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1121 if (!request_region(pci_resource_start(pdev
, bar
),
1122 pci_resource_len(pdev
, bar
), res_name
))
1125 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1126 if (!request_mem_region(pci_resource_start(pdev
, bar
),
1127 pci_resource_len(pdev
, bar
), res_name
))
1131 dr
= find_pci_dr(pdev
);
1133 dr
->region_mask
|= 1 << bar
;
1138 printk (KERN_WARNING
"PCI: Unable to reserve %s region #%d:%llx@%llx "
1140 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1141 bar
+ 1, /* PCI BAR # */
1142 (unsigned long long)pci_resource_len(pdev
, bar
),
1143 (unsigned long long)pci_resource_start(pdev
, bar
),
1149 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1150 * @pdev: PCI device whose resources were previously reserved
1151 * @bars: Bitmask of BARs to be released
1153 * Release selected PCI I/O and memory resources previously reserved.
1154 * Call this function only after all use of the PCI regions has ceased.
1156 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1160 for (i
= 0; i
< 6; i
++)
1161 if (bars
& (1 << i
))
1162 pci_release_region(pdev
, i
);
1166 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1167 * @pdev: PCI device whose resources are to be reserved
1168 * @bars: Bitmask of BARs to be requested
1169 * @res_name: Name to be associated with resource
1171 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1172 const char *res_name
)
1176 for (i
= 0; i
< 6; i
++)
1177 if (bars
& (1 << i
))
1178 if(pci_request_region(pdev
, i
, res_name
))
1184 if (bars
& (1 << i
))
1185 pci_release_region(pdev
, i
);
1191 * pci_release_regions - Release reserved PCI I/O and memory resources
1192 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1194 * Releases all PCI I/O and memory resources previously reserved by a
1195 * successful call to pci_request_regions. Call this function only
1196 * after all use of the PCI regions has ceased.
1199 void pci_release_regions(struct pci_dev
*pdev
)
1201 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1205 * pci_request_regions - Reserved PCI I/O and memory resources
1206 * @pdev: PCI device whose resources are to be reserved
1207 * @res_name: Name to be associated with resource.
1209 * Mark all PCI regions associated with PCI device @pdev as
1210 * being reserved by owner @res_name. Do not access any
1211 * address inside the PCI regions unless this call returns
1214 * Returns 0 on success, or %EBUSY on error. A warning
1215 * message is also printed on failure.
1217 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1219 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1223 * pci_set_master - enables bus-mastering for device dev
1224 * @dev: the PCI device to enable
1226 * Enables bus-mastering on the device and calls pcibios_set_master()
1227 * to do the needed arch specific settings.
1230 pci_set_master(struct pci_dev
*dev
)
1234 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1235 if (! (cmd
& PCI_COMMAND_MASTER
)) {
1236 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev
));
1237 cmd
|= PCI_COMMAND_MASTER
;
1238 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1240 dev
->is_busmaster
= 1;
1241 pcibios_set_master(dev
);
1244 #ifdef PCI_DISABLE_MWI
1245 int pci_set_mwi(struct pci_dev
*dev
)
1250 int pci_try_set_mwi(struct pci_dev
*dev
)
1255 void pci_clear_mwi(struct pci_dev
*dev
)
1261 #ifndef PCI_CACHE_LINE_BYTES
1262 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1265 /* This can be overridden by arch code. */
1266 /* Don't forget this is measured in 32-bit words, not bytes */
1267 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1270 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1271 * @dev: the PCI device for which MWI is to be enabled
1273 * Helper function for pci_set_mwi.
1274 * Originally copied from drivers/net/acenic.c.
1275 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1277 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1280 pci_set_cacheline_size(struct pci_dev
*dev
)
1284 if (!pci_cache_line_size
)
1285 return -EINVAL
; /* The system doesn't support MWI. */
1287 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1288 equal to or multiple of the right value. */
1289 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1290 if (cacheline_size
>= pci_cache_line_size
&&
1291 (cacheline_size
% pci_cache_line_size
) == 0)
1294 /* Write the correct value. */
1295 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1297 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1298 if (cacheline_size
== pci_cache_line_size
)
1301 printk(KERN_DEBUG
"PCI: cache line size of %d is not supported "
1302 "by device %s\n", pci_cache_line_size
<< 2, pci_name(dev
));
1308 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1309 * @dev: the PCI device for which MWI is enabled
1311 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1313 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1316 pci_set_mwi(struct pci_dev
*dev
)
1321 rc
= pci_set_cacheline_size(dev
);
1325 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1326 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1327 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
1329 cmd
|= PCI_COMMAND_INVALIDATE
;
1330 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1337 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1338 * @dev: the PCI device for which MWI is enabled
1340 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1341 * Callers are not required to check the return value.
1343 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1345 int pci_try_set_mwi(struct pci_dev
*dev
)
1347 int rc
= pci_set_mwi(dev
);
1352 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1353 * @dev: the PCI device to disable
1355 * Disables PCI Memory-Write-Invalidate transaction on the device
1358 pci_clear_mwi(struct pci_dev
*dev
)
1362 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1363 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1364 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1365 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1368 #endif /* ! PCI_DISABLE_MWI */
1371 * pci_intx - enables/disables PCI INTx for device dev
1372 * @pdev: the PCI device to operate on
1373 * @enable: boolean: whether to enable or disable PCI INTx
1375 * Enables/disables PCI INTx for device dev
1378 pci_intx(struct pci_dev
*pdev
, int enable
)
1380 u16 pci_command
, new;
1382 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1385 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1387 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1390 if (new != pci_command
) {
1391 struct pci_devres
*dr
;
1393 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1395 dr
= find_pci_dr(pdev
);
1396 if (dr
&& !dr
->restore_intx
) {
1397 dr
->restore_intx
= 1;
1398 dr
->orig_intx
= !enable
;
1404 * pci_msi_off - disables any msi or msix capabilities
1405 * @dev: the PCI device to operate on
1407 * If you want to use msi see pci_enable_msi and friends.
1408 * This is a lower level primitive that allows us to disable
1409 * msi operation at the device level.
1411 void pci_msi_off(struct pci_dev
*dev
)
1416 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1418 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1419 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1420 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1422 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1424 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1425 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1426 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1430 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1432 * These can be overridden by arch-specific implementations
1435 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1437 if (!pci_dma_supported(dev
, mask
))
1440 dev
->dma_mask
= mask
;
1446 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1448 if (!pci_dma_supported(dev
, mask
))
1451 dev
->dev
.coherent_dma_mask
= mask
;
1458 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1459 * @dev: PCI device to query
1461 * Returns mmrbc: maximum designed memory read count in bytes
1462 * or appropriate error value.
1464 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
1469 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1473 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1477 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
1479 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
1482 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1483 * @dev: PCI device to query
1485 * Returns mmrbc: maximum memory read count in bytes
1486 * or appropriate error value.
1488 int pcix_get_mmrbc(struct pci_dev
*dev
)
1493 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1497 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1499 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
1503 EXPORT_SYMBOL(pcix_get_mmrbc
);
1506 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1507 * @dev: PCI device to query
1508 * @mmrbc: maximum memory read count in bytes
1509 * valid values are 512, 1024, 2048, 4096
1511 * If possible sets maximum memory read byte count, some bridges have erratas
1512 * that prevent this.
1514 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
1516 int cap
, err
= -EINVAL
;
1517 u32 stat
, cmd
, v
, o
;
1519 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
1522 v
= ffs(mmrbc
) - 10;
1524 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1528 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1532 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
1535 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1539 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
1541 if (v
> o
&& dev
->bus
&&
1542 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
1545 cmd
&= ~PCI_X_CMD_MAX_READ
;
1547 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
1552 EXPORT_SYMBOL(pcix_set_mmrbc
);
1555 * pcie_get_readrq - get PCI Express read request size
1556 * @dev: PCI device to query
1558 * Returns maximum memory read request in bytes
1559 * or appropriate error value.
1561 int pcie_get_readrq(struct pci_dev
*dev
)
1566 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1570 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1572 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
1576 EXPORT_SYMBOL(pcie_get_readrq
);
1579 * pcie_set_readrq - set PCI Express maximum memory read request
1580 * @dev: PCI device to query
1581 * @rq: maximum memory read count in bytes
1582 * valid values are 128, 256, 512, 1024, 2048, 4096
1584 * If possible sets maximum read byte count
1586 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
1588 int cap
, err
= -EINVAL
;
1591 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
1594 v
= (ffs(rq
) - 8) << 12;
1596 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1600 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1604 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
1605 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
1607 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
1613 EXPORT_SYMBOL(pcie_set_readrq
);
1616 * pci_select_bars - Make BAR mask from the type of resource
1617 * @dev: the PCI device for which BAR mask is made
1618 * @flags: resource type mask to be selected
1620 * This helper routine makes bar mask from the type of resource.
1622 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
1625 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1626 if (pci_resource_flags(dev
, i
) & flags
)
1631 static void __devinit
pci_no_domains(void)
1633 #ifdef CONFIG_PCI_DOMAINS
1634 pci_domains_supported
= 0;
1638 static int __devinit
pci_init(void)
1640 struct pci_dev
*dev
= NULL
;
1642 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
1643 pci_fixup_device(pci_fixup_final
, dev
);
1648 static int __devinit
pci_setup(char *str
)
1651 char *k
= strchr(str
, ',');
1654 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
1655 if (!strcmp(str
, "nomsi")) {
1657 } else if (!strcmp(str
, "noaer")) {
1659 } else if (!strcmp(str
, "nodomains")) {
1661 } else if (!strncmp(str
, "cbiosize=", 9)) {
1662 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
1663 } else if (!strncmp(str
, "cbmemsize=", 10)) {
1664 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
1666 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
1674 early_param("pci", pci_setup
);
1676 device_initcall(pci_init
);
1678 EXPORT_SYMBOL(pci_reenable_device
);
1679 EXPORT_SYMBOL(pci_enable_device_io
);
1680 EXPORT_SYMBOL(pci_enable_device_mem
);
1681 EXPORT_SYMBOL(pci_enable_device
);
1682 EXPORT_SYMBOL(pcim_enable_device
);
1683 EXPORT_SYMBOL(pcim_pin_device
);
1684 EXPORT_SYMBOL(pci_disable_device
);
1685 EXPORT_SYMBOL(pci_find_capability
);
1686 EXPORT_SYMBOL(pci_bus_find_capability
);
1687 EXPORT_SYMBOL(pci_release_regions
);
1688 EXPORT_SYMBOL(pci_request_regions
);
1689 EXPORT_SYMBOL(pci_release_region
);
1690 EXPORT_SYMBOL(pci_request_region
);
1691 EXPORT_SYMBOL(pci_release_selected_regions
);
1692 EXPORT_SYMBOL(pci_request_selected_regions
);
1693 EXPORT_SYMBOL(pci_set_master
);
1694 EXPORT_SYMBOL(pci_set_mwi
);
1695 EXPORT_SYMBOL(pci_try_set_mwi
);
1696 EXPORT_SYMBOL(pci_clear_mwi
);
1697 EXPORT_SYMBOL_GPL(pci_intx
);
1698 EXPORT_SYMBOL(pci_set_dma_mask
);
1699 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
1700 EXPORT_SYMBOL(pci_assign_resource
);
1701 EXPORT_SYMBOL(pci_find_parent_resource
);
1702 EXPORT_SYMBOL(pci_select_bars
);
1704 EXPORT_SYMBOL(pci_set_power_state
);
1705 EXPORT_SYMBOL(pci_save_state
);
1706 EXPORT_SYMBOL(pci_restore_state
);
1707 EXPORT_SYMBOL(pci_enable_wake
);
1708 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);