4 #include <asm/pgtable.h>
5 #include <asm/cacheflush.h>
8 * Functions to keep the agpgart mappings coherent with the MMU. The
9 * GART gives the CPU a physical alias of pages in memory. The alias
10 * region is mapped uncacheable. Make sure there are no conflicting
11 * mappings with different cachability attributes for the same
12 * page. This avoids data corruption on some CPUs.
16 * Caller's responsibility to call global_flush_tlb() for performance
19 #define map_page_into_agp(page) change_page_attr(page, 1, PAGE_KERNEL_NOCACHE)
20 #define unmap_page_from_agp(page) change_page_attr(page, 1, PAGE_KERNEL)
21 #define flush_agp_mappings() global_flush_tlb()
24 * Could use CLFLUSH here if the cpu supports it. But then it would
25 * need to be called for each cacheline of the whole page so it may
26 * not be worth it. Would need a page for it.
28 #define flush_agp_cache() wbinvd()
30 /* Convert a physical address to an address suitable for the GART. */
31 #define phys_to_gart(x) (x)
32 #define gart_to_phys(x) (x)
34 /* GATT allocation. Returns/accepts GATT kernel virtual address. */
35 #define alloc_gatt_pages(order) \
36 ((char *)__get_free_pages(GFP_KERNEL, (order)))
37 #define free_gatt_pages(table, order) \
38 free_pages((unsigned long)(table), (order))