drivers/ide/atiixp.c

   1 /*
   2  *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
   3  *  Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
   4  */
   5
   6 #include <linux/types.h>
   7 #include <linux/module.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pci.h>
  10 #include <linux/ide.h>
  11 #include <linux/init.h>
  12
  13 #define DRV_NAME "atiixp"
  14
  15 #define ATIIXP_IDE_PIO_TIMING           0x40
  16 #define ATIIXP_IDE_MDMA_TIMING          0x44
  17 #define ATIIXP_IDE_PIO_CONTROL          0x48
  18 #define ATIIXP_IDE_PIO_MODE             0x4a
  19 #define ATIIXP_IDE_UDMA_CONTROL         0x54
  20 #define ATIIXP_IDE_UDMA_MODE            0x56
  21
  22 typedef struct {
  23         u8 command_width;
  24         u8 recover_width;
  25 } atiixp_ide_timing;
  26
  27 static atiixp_ide_timing pio_timing[] = {
  28         { 0x05, 0x0d },
  29         { 0x04, 0x07 },
  30         { 0x03, 0x04 },
  31         { 0x02, 0x02 },
  32         { 0x02, 0x00 },
  33 };
  34
  35 static atiixp_ide_timing mdma_timing[] = {
  36         { 0x07, 0x07 },
  37         { 0x02, 0x01 },
  38         { 0x02, 0x00 },
  39 };
  40
  41 static DEFINE_SPINLOCK(atiixp_lock);
  42
  43 /**
  44  *      atiixp_set_pio_mode     -       set host controller for PIO mode
  45  *      @drive: drive
  46  *      @pio: PIO mode number
  47  *
  48  *      Set the interface PIO mode.
  49  */
  50
  51 static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
  52 {
  53         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  54         unsigned long flags;
  55         int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
  56         u32 pio_timing_data;
  57         u16 pio_mode_data;
  58
  59         spin_lock_irqsave(&atiixp_lock, flags);
  60
  61         pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
  62         pio_mode_data &= ~(0x07 << (drive->dn * 4));
  63         pio_mode_data |= (pio << (drive->dn * 4));
  64         pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
  65
  66         pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
  67         pio_timing_data &= ~(0xff << timing_shift);
  68         pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
  69                  (pio_timing[pio].command_width << (timing_shift + 4));
  70         pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
  71
  72         spin_unlock_irqrestore(&atiixp_lock, flags);
  73 }
  74
  75 /**
  76  *      atiixp_set_dma_mode     -       set host controller for DMA mode
  77  *      @drive: drive
  78  *      @speed: DMA mode
  79  *
  80  *      Set a ATIIXP host controller to the desired DMA mode.  This involves
  81  *      programming the right timing data into the PCI configuration space.
  82  */
  83
  84 static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
  85 {
  86         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  87         unsigned long flags;
  88         int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
  89         u32 tmp32;
  90         u16 tmp16;
  91         u16 udma_ctl = 0;
  92
  93         spin_lock_irqsave(&atiixp_lock, flags);
  94
  95         pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);
  96
  97         if (speed >= XFER_UDMA_0) {
  98                 pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
  99                 tmp16 &= ~(0x07 << (drive->dn * 4));
 100                 tmp16 |= ((speed & 0x07) << (drive->dn * 4));
 101                 pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
 102
 103                 udma_ctl |= (1 << drive->dn);
 104         } else if (speed >= XFER_MW_DMA_0) {
 105                 u8 i = speed & 0x03;
 106
 107                 pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
 108                 tmp32 &= ~(0xff << timing_shift);
 109                 tmp32 |= (mdma_timing[i].recover_width << timing_shift) |
 110                          (mdma_timing[i].command_width << (timing_shift + 4));
 111                 pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
 112
 113                 udma_ctl &= ~(1 << drive->dn);
 114         }
 115
 116         pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);
 117
 118         spin_unlock_irqrestore(&atiixp_lock, flags);
 119 }
 120
 121 static u8 atiixp_cable_detect(ide_hwif_t *hwif)
 122 {
 123         struct pci_dev *pdev = to_pci_dev(hwif->dev);
 124         u8 udma_mode = 0, ch = hwif->channel;
 125
 126         pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
 127
 128         if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
 129                 return ATA_CBL_PATA80;
 130         else
 131                 return ATA_CBL_PATA40;
 132 }
 133
 134 static const struct ide_port_ops atiixp_port_ops = {
 135         .set_pio_mode           = atiixp_set_pio_mode,
 136         .set_dma_mode           = atiixp_set_dma_mode,
 137         .cable_detect           = atiixp_cable_detect,
 138 };
 139
 140 static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
 141         {       /* 0: IXP200/300/400/700 */
 142                 .name           = DRV_NAME,
 143                 .enablebits     = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
 144                 .port_ops       = &atiixp_port_ops,
 145                 .host_flags     = IDE_HFLAG_LEGACY_IRQS,
 146                 .pio_mask       = ATA_PIO4,
 147                 .mwdma_mask     = ATA_MWDMA2,
 148                 .udma_mask      = ATA_UDMA5,
 149         },
 150         {       /* 1: IXP600 */
 151                 .name           = DRV_NAME,
 152                 .enablebits     = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
 153                 .port_ops       = &atiixp_port_ops,
 154                 .host_flags     = IDE_HFLAG_SINGLE | IDE_HFLAG_LEGACY_IRQS,
 155                 .pio_mask       = ATA_PIO4,
 156                 .mwdma_mask     = ATA_MWDMA2,
 157                 .udma_mask      = ATA_UDMA5,
 158         },
 159 };
 160
 161 /**
 162  *      atiixp_init_one -       called when a ATIIXP is found
 163  *      @dev: the atiixp device
 164  *      @id: the matching pci id
 165  *
 166  *      Called when the PCI registration layer (or the IDE initialization)
 167  *      finds a device matching our IDE device tables.
 168  */
 169
 170 static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 171 {
 172         return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL);
 173 }
 174
 175 static const struct pci_device_id atiixp_pci_tbl[] = {
 176         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
 177         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
 178         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
 179         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
 180         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
 181         { 0, },
 182 };
 183 MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
 184
 185 static struct pci_driver atiixp_pci_driver = {
 186         .name           = "ATIIXP_IDE",
 187         .id_table       = atiixp_pci_tbl,
 188         .probe          = atiixp_init_one,
 189         .remove         = ide_pci_remove,
 190         .suspend        = ide_pci_suspend,
 191         .resume         = ide_pci_resume,
 192 };
 193
 194 static int __init atiixp_ide_init(void)
 195 {
 196         return ide_pci_register_driver(&atiixp_pci_driver);
 197 }
 198
 199 static void __exit atiixp_ide_exit(void)
 200 {
 201         pci_unregister_driver(&atiixp_pci_driver);
 202 }
 203
 204 module_init(atiixp_ide_init);
 205 module_exit(atiixp_ide_exit);
 206
 207 MODULE_AUTHOR("HUI YU");
 208 MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
 209 MODULE_LICENSE("GPL");