arch/sh/drivers/pci/pci.c

   1 /*
   2  * arch/sh/drivers/pci/pci.c
   3  *
   4  * Copyright (c) 2002 M. R. Brown  <mrbrown@linux-sh.org>
   5  * Copyright (c) 2004 - 2006 Paul Mundt  <lethal@linux-sh.org>
   6  *
   7  * These functions are collected here to reduce duplication of common
   8  * code amongst the many platform-specific PCI support code files.
   9  *
  10  * These routines require the following board-specific routines:
  11  * void pcibios_fixup_irqs();
  12  *
  13  * See include/asm-sh/pci.h for more information.
  14  *
  15  * This file is subject to the terms and conditions of the GNU General Public
  16  * License.  See the file "COPYING" in the main directory of this archive
  17  * for more details.
  18  */
  19 #include <linux/kernel.h>
  20 #include <linux/pci.h>
  21 #include <linux/init.h>
  22 #include <asm/io.h>
  23
  24 static u8 __init simple_swizzle(struct pci_dev *dev, u8 *pinp)
  25 {
  26         u8 pin = *pinp;
  27
  28         while (dev->bus->parent) {
  29                 pin = pci_swizzle_interrupt_pin(dev, pin);
  30                 /* Move up the chain of bridges. */
  31                 dev = dev->bus->self;
  32         }
  33         *pinp = pin;
  34
  35         /* The slot is the slot of the last bridge. */
  36         return PCI_SLOT(dev->devfn);
  37 }
  38
  39 static int __init pcibios_init(void)
  40 {
  41         struct pci_channel *p;
  42         struct pci_bus *bus;
  43         int busno;
  44
  45 #ifdef CONFIG_PCI_AUTO
  46         /* assign resources */
  47         busno = 0;
  48         for (p = board_pci_channels; p->pci_ops != NULL; p++)
  49                 busno = pciauto_assign_resources(busno, p) + 1;
  50 #endif
  51
  52         /* scan the buses */
  53         busno = 0;
  54         for (p = board_pci_channels; p->pci_ops != NULL; p++) {
  55                 bus = pci_scan_bus(busno, p->pci_ops, p);
  56                 busno = bus->subordinate + 1;
  57         }
  58
  59         pci_fixup_irqs(simple_swizzle, pcibios_map_platform_irq);
  60
  61         return 0;
  62 }
  63 subsys_initcall(pcibios_init);
  64
  65 /*
  66  *  Called after each bus is probed, but before its children
  67  *  are examined.
  68  */
  69 void __devinit __weak pcibios_fixup_bus(struct pci_bus *bus)
  70 {
  71         pci_read_bridge_bases(bus);
  72 }
  73
  74 void pcibios_align_resource(void *data, struct resource *res,
  75                             resource_size_t size, resource_size_t align)
  76                             __attribute__ ((weak));
  77
  78 /*
  79  * We need to avoid collisions with `mirrored' VGA ports
  80  * and other strange ISA hardware, so we always want the
  81  * addresses to be allocated in the 0x000-0x0ff region
  82  * modulo 0x400.
  83  */
  84 void pcibios_align_resource(void *data, struct resource *res,
  85                             resource_size_t size, resource_size_t align)
  86 {
  87         if (res->flags & IORESOURCE_IO) {
  88                 resource_size_t start = res->start;
  89
  90                 if (start & 0x300) {
  91                         start = (start + 0x3ff) & ~0x3ff;
  92                         res->start = start;
  93                 }
  94         }
  95 }
  96
  97 int pcibios_enable_device(struct pci_dev *dev, int mask)
  98 {
  99         u16 cmd, old_cmd;
 100         int idx;
 101         struct resource *r;
 102
 103         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 104         old_cmd = cmd;
 105         for(idx=0; idx<6; idx++) {
 106                 if (!(mask & (1 << idx)))
 107                         continue;
 108                 r = &dev->resource[idx];
 109                 if (!r->start && r->end) {
 110                         printk(KERN_ERR "PCI: Device %s not available because "
 111                                "of resource collisions\n", pci_name(dev));
 112                         return -EINVAL;
 113                 }
 114                 if (r->flags & IORESOURCE_IO)
 115                         cmd |= PCI_COMMAND_IO;
 116                 if (r->flags & IORESOURCE_MEM)
 117                         cmd |= PCI_COMMAND_MEMORY;
 118         }
 119         if (dev->resource[PCI_ROM_RESOURCE].start)
 120                 cmd |= PCI_COMMAND_MEMORY;
 121         if (cmd != old_cmd) {
 122                 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
 123                        pci_name(dev), old_cmd, cmd);
 124                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 125         }
 126         return 0;
 127 }
 128
 129 /*
 130  *  If we set up a device for bus mastering, we need to check and set
 131  *  the latency timer as it may not be properly set.
 132  */
 133 static unsigned int pcibios_max_latency = 255;
 134
 135 void pcibios_set_master(struct pci_dev *dev)
 136 {
 137         u8 lat;
 138         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 139         if (lat < 16)
 140                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 141         else if (lat > pcibios_max_latency)
 142                 lat = pcibios_max_latency;
 143         else
 144                 return;
 145         printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
 146                pci_name(dev), lat);
 147         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 148 }
 149
 150 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
 151 {
 152         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 153 }
 154
 155 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
 156 {
 157         resource_size_t start = pci_resource_start(dev, bar);
 158         resource_size_t len = pci_resource_len(dev, bar);
 159         unsigned long flags = pci_resource_flags(dev, bar);
 160
 161         if (unlikely(!len || !start))
 162                 return NULL;
 163         if (maxlen && len > maxlen)
 164                 len = maxlen;
 165
 166         /*
 167          * Presently the IORESOURCE_MEM case is a bit special, most
 168          * SH7751 style PCI controllers have PCI memory at a fixed
 169          * location in the address space where no remapping is desired
 170          * (typically at 0xfd000000, but is_pci_memaddr() will know
 171          * best). With the IORESOURCE_MEM case more care has to be taken
 172          * to inhibit page table mapping for legacy cores, but this is
 173          * punted off to __ioremap().
 174          *                                      -- PFM.
 175          */
 176         if (flags & IORESOURCE_IO)
 177                 return ioport_map(start, len);
 178         if (flags & IORESOURCE_MEM)
 179                 return ioremap(start, len);
 180
 181         return NULL;
 182 }
 183 EXPORT_SYMBOL(pci_iomap);
 184
 185 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 186 {
 187         iounmap(addr);
 188 }
 189 EXPORT_SYMBOL(pci_iounmap);